JP2001168199A - Automatic layout and wiring method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an automatic layout and wiring method for semiconductor devices which enables reduction of delay in a route which does not satisfy the delay standard of a semiconductor integrated circuit device where elements are laid out and wired. SOLUTION: This method is based on the first step (1-12) of determining a wiring length from the output end of a semiconductor element which indicates a position where a buffer should be inserted, and judging whether coordinates can be laid out in positions where buffers do not overlap with existing elements within a buffer insertion range; the second step (1-13) of laying out and wiring buffers in coordinates in the case where coordinates can be laid out; and the third step ((13-1)-(13-6)) of setting 1G in the vicinity of a wiring present within a buffer insertion range on a wiring where buffers are to be inserted, and searching for a position where buffers to be inserted in the vicinity of this wiring do not overlap with the existing elements in the case where coordinates cannot be laid out in positions where buffers do not overlap with the existing elements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing method for a semiconductor device, and more particularly to an automatic placement and routing method for a semiconductor device that automatically executes placement and wiring of elements in an LSI.

[0002]

2. Description of the Related Art Large scale integrated circuits (Large Scale Integrat)
ion; hereinafter, referred to as LSI).
With the advance of miniaturization, the operation speed of the elements constituting the LSI has been increased. On the other hand, as the scale of the LSI increases, the parasitic capacitance and the parasitic resistance of the wiring in the LSI increase. Due to the increase in the parasitic capacitance and the parasitic resistance of the wiring in the LSI, the signal delay due to the length of the wiring in the LSI has recently become so large that it cannot be ignored. In a recent technology for designing an LSI product, the timing of a signal in the LSI is corrected by using a technique called IPO (In-Place-Optimization) in a layout process. In the timing correction of the signal in the LSI using the IPO, a buffer is inserted into a wiring that does not satisfy the delay standard of the signal in the LSI. That is, the delay in the signal in the LSI due to the insertion of this buffer is reduced.

A general conventional automatic placement and routing method for a semiconductor device will be described with reference to FIGS. FIG.
FIG. 1 shows a circuit diagram in the case where there is a wiring that does not satisfy a delay standard in a conventional automatic placement and routing method of a semiconductor device. FIG. 10 is a circuit diagram in which a buffer is inserted at a position close to the first flip-flop in the conventional method of automatically placing and routing a semiconductor device. FIG. 11 is a circuit diagram in which a buffer is inserted at a position far from the first flip-flop in the conventional automatic placement and routing method for a semiconductor device. From the output terminal (hereinafter referred to as Q) of the first flip-flop (hereinafter referred to as F / F-1) (7-1) to the input of the second flip-flop (hereinafter referred to as F / F-2) (7-2) When the route (7-3) (wiring length 1) to the end (hereinafter referred to as D) is a wiring that does not satisfy the delay standard, the route (7-3)
It is necessary to reduce the delay of the signal in and to satisfy the delay standard. The buffer ((8-3) or (9-3) is used to reduce the signal delay in this path (7-3) and satisfy the delay standard.
-3)) is inserted. In FIG. 10 or FIG.
(8-4) and (9-4), which are the wiring length l1 from Q of 1 ((8-1) or (9-1)) to the buffer ((8-3) or (9-3)) Are different. Further, the buffer ((8-3) or (9-3)) transfers the F / F-2 ((8-
2) or (9-2)), which is different from (8-5) and (9-5), which are the wiring length l-l1 to D. There is no different circuit portion between the circuit diagrams of FIGS. 10 and 11.

The use of this general conventional automatic placement and routing method for a semiconductor device causes a problem that the TAT (turn around time) for executing timing correction of signals in an LSI becomes long. The reason why the TAT becomes long will be described with reference to FIGS. The signal delay value in the circuit diagram of FIG. 9 is obtained by the following equation (Equation 1). tpd (D1) = tld + R1 × (Cld + Co × l / 2) + Ro × Co × l 2/2 ( 1) where, tld is F / F-1 element itself delay value, R1 is F / F-1 device Its own output resistance, Ro is the wiring resistance per unit wiring length, Co is the capacitance per unit wiring length, Cld
Is the input capacitance of the next element. An expression in which (Equation 1) is separated into delay types and displayed is shown in the following expression (Equation 2). tpd (D1) = tld + R1 × Cld + (R1 × Co × l / 2 + Ro × Co × l 2/2) ( Equation 2) in order from the first term on the right side in (Equation 2), elements themselves delay value (tld) , Delay value (R1 × C
ld), the delay value due to the wiring capacitance (R1 × Co × 1/2/2 +
A ^{Ro × Co × l 2/2} ).

The signal delay value in the circuit shown in FIG. 10 is shown in the following equation (Equation 3) (the corresponding number in FIG. 10 is (8-x), and the number corresponding to the corresponding number in FIG. 11 is (9-x). x), the case of Fig. 11 is the same as that of Fig. 10. Here, x is a natural number (1, 2, 3, 3).
…))). tpd (D2) = tld1 + R1 × (Co × l1 / 2 + Cin) + Co × Ro × (l1) 2/2 + tld2 + R2 × (Co × (l-l1) / 2 + Cld) + Co × Ro × (l-l1) 2/2 ( Where tld2 is a delay value specific to the buffer, Cin is the input capacity of the buffer (8-3), and Cld is F / F-2 (8
-2) input capacitance, R2 is the output resistance of the buffer (8-3), and l1 is the Q / F of the F / F-1 (8-1).
The wiring length (8-4) up to -3) is shown. In (Equation 3), the right side is the buffer (8) from the Q of F / F-1 (8-1).
-3) (tld1 + R1 × (Co × 11 /
2 + Cin) + Co × Ro × ( the ^l1) 2/2), buffer (delay value from 8-3) to D of F / F-2 (8-2) (tld2 + R2 × (Co × (l-l1) / 2 + C
shows the sum of the ld) + Co × Ro × ( l-l1) 2/2). The following equation (Equation 4) shows the equation obtained by dividing (Equation 3) into the types of delay. tpd (D2) = (tld1 + tld2) + (R1 × Cin + R2 × Cld) + {R1 × Co × l1 / 2 + Ro × Co × (l1) 2/2 + R2 × Co × (l-l1) / 2 + Ro × Co × ( ^{l-l1) 2/2}} ( equation 4) (in order from the first term to term enclosed in tld1 and parentheses in the right side in equation 4), the element itself delay value (tld1 +
tld2), the delay value due to the next stage input capacitance (R1 × Cin
+ R2 × Cld), delay value due to wiring capacitance (R1 × Co
× l1 / 2 + Ro × Co × (l1) 2/2 + R2 × Co
× (l−11) / 2 + Ro × Co × (l−11) ² /
2｝). Further, as is apparent from (Equation 4), the part of the delay value due to the next stage input capacitance and the delay value of the element itself are constant independently of the change in the wiring length l1.

In FIG. 10, assuming that the length of the buffer insertion position 11 is “0”, the delay value (tpd (D2)) due to the wiring capacitance is calculated by the equation (4) according to F / F-1 (8-1) itself. The delay value (tld1), the delay value (R1 × Cin) relating to the input capacity of the buffer (8-3) based on the F / F-1 (8-1), and the delay value of the buffer (8-3) itself. Delay value (tld2) and delay value (R2 × Cld) due to input capacitance of next stage based on buffer (8-3)
And the delay value due to the wiring capacitance (R2 × Co × 1/2/2 + Ro)
× the sum of the Co × ^l 2/2). Usually, since R2 << R1, the delay value tpd (D2) is almost always smaller than the delay value tpd (D1) when no buffer is inserted. On the other hand, assuming that the length of the buffer insertion position 11 in FIG. 11 is “1”, the delay value (tpd (D2)) due to the wiring capacitance is expressed by F / F−1 according to (Equation 4).
(8-1) own delay value (tld1) and F / F-1
The delay value (R1 × Cin) relating to the input capacity of the buffer when (8-1) is used as a reference, the delay value (tld2) of the buffer (8-3) itself, and the buffer (8-3) are used as references. (R2 × Cl)
d) and all wiring delay values (R1 × Co × 1/2 + Ro)
× the sum of the Co × ^l 2/2). This case is the same as the case of FIG. 9 where a buffer delay is added.
The delay value due to the wiring capacitance is larger than the delay value tpd (D1) when no buffer is inserted. Therefore, a part where the delay value due to the wiring capacitance becomes constant even if the wiring length changes in (Equation 4) is added, and the characteristic as shown in FIG. 12 is obtained. (10-1) in FIG. 12 is a state before the buffer is inserted as shown in FIG. 9, and the delay time tD does not satisfy the delay standard. FIG. 12 (10-2) shows F / F-1 ((8-1) or (9-
1)) Q to buffer ((8-3) or (9-3))
This shows the characteristics when the buffer (8-3) is inserted at the position A where the wiring length is 11 (11 is a value close to zero). Further, FIG. 12 (10-3) shows the F / F-
From Q of 1 ((8-1) or (9-1)) to the buffer ((8-3) or (9-3)), a buffer is provided at a position B where the wiring length is l1 (l is a value close to l). The following shows characteristics when (9-3) is inserted. In this case, the delay value becomes larger than before the buffer is inserted. Also, a source element such as F
FIG. 13 shows the drive characteristics of the / F-1 (11-1) and the buffer (11-2). According to this drive characteristic, the amount by which the delay value is reduced changes depending on the position where the buffer is inserted. Therefore, it is understood that it is necessary to limit the arrangement range of the insertion buffer.

The operation of a general conventional automatic placement and routing method for a semiconductor device will be described in order with reference to a flowchart. FIG. 14 shows a flow chart of a conventional automatic placement and routing method for a semiconductor device. FIG. 14 is a flowchart for inserting a buffer into a wiring that does not satisfy the delay standard according to the conventional method. 1. The semiconductor circuit elements are arranged and wired based on a list (hereinafter referred to as a netlist) (12-1) showing how the semiconductor circuit elements are arranged and wired. Data indicating how they are arranged and wired above (hereinafter referred to as layout data)
(12-3) is created. Next, delay information (12-5) is created from the layout data (12-3) and the delay library (12-4) indicating delay values of circuit elements and wiring on the circuit. 2. The critical path timing standard (12-6) indicating the maximum allowable delay value and the delay information (12-5) are compared with each other to calculate the wiring that does not satisfy the delay standard, Is corrected (12-7) to insert a buffer into a wire that does not satisfy the condition (1), and a corrected netlist (12-8) is created. 3. Based on the corrected netlist (12-8) and the layout data (12-3), a coordinate at which a buffer can be inserted on a wiring that does not satisfy the delay standard is searched, and relocation wiring (12-9) is performed. . At this point, the position where the buffer is to be inserted has not been specified, so that the expected effect may not be obtained depending on the position where the buffer is inserted. 4. Layout data (re-layout data) (1
2-10) is created, and the re-layout data (12-
10) and the delay library (12-4) to generate the re-delay information (12-11). 5. Finally, the critical path timing standard (12
-6) is checked (12-12), and if there is a delay wiring that does not satisfy the standard, the above method is repeated from netlist correction (12-7). If all the wirings satisfy the standard, the automatic placement and routing method of the semiconductor device ends.

However, in the conventional automatic placement and routing method of a semiconductor device described above, for example, in a case where a buffer of 100,000 gates is inserted for every 3,000,000 gates in an actual 0.25 μmL SI product, the signal delay standard in the LSI is required. Will be corrected. As described above, since the delay standard is used for all the wirings that do not satisfy the delay standard, the timing correction using the IPO is repeated many times, and there is a problem that the TAT becomes long. In addition, correcting all the wirings that do not satisfy the delay standard is the biggest factor that increases the TAT. On the other hand, even if processing is performed to correct placement and routing automatically for a layout that has been corrected using IPO and completed once, the buffer is not placed at the expected position on the wiring in the actual placement and routing. Almost impossible. Therefore, there are portions to be corrected that do not satisfy the delay standard. Therefore, it is necessary to perform the IPO correction again, and the TA for correcting the timing of the signal in the LSI is required.
There is a problem that T becomes long.

For the purpose of solving the above problems,
There is an automatic layout method for a semiconductor device described in Japanese Patent Publication No. 2739843. This patent publication No. 27398
According to the invention described in No. 43, when a buffer is inserted into a critical net after placement and routing in a semiconductor device, a function cell, a buffer, a wiring, and the like are provided for the purpose of reducing the delay amount of the critical net. It is expected that it is possible to realize an automatic layout method of a semiconductor device in which the optimum insertion position of the buffer can be clearly set and the arrangement and wiring can be performed, while taking into account the real circuit factors caused by the above. You.

[0010]

However, Patent Publication No. 2
In the automatic layout method for a semiconductor device described in US Pat. No. 7,398,843, the optimum position is one point. Therefore, it is difficult to position and wire the optimum position in a semiconductor integrated circuit device that has already been arranged and wired, and it is easy to execute. It can be difficult.

In view of the above-mentioned problems in the prior art, the present invention provides an automatic placement and routing method for a semiconductor device capable of reducing a delay in a routing path that does not satisfy a delay standard of a semiconductor integrated circuit device in which elements are placed and wired. The purpose is to provide.

[0012]

According to the first aspect of the present invention, there is provided an automatic placement and routing method for a semiconductor device, wherein a critical path timing standard indicating a maximum delay value, which is a maximum allowable delay value, is used. A modified netlist indicating a list in which a buffer is inserted into a wiring that is not satisfied, layout data indicating how semiconductor circuit elements are arranged and wired on a circuit, and circuit blocks in the netlist. A first procedure for calculating a delay value in the wiring that does not satisfy the critical path timing standard by using a block library having characteristics; and a wiring from an output end of one semiconductor element indicating a position where a buffer is to be inserted. Determine the length, calculate the coordinates where the buffer can be inserted, and calculate the buffer in the buffer insertion range where the coordinates were calculated. The second step is to determine whether coordinates can be placed at a position that does not overlap with existing elements, and if so, to place and wire a buffer at that coordinate, If it is impossible to arrange coordinates at a position that does not overlap with the element, 1G, which is the minimum unit for arranging the semiconductor element on the wiring into which the buffer is to be inserted, is set to 1G of the wiring existing within the buffer insertion range. A third procedure to search for a position where the buffer to be inserted in the vicinity of the wiring does not overlap with the existing element by setting it near, and placing the buffer at that position and wiring it, and all those that do not meet the delay standard It is determined whether or not the buffer has been inserted into the wiring of all lines, and the procedure from the first step is repeated until the buffer is inserted into all the wirings that do not satisfy the delay specification. And wherein the Succoth.

Therefore, according to the method of automatically placing and routing a semiconductor device according to the first invention of the present application, the position at which a buffer is inserted on a wiring that does not satisfy the delay standard is determined by the delay value of the source-side element itself and the delay value due to the wiring load. By arranging and wiring a buffer for a wiring length in a range larger than that of the above, it is possible to correct the delay standard.
In addition, since a correction that satisfies the delay standard can be made with a single correction without having to make another IPO correction, a short TA
T can be realized.

The automatic placement and routing method for a semiconductor device according to the second invention of the present application is directed to the automatic placement and routing method for a semiconductor device according to the first invention of the present application, which searches for a position where a buffer in the vicinity of the wiring does not overlap an existing element. The third procedure is a minimum unit for arranging a semiconductor element on a wiring into which a buffer is to be inserted, at a position on the + side and at a right angle to the wiring and at a distance from the wiring by a predetermined length. The first procedure is to search for the coordinates of the position where the buffer does not overlap the existing element within the buffer insertion range in parallel with the wiring at the predetermined position, and there are the coordinates where the buffer can be inserted. If this is the case, terminate this procedure and search for wiring that does not meet the other delay specifications. A second procedure of setting 1G at a position separated by a length and searching for coordinates of a position where the buffer does not overlap an existing element in the buffer insertion range in parallel with a wiring at a predetermined position, and inserting a buffer. If there are possible coordinates, terminate this procedure and search for wiring that does not meet other delay standards. If the above procedure does not make it possible to place the buffer overlapping existing elements, In the first and second procedures, the length at which 1 G separates from the wiring is increased, and the coordinates of the position where the buffer does not overlap the existing element within the buffer insertion range are searched in parallel with the wiring at the predetermined position. It is characterized in that three procedures are set.

Therefore, according to the semiconductor device automatic placement and routing method of the second invention of the present application, the coordinates of a position where the buffer does not overlap the existing element are searched in parallel with the wiring at a position on the + side with respect to the wiring. . Next, the coordinates of a position where the buffer does not overlap the existing element are searched in parallel with the wiring on the negative side of the wiring. Then, by changing the distance between the wiring and the position to be searched, it is possible to find the coordinates of the position in the buffer insertion range that does not overlap with the existing element. Here, the predetermined length is a length in units of a certain length. For example, the length is in units of 1 G. In the present invention, when the number of times this procedure is executed is the nth time, the n unit length (nG in the example shown here) becomes the predetermined length at that number.

The automatic placement and routing method for a semiconductor device according to the third invention of the present application is directed to the automatic placement and routing method for a semiconductor device according to the first invention of the present application, which searches for a position where a buffer in the vicinity of the wiring does not overlap an existing element. The third procedure is a minimum unit for arranging a semiconductor element on a wiring into which a buffer is to be inserted, at a position perpendicular to the wiring and on the + side and away from the wiring by a predetermined length. Is set, and the first step of searching for coordinates at a position where the buffer does not overlap an existing element within the buffer insertion range, and if there are coordinates at which the buffer can be inserted, this step is terminated. Search for wiring that does not meet the other delay specifications, and if it is not possible to place the buffer so that it overlaps with the existing elements, a position symmetrical to the wiring (the negative side) Position of There is a second procedure for searching for coordinates at a position where the buffer does not overlap an existing element within the buffer insertion range, and a coordinate at which a buffer can be inserted. In this case, terminate this procedure and search for wiring that does not meet the other delay specifications. If the above procedure does not make it possible to place the buffer so that it overlaps the existing elements, the first and second procedures shall be performed. In the above, the third step of searching the coordinates of the position where the buffer does not overlap the existing element in parallel with the wiring in the buffer insertion range, and if there is the coordinates where the buffer can be inserted, this step is ended. Then, search for wiring that does not meet other delay standards, and if it is not possible to place the buffer so that it overlaps with the existing elements even by the third procedure, perform wiring in the first and second procedures. By increasing the length of G is separated and sets a fourth procedure for the first and second and third steps.

Therefore, according to the method of automatically placing and routing a semiconductor device according to the third aspect of the present invention, the coordinates of a position where the buffer does not overlap the existing element at the position on the + side with respect to the wiring are searched. Next, the coordinates of the position where the buffer does not overlap with the existing element are searched for at a position (position on the minus side) symmetrical with respect to the wiring and the position searched one step before. Then, the above procedure is executed at a position where the parallel movement is performed along the wiring. Further, the above procedure is executed while gradually increasing the distance of the search position from the wiring. With the above method, it becomes possible to search all the areas within the buffer insertion range for coordinates of positions that do not overlap with existing elements.

The automatic placement and routing method for a semiconductor device according to the fourth invention of the present application is directed to the automatic placement and routing method for a semiconductor device according to the first invention of the present application, which searches for a position where a buffer in the vicinity of the wiring does not overlap an existing element. In the third procedure, n (n
Is a natural number), and 1 is searched for a buffer-insertable coordinate on the wiring within the buffer insertion range, and if there is a buffer-insertable coordinate, this procedure is performed. Search for wiring that does not satisfy the other delay standard, and if there is no coordinate at which a buffer can be inserted, set the search start position at one end within the buffer insertion range and go to the second procedure below. It is possible to insert the buffer by moving in the buffer insertion range by 1 G in parallel with the wiring at a position + nG away from the wiring (one direction away from the wiring is defined as a plus (+) direction) at the position + nG away from the wiring. The second step of searching for coordinates, and if there are coordinates that can insert a buffer, terminate this procedure and search for wiring that does not meet other delay standards, and insert a buffer. If there is no possible coordinate, the position away from the wiring by -nG (the other direction away from the wiring, that is, the direction opposite to the + direction is defined as a minus (-) direction) is set in the buffer insertion range by 1 G in parallel with the wiring. The third step of moving and searching for coordinates where a buffer can be inserted, and if there are coordinates where a buffer can be inserted, terminate this procedure and route the wiring that does not meet other delay standards And if there is no coordinate at which a buffer can be inserted, a fourth procedure is set, where n is set to n + 1 and the procedure returns to the second procedure.

Therefore, according to the semiconductor device automatic placement and routing method of the fourth invention of the present application, coordinates at which a buffer can be inserted are searched for on the wiring within the buffer insertion range. Next, the coordinates of a position where the buffer does not overlap the existing element at a position + nG away from the wiring and parallel to the wiring are searched. Next, the coordinates of a position where the buffer does not overlap the existing element at a position + nG away from the wiring and parallel to the wiring are searched. Next, by setting n to n + 1 and returning to the above-described second procedure, it becomes possible to find the coordinates of a position in the buffer insertion range that does not overlap with an existing element.

According to a fifth aspect of the present invention, there is provided an automatic placement and routing method for a semiconductor device according to the first aspect of the present invention, which searches for a position where a buffer in the vicinity of a wiring does not overlap an existing element. In the third procedure, n (n
Is a natural number), and 1 is searched for a buffer-insertable coordinate on the wiring within the buffer insertion range, and if there is a buffer-insertable coordinate, this procedure is performed. Search for wiring that does not satisfy the other delay standard, and if there is no coordinate at which a buffer can be inserted, set the search start position at one end within the buffer insertion range and go to the second procedure below. If there is a first step to proceed and if there are coordinates where a buffer can be inserted, terminate this procedure and search for wiring that does not meet other delay standards, and find the coordinates where a buffer can be inserted. If not, a second procedure of searching for coordinates where a buffer can be inserted at a position + nG away from the wiring (one direction away from the wiring is defined as a plus (+) direction), and inserting a buffer If there is a coordinate that can be used, this procedure is terminated and a wiring that does not satisfy another delay standard is searched. If there is no coordinate that can insert a buffer, a position -nG away from the wiring is searched. A third procedure for searching for coordinates where a buffer can be inserted in the other direction away from the wiring, that is, the direction opposite to the + direction is defined as a minus (-) direction, and the buffer can be inserted. If there are coordinates, this procedure is terminated and a search is made for wiring that does not satisfy other delay standards. If there are no coordinates where a buffer can be inserted in the searched area, the buffer insertion range In the case of moving by 1 G in parallel with the wiring and returning to the second procedure, moving by 1 G in parallel with the wiring and deviating from the buffer insertion range, the fourth procedure to proceed to the next fifth procedure, And setting a fifth procedure returns to the second step and begin the search at one end of the § insertion range.

Therefore, according to the method of automatically placing and routing a semiconductor device according to the fifth aspect of the present invention, coordinates at which a buffer can be inserted are searched for on the wiring within the buffer insertion range. If there is no coordinate at which a buffer can be inserted, a search start position is set at one end within the buffer insertion range, and the procedure proceeds to the next step. Next, at a position + nG away from the wiring, a coordinate at which a buffer can be inserted is searched. Next, a search is made for coordinates where a buffer can be inserted at a position -nG away from the wiring. Next, by moving by 1 G in parallel with the wiring and setting n to n + 1 and returning to the above-described second procedure, it is possible to find the coordinates of a position in the buffer insertion range that does not overlap the existing element.

According to a sixth aspect of the present invention, there is provided an automatic placement and routing method for a semiconductor device according to the first aspect of the present invention, which searches for a position where a buffer in the vicinity of a wiring does not overlap an existing element. The order in which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range is searched in the first step, and the wiring is divided in one of two regions divided by the wiring. A second step of searching for a coordinate at which a buffer can be inserted from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the other, in the other area of the area divided into two by the wiring And a third step of searching for coordinates at which a buffer can be inserted from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the wiring, and Gradually lengthened again second step a predetermined fixed distance from the wiring in the second step and the third step until it finds can coordinate to insert §, characterized in that the process proceeds to the third step.

Therefore, according to the automatic placement and routing method for a semiconductor device according to the sixth aspect of the present invention, a coordinate at which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range is searched. Next, in one area of the area divided into two by the wiring, a coordinate that allows a buffer to be inserted from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the wiring is searched. . Next, in the other area of the area divided into two parts by the wiring, a coordinate which can insert a buffer from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the wiring is searched. . By gradually increasing the predetermined distance from the wiring in the second and third procedures until the coordinates at which a buffer can be inserted are found, and then proceeding to the second and third procedures again, It is possible to find the coordinates of a position that does not overlap with the existing element. Here, the predetermined constant distance is a length in units of a certain length. For example, the distance is a unit of 1 G.

The automatic placement and routing method for a semiconductor device according to the seventh aspect of the present invention is directed to the automatic placement and routing method for a semiconductor device according to the first aspect of the present invention, which searches for a position where a buffer near a wiring does not overlap an existing element. The order in which the first step of searching for a coordinate at which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range and the end of one of two areas divided by the wiring are determined. A second step of retrieving coordinates at which a buffer can be inserted within a buffer insertion range at a position separated by a predetermined fixed distance from the wiring, and at one end of the other area of the area divided into two by the wiring, A third step of searching for a coordinate at which a buffer can be inserted within a buffer insertion range at a position separated by a predetermined fixed distance from the wiring, and a second step and a third step. Then, at a position moved a predetermined distance from one end to the other end in the buffer insertion range, a second process and a fourth process for proceeding to the third process are set again to insert a buffer in the buffer insertion range. The method is characterized in that a predetermined constant distance from the wiring is gradually increased in the fourth process until a possible coordinate is found, and the process proceeds to the second, third, and fourth processes again.

Therefore, according to the automatic placement and routing method for a semiconductor device according to the seventh aspect of the present invention, a coordinate at which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range is searched. Next, at one end of one of the regions divided into two by the wiring, a coordinate at which a buffer can be inserted within a buffer insertion range at a position separated by a predetermined fixed distance from the wiring is searched. Next, at one end of the other area of the area divided by the wiring, coordinates are searched for a buffer into which a buffer can be inserted within a buffer insertion range at a position separated by a predetermined fixed distance from the wiring. Next, in the second and third procedures, at the position moved a predetermined distance from the one end to the other end within the buffer insertion range, the procedure proceeds to the second and third procedures again, so that all of the buffers within the buffer insertion range are obtained. With respect to the area, it is possible to search all over the coordinates of the position that does not overlap with the existing elements.

The automatic placement and routing method for a semiconductor device according to the eighth aspect of the present invention is the same as the automatic placement and routing method for a semiconductor device according to any one of the first to seventh aspects of the present invention. Wiring length (1) from one end to the input end of another semiconductor element, wiring length (11) from the output end of one semiconductor element to the inserted buffer input, parasitic capacitance per unit wiring length (Co), unit wiring Wiring resistance per length (R
o), the delay value (tld1) of one semiconductor element itself, the output resistance (R1) of one semiconductor element, the output resistance of a buffer (R2), the input capacitance (Cin) of a buffer, and the input capacitance (Cld) of another semiconductor element ), The delay value of the buffer itself (tl
d2), the condition is that the delay value tPD after inserting the buffer is smaller than the delay standard tPD0. tPD0> tPD = tld1 + R1 × (Co × 1/2)
+ Cin) + Ro × Co × (l1) 2/2 + tld2 +
R2 × {Co × (l-11) / 2 + Cld} + Ro × C
by o × (l-l1) 2 /2 conditions, and obtains the wiring length l1 is a length limit that can be inserted buffer.

Therefore, according to the method of manufacturing an automatic placement and routing method for a semiconductor device according to the eighth aspect of the present invention, the buffer length can be inserted by comparing the delay value tPD after the insertion of the buffer with the delay standard tPD0. Is obtained. The wiring length l1 makes it possible to clarify the range of positions where a buffer satisfying the delay standard can be inserted.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment An automatic placement and routing method for a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. Figure 1
5 is a flowchart of automatically inserting a buffer into a wiring that does not satisfy a delay standard according to the present invention. First, an outline of a procedure of an automatic placement and routing method for a semiconductor device according to the present embodiment will be described. 1. The placement and wiring (1-2) is performed based on the netlist (1-1), which is a list indicating how to place and route the semiconductor circuit elements, and how the semiconductor circuit elements are placed on the circuit after the placement and wiring. The layout data (1-3), which is data indicating whether or not wiring has been performed, is created. Next, delay information (1-5) is created based on the layout data (1-3) and a delay library (1-4) indicating delay values of circuit elements and wiring on a circuit. 2. The wiring which does not satisfy the delay standard is calculated based on the critical path timing standard (1-6) indicating the maximum delay value which is the maximum allowable delay value and the delay information (1-5). A netlist correction (1-7) for inserting a buffer into a non-existing wiring is performed to create a corrected netlist (1-8). 3. Block library showing circuit block characteristics in netlist (1-10), modified netlist (1-8)
Then, based on the layout data (1-3), the delay parameter of the source element and the buffer on the wiring that does not satisfy the delay standard is extracted (1-9), and the range in which the buffer is inserted is calculated (1-11). 4. It is determined whether or not the buffer can be arranged at coordinates that do not overlap the existing elements on the wiring that does not satisfy the delay standard and within the range where the buffer is inserted (1-12). Next, the coordinates at which the buffer can be arranged without overlapping the existing elements are given as the arrangement coordinates of the buffer, and the arrangement and wiring are performed (1-13). 5. On the other hand, if there is another element or wiring other than this wiring path and it cannot be arranged overlapping with the buffer, the buffer determined in (1-11) is inserted in parallel on both sides of the wiring that does not satisfy the delay standard. , Search for coordinates where existing elements and buffers do not overlap. Then, it is given as the arrangement coordinates of the buffer (1-14), and the buffer is arranged and wired (1-13). 6. After the buffer is completely inserted into all the wirings that do not satisfy the delay standard (1-15), layout data (relayout data) (1-16) is created again. 7. Next, the re-layout data (1-16) and the delay library (1-4) are used to generate the re-delay information (1--1).
17) is created and it is confirmed whether the critical path timing standard (1-6) is satisfied (1-18).
With procedures.

A procedure for calculating a buffer insertion position in the automatic placement and routing method for a semiconductor device according to the present embodiment will be described with reference to FIGS. 2 to 5 and FIGS. FIG. 2 is a diagram illustrating a state in which a buffer is arranged in a range where a calculated buffer on a wiring that does not satisfy a delay standard is inserted according to the present invention, and the buffer overlaps with an existing element in which a semiconductor element is arranged. FIG. 3 is a diagram of an embodiment in which a buffer is arranged in the vicinity of a delay line because a buffer cannot be arranged in a range where a calculated buffer on a line that does not satisfy the delay standard is inserted according to the present invention. The reason why the buffer cannot be arranged in the range where the calculated buffer is inserted on the wiring that does not satisfy the delay standard is that another element other than this wiring path is already arranged and wired. FIG.
FIG. 4 is a diagram showing a search order for arranging a buffer at the coordinate position shown in FIG. 3. FIG. 5 is a flowchart for searching and determining coordinates for arranging a buffer. 1. When the buffer (8-3) shown in FIG. 10 is inserted into the wiring length (l) of the wiring path (7-3) of the circuit shown in FIG.
Is represented by the sum of l1 (8-4) and l-1 (8-5). The delay value tPD after inserting the buffer = (the delay value of the source element itself + the wiring delay value from the output of the source element to the buffer input + the delay value due to the input capacity of the buffer) + (the delay value of the buffer itself + the buffer output It is necessary that the wiring delay value up to the input of the load element + the delay value due to the input capacitance of the load element) satisfies tPD <tPD0 (delay standard). That is, tPD <tPD0 is as shown below. The wiring length (l) from the output end of the source element to the input end of the load element, the wiring length (l1) from the output of the source element to the input of the inserted buffer, the parasitic capacitance per unit wiring length (Co), and the unit wiring length Wiring resistance (R
o), the delay value of the source element itself (tld1), the output resistance of the source element (R1), the output resistance of the buffer (R2), the input capacitance of the buffer (Cin), the input capacitance of the load element (Cld), and the delay of the buffer itself When the value is (tld2), tPD0> tld1 + R1 × (Co × l1 / 2 + Ci
^{n) + Ro × Co × (} l1) 2/2 + tld2 + R2 ×
{Co × (l-11) / 2 + Cld} + Ro × Co ×
Request ^(l-l1) wiring length l1 of limits can be inserted satisfying buffer 2/2. 2. Wiring length l from the output of the source element to insert the buffer
1 from the output of the source element and the wiring length l on the wiring.
The coordinates for inserting a buffer that does not overlap the existing element are searched for within one, and the coordinates for inserting the buffer are calculated to perform the placement and wiring. 3. In the above “2”, as shown in FIG.
5) When the buffer (2-6) overlaps and the buffer cannot be inserted, the coordinates parallel to the wiring from the output of the source element and within the wiring length l1 on the wiring as shown in FIGS. Search for the coordinates at which a buffer that does not overlap with the existing element is inserted, calculate the coordinates at which the buffer is inserted, and place and wire as shown in FIG.

Automatic placement and routing of semiconductor device of this embodiment
The procedure of the method will be described in detail with reference to FIGS.
Also, the procedure of the above “3” is described in more detail in “6” below.
Will be described. Procedure 1 and Procedure 2 are half of the above-described embodiment.
1 and 2 shown in the outline of the procedure of the automatic arrangement and wiring method of the conductor device
And 2 are the same. 3. Corrected netlist (1-8), layout data
(1-3) and block library (1-10)
To calculate various quantities. That is, a distribution that does not meet the delay specification
Wiring from source element output to load element input of wire path
Length (l), from the source element output to the inserted buffer input
Length (l1), load from inserted buffer output
Wiring length (l-11) to element input, per unit wiring length
Parasitic capacitance (Co), wiring resistance per unit wiring length (R
o), the delay value of the source element itself (tld1), the source element
Output resistance (R1), output resistance of buffer (R2),
Buffer input capacitance (Cin), load element input capacitance
(Cld), find the delay value (tld2) of the buffer itself
You. In (1-9), the calculation formula of the delay value is tPD = tld1 + R1 × (Co × l1 / 2 + Cin)
+ Ro × Co × (l1)²/ 2 + tld2 + R2 × ΔC
ox (l-11) / 2 + CldＣｌ + Ro × Co × (l−
l1)²/ 2 is used to calculate tPD. This tPD is the delay standard tP
TPD0> tPD must be satisfied to satisfy D0
No. Therefore, the delay equation is tPD0> tld1 + R1 × (Co × l1 / 2 + Ci
n) + Ro × Co × (11)²/ 2 + tld2 + R2 ×
{Co × (l-11) / 2 + Cld} + Ro × Co ×
(L-11)²/ 2. This equation is transformed to output the buffer
Up to the wiring length l1. That is, l1 <<< − Co × (R1 / 2−R2 / 2−Ro × l) ±
[{Co × (R1 / 2−R2 / 2−Ro × l)}}² -4
× Ro × Co × (tld1 + tld2 + R1 × Cin +
R2 × Cld) + R2 × Co × 1/2 + Ro × Co × 1
²/ 2-tPD0)]^1/2>> / (2 × Ro × Co)
 (However, l1 is in the range of 0 ≦ l1 ≦ l) The obtained l1 is the output from the source element output to be inserted into the buffer.
One is the limit distance on the wiring. On wiring from source element output
Determine the wiring length of l1 as the range in which the buffer is inserted
(1-11). 4. A buffer on the wiring that does not meet the delay specification is inserted.
Within the range calculated in (1-11),
Determines whether it is possible to place the coordinates at
(1-12). Next, the coordinates are given to the buffer.
Then, place and route (1-13). 5. As shown in FIG. 2, the buffer (2-6) is an existing device
(2-5) and the flowchart of FIG.
(FIG. 5 shows details of FIG. 1 (1-14)).
Is shown). Wiring to insert buffer (4-3)
(The smallest unit of element arrangement; hereinafter referred to as 1G)
X-coordinate of orthogonal linear coordinates xy with a certain point on the wiring as the origin
One of the mark and the y-coordinate, in the direction perpendicular to the wiring (4-3)
Set the position (4-5). This + side position (4-5)
At the output terminal side of the source element (4-1).
In the direction of the element (4-2), the buffer is determined by (1-11).
Coordinates where the buffer does not overlap with existing elements up to the insertion range
(13-1) and (13-2). Next
When the buffer overlaps with the existing element and cannot be arranged (13)
-3) is the 1G- side of the opposite side with the wiring (4-3) in between.
Positions (4-6) are likewise duplicated for buffers
Find coordinates that do not match. Next, the buffer is
Find non-overlapping coordinates and give them to buffer
(13-7). 6. In the above "5", the buffer does not overlap with the existing element
If there is no mark, coordinate position from wiring (4-3)
..., etc., and add 1 (13-6). For example, as shown in FIG.
When the coordinate position is
You will be. Flowchart (13-2) to (13-5)
Repeat until The buffer does not overlap the existing element
Search for a marker and give its coordinates to the buffer (13-
7). 7. Place the buffer at the coordinate position (1-13)
You. Then, for example, as shown in FIG.
Is arranged. 8. Buffer insertion for all wiring that does not meet delay specifications
Is completed (1-15), and all are completed.
The procedure from (1-9) is repeated until the operation is completed. 9. Buffers are placed on all wires that do not meet the delay standard
If wiring is completed, the relayout data (1-1
6) is created and combined with the delay library (1-4).
The delay information (1-17) is created. Ultimately Kritika
Whether or not the Lupass timing standard (1-6) is satisfied
(1-18), and a method for automatic placement and routing of semiconductor devices
To end.

According to the method for automatically placing and routing a semiconductor device according to the embodiment of the present invention, wiring that does not satisfy the critical path timing standard (1-6) indicating the maximum delay value, which is the maximum allowable delay value, is used. A modified netlist (1-8) indicating a list into which a buffer is to be inserted, and layout data (1-3) indicating how semiconductor circuit elements are arranged and wired on a circuit. Calculate the delay value of the wiring that does not satisfy the critical path timing standard (1-6) by using the block library (1-10) indicating the circuit block characteristics in the netlist (1-9) The procedure and the wiring length from the output terminal of one semiconductor device indicating the position where the buffer is to be inserted are determined, and the coordinates at which the buffer can be inserted are calculated. It is determined whether or not coordinates can be arranged at a position where the buffer does not overlap with an existing element in the issued buffer insertion range (1-12). If the coordinates can be arranged, the buffer is arranged at the coordinates. (1-13) If it is not possible to arrange coordinates in a position where the buffer does not overlap the existing element, the semiconductor element is placed on the wiring into which the buffer is to be inserted. A third procedure of setting 1G, which is the minimum unit to be arranged, in the vicinity of a wiring existing in the buffer insertion range and searching for a position where a buffer to be inserted in the vicinity of the wiring does not overlap with an existing element ( (13-1) to (13-
6)), place a buffer at that position and wire it, determine whether or not the buffer has been inserted into all the wires that do not meet the delay standard. By repeating the procedure from the first step until the buffer insertion is completed, the position where the buffer is inserted on the wiring that does not satisfy the delay standard is compared with the delay value of the source-side element itself and the delay value due to the wiring load. Thus, the wiring length can be arranged and wired for the wiring length in a range that is large, and the correction that satisfies the delay standard can be performed. In addition, since a correction that satisfies the delay standard can be made with one correction without having to make another IPO correction, a short TAT
Can be realized.

Second Embodiment An automatic placement and routing method for a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG.
8 is a flowchart for automatically inserting a buffer into a wiring that does not satisfy a delay standard according to a second embodiment of the present invention.
FIG. 7 is a diagram showing an order of searching for a place where a buffer can be arranged in the automatic placement and routing method for a semiconductor device according to the second embodiment of the present invention. FIG. 8 is a flowchart showing the buffer arrangement coordinate search / determination in the automatic arrangement and wiring method of the semiconductor device according to the second embodiment of the present invention. First, an outline of a procedure of an automatic placement and routing method for a semiconductor device according to the present embodiment will be described. 1. Based on the netlist (5-1), the placement and routing (5-
2) is performed to create layout data (5-3).
Next, delay information (5-5) is created from the layout data (5-3) and the delay library (5-4). 2. Based on the critical path timing standard (5-6) and the delay information (5-5), a wiring that does not satisfy the delay standard is calculated, and a buffer is inserted into the wiring that does not satisfy the delay standard (5-7). To create a modified netlist (5-8). 3. Block library (5-10) and modified netlist (5-8) indicating circuit block characteristics in the netlist
Based on the data and the layout data (5-3), the source device on the wiring that does not satisfy the delay standard and the delay parameter of the buffer are extracted (5-9), and the buffer insertion range is calculated (5-9).
-11). 4. It is determined whether or not the buffer can be arranged at coordinates that do not overlap with the existing elements on the wiring that does not satisfy the delay standard and in the buffer insertion range (5-12). Next, coordinates that allow the buffer to be arranged without overlapping existing elements are given as arrangement coordinates of the buffer, and arrangement and wiring are performed (5-13). 5. On the other hand, there are other elements, wiring, etc.
If it is not possible to place the buffer so as to overlap with the buffer, a search is made for the coordinates at which the buffer does not overlap the existing element in the buffer insertion range obtained in (5-11) alternately on both sides of the wiring that does not satisfy the delay standard, and the buffer is placed. Given as coordinates (5
-14), and place and route (5-13). 6. After the buffer is completely inserted into all the wirings that do not satisfy the delay standard (5-15), the relayout data (5-16) is created. 7. The re-layout data (5-16) and the delay library (5-4) form the re-delay information (5-17).
And create a critical path timing standard (5-
There is a procedure (5-18) of confirming whether 6) is satisfied.

The procedure for calculating the buffer insertion position in the semiconductor device automatic placement and routing method according to the present embodiment will be described with reference to FIGS. 2, 7 and 8. Steps 1 to 2 are the same as the procedure for calculating the buffer insertion position in the semiconductor device automatic placement and routing method according to the first embodiment of the present invention. In the present embodiment, the third procedure of the first embodiment is changed. 3. In the procedure "2" for calculating the buffer insertion position according to the first embodiment, as shown in FIG.
5) When the buffer (2-6) overlaps and the buffer cannot be inserted, as shown in FIGS. 7 and 8, alternately on both sides of the wiring from the source element output and within the wiring length l1 on the wiring The coordinates at which a buffer that does not overlap with the existing element are inserted are searched for, the coordinates at which the buffer is inserted are calculated, and the wiring is performed.

The procedure of the automatic placement and routing method of the semiconductor device according to the embodiment will be described in detail with reference to FIGS. The procedure of the above "3" will be described in more detail in the following "6". Procedure 1 to procedure 4 are the same as in the first embodiment according to the present invention. 5. The case of overlapping with an existing element will be described with reference to the flowchart of FIG. 8 and FIG. 7 (FIG. 8 shows details of FIG. 6 (5-14)). Wiring to insert buffer (6-
From the output wiring coordinates of the source element in 3), the wiring (6-3) into which the buffer is to be inserted is a position on the 1G load side, and the wiring is 1G (the wiring is the axis and a point on the wiring is the origin. One of the x-coordinates or y-coordinates of the orthogonal linear coordinates xy, a search is made to determine whether or not the buffer overlaps with an existing element at the coordinates on the side perpendicular to the wiring (6-3) + (6-5) (14-
2). If the buffer cannot be overlapped with the existing element (14-3), the wiring (6-3) is inserted, and the opposite side, 1G
The coordinates on the negative side (6-6) where the buffer does not overlap with the existing element are searched (14-4). If the buffer still cannot overlap with the existing element, the buffer overlaps with the existing element on the wiring (6-3) by a further 1 G at the position on the load element side and 1 G + side from the wiring (6-3). It is determined whether the buffer does not overlap the existing element at the coordinates on the opposite side, 1G- side, with the wiring (6-3) interposed. Repeat (14-1) to (14-6) to find the coordinates where the buffer and the existing element do not overlap, and give the coordinates to the buffer up to the range to insert the buffer obtained in (5-11) ( 14-8). 6. If the buffer cannot overlap with the existing element in the above “5”, the coordinates (6) on the 1G + side from the wiring (6-3) are further added.
-9) and the wiring (6-3) are sandwiched, and the coordinates (6-10) on the opposite side are searched for coordinates where the buffer does not overlap the existing element, and the coordinates are given to the buffer (14-).
8). 7. It is determined whether or not the buffer insertion has been completed for all the wirings that do not satisfy the delay standard (5-15), and the procedure from (5-9) is repeated until all the wiring is completed. 8. When the buffers can be arranged and routed on all the wires that do not satisfy the delay standard, re-layout data (5-16) is created, and re-delay information (5-17) is created along with the delay library (5-4). Finally the critical path
It is confirmed whether the timing standard (5-6) is satisfied (5-18), and the automatic placement and routing method of the semiconductor device is completed.

According to the semiconductor device automatic placement and routing method according to the embodiment of the present invention, n (n is a natural number) is set to 1
As a result, a search is made for coordinates at which a buffer can be inserted on the wiring (6-3) within the buffer insertion range, and if there are coordinates at which a buffer can be inserted, this procedure is terminated. Search for wiring that does not meet other delay standards, and if there are no coordinates where a buffer can be inserted, set the search start position at one end within the buffer insertion range and proceed to the next second procedure. Step (14-1), and if there is a coordinate at which a buffer can be inserted, the procedure is terminated to search for a wiring that does not satisfy another delay standard, and a buffer can be inserted. If there is no coordinate, a second procedure for searching for a coordinate at which a buffer can be inserted at a position (6-5) away from the wiring by + nG (one direction away from the wiring is a plus (+) direction) ( 14-2), If there is a coordinate at which a buffer can be inserted, this procedure is terminated and another wiring that does not satisfy the delay standard is searched (14-3), and there is no coordinate at which a buffer can be inserted. -NG from wiring
Separated position (6-6) (the other direction away from the wiring, ie, the direction opposite to the + direction is the minus (-) direction)
In (3), a third procedure (14-4) for searching for coordinates at which a buffer can be inserted, and if there is a coordinate at which a buffer can be inserted, this procedure is terminated and another delay standard is set. A search is made for a wire that does not satisfy the condition (14-5). If there is no coordinate at which a buffer can be inserted in the searched area, the wire is moved by 1 G parallel to the wire within the buffer insertion range and the second hand is moved. Returning to the order (14-6), if moving by 1 G in parallel with the wiring deviates from the buffer insertion range, the fourth procedure proceeds to the next fifth procedure ((14-6).
5), (14-6)) and a fifth procedure (14-7) in which n is set to n + 1, a search start position is set at one end in the buffer insertion range, and the procedure returns to the second procedure.
For all areas within the buffer insertion range, it is possible to search all over the coordinates of positions that do not overlap with existing elements, and by arranging and wiring buffers, it is possible to correct delay specifications it can. In addition, IP
Since a correction that satisfies the delay standard can be performed by one correction without performing the O correction, a short TAT can be realized.

[0036]

As described above, in the automatic placement and routing method of the semiconductor device according to the present invention, it becomes possible to search all the areas within the buffer insertion range for coordinates of positions that do not overlap existing elements. By arranging and wiring the buffer, it is possible to make a correction satisfying the delay standard. In addition, since a correction that satisfies the delay standard can be performed with one correction without performing the IPO correction again, a short TAT can be realized.

[Brief description of the drawings]

FIG. 1 is a flowchart of an automatic placement and routing method for a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a state in which a buffer is arranged in a specified range and overlaps an existing element in the automatic placement and routing method for a semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a state in which a place where a buffer can be arranged near a specified range is searched and arranged in the automatic placement and routing method for a semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a diagram illustrating an order of searching for a place where a buffer can be arranged in the automatic placement and routing method for a semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a flowchart showing a buffer arrangement coordinate search / determination in the semiconductor device automatic arrangement and wiring method according to the first embodiment of the present invention;

FIG. 6 is a flowchart of an automatic placement and routing method for a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an order of searching for a place where a buffer can be arranged in the automatic placement and routing method for a semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a flowchart showing a buffer arrangement coordinate search / determination in the semiconductor device automatic arrangement and wiring method according to the second embodiment of the present invention.

FIG. 9 shows a circuit diagram in a case where there is a wiring that does not satisfy a delay standard in a conventional method of automatically placing and routing a semiconductor device.

FIG. 10 is a circuit diagram in which a buffer is inserted at a position A in the conventional method of automatically placing and routing a semiconductor device.

FIG. 11 is a circuit diagram in which a buffer is inserted at a position B in the conventional method of automatically placing and routing a semiconductor device.

FIG. 12 is a diagram showing a delay difference due to a difference in a buffer insertion position in a conventional automatic placement and routing method for a semiconductor device.

FIG. 13 is a diagram showing drive characteristics of a source element and a buffer in a conventional automatic placement and routing method for a semiconductor device.

FIG. 14 is a flowchart of a conventional automatic placement and routing method for a semiconductor device.

[Explanation of symbols]

(2-1) (3-1) (4-1) (6-1) ... source element (2-2) (3-2) (4-2) (6-2) ... load element (2-3) (3-3) (4-3) (6-3) ... wiring route that does not satisfy the delay standard (2-4) (3-4) (4-4) (6-4) ... Calculated buffer insertion range (2-5) (3-5)... Arranged existing element (2-6)... Buffer to be inserted (position overlapping other existing elements) ( 3-6)... Buffers arranged according to the present invention (4-5) to (4-10)... Order in which to search for a buffer insertion position according to the embodiment of the present invention (6-5) to (6) −10) Order of searching for a buffer insertion position according to the second embodiment of the present invention (7-1) (8-1) (9-1) ... source element F /
F-1 (7-2) (8-2) (9-2) ... load element F /
F-2 (7-3): wiring route that does not satisfy the delay standard (8-3) (9-3) ... buffer (8-4) (9-4) ... from the source element to the buffer (8-5) (9-5) ... wiring path from buffer to load element (10-1) ... delay characteristic before inserting buffer shown in Fig. 9 (10-2) ..Delay characteristics when buffer shown in FIG. 10 is inserted at position A (10-3) ... Delay characteristics when buffer shown in FIG. 11 is inserted at position B (11-1) ... Source element (11-2) ・ ・ ・ Drive characteristics of buffer

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akitoshi Kato 1-403, Kosugicho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 F-term (reference) in NEC Ic Microcomputer System Co., Ltd. 5B046 AA08 BA04 JA01 KA06 5F064 BB26 DD02 DD03 DD14 DD25 EE02 EE03 EE08 EE43 EE47 EE54 HH06 HH12

Claims (8)

[Claims] 1. A modified netlist showing a list in which a buffer is inserted into a wiring that does not satisfy a critical path timing standard indicating a maximum delay value that is an allowable maximum delay value, Calculating a delay value in the wiring that does not satisfy the critical path timing standard by using layout data that is data indicating whether circuit elements are arranged and wired, and a block library that indicates circuit block characteristics in a netlist. In the first procedure, a wiring length from an output end of one semiconductor element indicating a position where a buffer is to be inserted is obtained, coordinates at which a buffer can be inserted are calculated, and a range in which the coordinates are calculated ( It is determined whether or not it is possible to place the coordinates in a position where the buffer does not overlap with the existing elements in the buffer insertion range. The second procedure is to place and route a buffer at that coordinate if it is possible to place it, and if it is not possible to place the coordinate at a position where the buffer does not overlap the existing element One grid (hereinafter referred to as 1G), which is the minimum unit for arranging a semiconductor element on a wiring into which a buffer is to be inserted, is set near a wiring existing in the buffer insertion range, and is set in the vicinity of the wiring. The third step of searching for a position where the buffer to be inserted does not overlap with the existing device, placing the buffer at that position, wiring it, and inserting the buffer into all the wiring that does not meet the delay standard are completed Determining whether or not to insert buffers into all the wirings that do not satisfy the delay standard, and repeating the procedure from the first step until the wiring is completed. . 2. The third step of searching for a position where a buffer in the vicinity of a wiring does not overlap with an existing element is performed in a position in one direction from the wiring (hereinafter, referred to as a + position) and at a right angle to the wiring. 1G, which is the minimum unit for arranging a semiconductor element on a wiring into which a buffer is to be inserted, is set at a position separated from the wiring by a predetermined length, and the buffer does not overlap with an existing element within the buffer insertion range. A first procedure for searching for the coordinates of the position in parallel with the wiring at the predetermined position, and if there is a coordinate at which a buffer can be inserted, the procedure is terminated and wiring that does not satisfy the other delay standards is completed. If it is impossible to place the buffer so that it overlaps with the existing element, the position on the + side with respect to the wiring is a position in a symmetrical region (hereinafter referred to as the-side position) and From a specified length A second procedure of setting 1G to the position to be inserted, and searching for the coordinates of the position where the buffer does not overlap the existing element in the buffer insertion range in parallel with the wiring at the predetermined position, and the coordinates at which the buffer can be inserted If there is a buffer, terminate this procedure and search for wiring that does not meet other delay standards. If the above procedure does not make it possible to place the buffer so that it overlaps the existing elements,
In the first and second procedures, the length at which 1 G is separated from the wiring is increased, and the coordinates of the position where the buffer does not overlap the existing element within the buffer insertion range are searched in parallel with the wiring at the predetermined position. 2. The method according to claim 1, wherein the steps (a) and (b) are set. 3. The third step of searching for a position where a buffer in the vicinity of a wiring does not overlap with an existing element is performed at a position perpendicular to the wiring and on the + side and separated from the wiring by a predetermined length. A first procedure of setting 1G, which is the minimum unit for arranging a semiconductor element on a wiring into which a buffer is to be inserted, and searching for coordinates of a position where the buffer does not overlap an existing element within the buffer insertion range; If there is a coordinate at which a buffer can be inserted, terminate this procedure and search for wiring that does not meet other delay standards. 1G is set at a position symmetrical with respect to the wiring with respect to the position checked in the first procedure (a position in the position area on the negative side), and a position where the buffer does not overlap with an existing element within the buffer insertion range. Seat The second step of searching for a mark, and if there is a coordinate at which a buffer can be inserted, terminate this step and search for wiring that does not meet other delay standards.
If it is not possible to arrange the buffer so as to overlap with the existing element by the above procedure, the coordinates of the position where the buffer does not overlap with the existing element in the first and second procedures are set as wiring and within the buffer insertion range. If there is a third step to search in parallel, and if there is a coordinate at which a buffer can be inserted, terminate this step and search for wiring that does not meet other delay standards. In the case where it is impossible to overlap with the existing element, it is necessary to extend the length of 1 G away from the wiring in the first and second procedures and to perform the first, second and third procedures. ,
2. The automatic placement and routing method for a semiconductor device according to claim 1, wherein 4. The third procedure for searching for a position where a buffer in the vicinity of a wiring does not overlap an existing element is performed by setting n (n is a natural number) to 1 on a wiring within the buffer insertion range. Search for coordinates where a buffer can be inserted, and if there are coordinates where a buffer can be inserted, terminate this procedure and search for wiring that does not meet other delay standards, and insert a buffer If there are no coordinates that can be performed, a search start position is set at one end in the buffer insertion range, and the first procedure proceeds to the next second procedure, and a position away from the wiring by + nG (one direction away from the wiring is In the plus (+) direction), the second procedure of moving in the buffer insertion range by 1 G in parallel with the wiring and searching for the coordinates where the buffer can be inserted, and the coordinates where the buffer can be inserted are as follows. If there is, terminate this procedure and search for a wire that does not satisfy another delay standard. If there is no coordinate at which a buffer can be inserted, -n
G away position (the other direction away from wiring, ie +
The direction opposite to the direction is referred to as a minus (-) direction). The third procedure of searching the coordinates where the buffer can be inserted by moving in the buffer insertion range by 1 G in parallel with the wiring, and inserting the buffer. If there is a coordinate that can be inserted, the procedure is terminated and a wiring that does not satisfy another delay standard is searched. If there is no coordinate that can insert a buffer, n is set to n + 1 and the second 2. The method according to claim 1, further comprising: setting a fourth step of returning to the procedure. 5. The third step of searching for a position where a buffer in the vicinity of a wiring does not overlap with an existing element is performed by setting n (n is a natural number) to 1 on a wiring within the buffer insertion range. Search for coordinates where a buffer can be inserted, and if there are coordinates where a buffer can be inserted, terminate this procedure and search for wiring that does not meet other delay standards, and insert a buffer If there are no coordinates that can be used, there is a first procedure where the search start position is set at one end in the buffer insertion range and the procedure proceeds to the next second procedure, and there are coordinates where a buffer can be inserted. In this case, the procedure is terminated to search for a wire that does not satisfy another delay standard. If there is no coordinate at which a buffer can be inserted, the position away from the wire by + nG (one direction away from the wire is added. (+) Person The second procedure for searching for coordinates where a buffer can be inserted, and if there is a coordinate where a buffer can be inserted, this procedure is terminated and another delay standard is satisfied. If there are no wires that can be inserted into the buffer and there are no coordinates at which a buffer can be inserted, the position away from the wires by -nG (the other direction away from the wires, that is, the direction opposite to the + direction is the minus (-) direction. In step 3), search for coordinates at which a buffer can be inserted, and if there are coordinates at which a buffer can be inserted, terminate this procedure and replace wiring that does not meet other delay standards. If there is no coordinate at which the buffer can be inserted in the searched area, move by 1 G parallel to the wiring within the buffer insertion range, return to the second procedure, and move 1 G parallel to the wiring. A fourth procedure to proceed to the next fifth procedure when the movement deviates from the buffer insertion range, a fifth procedure to set a search start position at one end within the buffer insertion range and set n to n + 1, and return to the second procedure; 2. The automatic placement and routing method for a semiconductor device according to claim 1, wherein 6. The order of searching for a position where a buffer in the vicinity of a wiring does not overlap an existing element is to search for coordinates at which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range. In the first step, in one of the areas divided into two by the wiring, coordinates at which a buffer can be inserted from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the wiring are determined. It is possible to insert a buffer from one end to the other end within the buffer insertion range at a position separated by a predetermined fixed distance from the wiring in the second step of searching and in the other area of the area divided into two by the wiring And a third step of searching for coordinates, and gradually increasing a predetermined distance from the wiring in the second and third steps until coordinates capable of inserting a buffer are found. 2. The method according to claim 1, wherein the process is lengthened and the process proceeds to the second and third steps again. 7. The order of searching for a position where a buffer in the vicinity of a wiring does not overlap an existing element is to search for coordinates at which a buffer can be inserted from one end to the other end of the wiring within the buffer insertion range. A first step of searching for a coordinate at which a buffer can be inserted in a buffer insertion range at a position separated by a predetermined fixed distance from the wiring at one end of one of the areas divided into two by the wiring; The second step is to search for a coordinate at which a buffer can be inserted in a buffer insertion range at a position separated by a predetermined distance from the wiring at one end of the other area of the area divided into two by the wiring. In the second step and the third step, the second step and the third step are performed again at a position moved from the one end to the other end by a predetermined distance within the buffer insertion range. In the fourth process, a predetermined constant distance from the wiring is gradually increased until coordinates that can insert a buffer within the buffer insertion range are set, and the second process and the third process are performed again. 2. The method according to claim 1, further comprising the steps of: 8. A wiring length (l) from an output terminal of one semiconductor device to an input terminal of another semiconductor device, a wiring length (11) from an output terminal of one semiconductor device to an inserted buffer input,
Parasitic capacitance per unit wiring length (Co), wiring resistance per unit wiring length (Ro), delay value of one semiconductor element itself (tld1), output resistance of one semiconductor element (R1), output resistance of buffer ( R2) Input capacity of buffer (Ci
n), the input capacitance (Cld) of another semiconductor element, and the delay value (tld2) of the buffer itself, a condition that the delay value tPD after inserting the buffer is smaller than the delay standard tPD0. tPD0> tPD = tld1 + R1 × (Co × l1 / 2
+ Cin) + Ro × Co × (l1) 2/2 + tld2 +
R2 × {Co × (l-11) / 2 + Cld} + Ro × C
claim by o × (l-l1) 2 /2 conditions, and obtains the wiring length l1 is a length limit that can be inserted buffer 1
8. The automatic placement and routing method for a semiconductor device according to claim 1.