TWI244583B - Optimization method of clock network capacitance on an integrated circuit - Google Patents

Abstract

A method of optimizing clock network capacitance of an integrated circuit (IC) including identifying any crossover points between clock traces and signal traces and reducing clock trace to reference trace capacitance at identified crossover points. Each clock trace is shielded by ground traces routed on either side of the clock traces. The reducing of clock trace to reference trace capacitance may include narrowing the reference traces at identified crossover points. Narrowing of the reference traces at a crossover point reduces capacitance to compensate for additional capacitance between the clock trace and the signal trace. Narrowing may be performed by trimming or notching at the crossover points. Such capacitive compensation provides clock traces of the clock network with substantially uniform capacitance per unit length.

Description

1244583 _Case No. 92127914_year month__ V. Description of the invention (1) This patent application claims the priority of the United States. Its application number is 10/464782, and the application date is May 21, 2003. All contents and purposes of the patent application are incorporated in the present invention. [Technical Field to which the Invention belongs] The present invention relates to an integrated circuit (IC) layout (wiring) and design, and more specifically, to optimization of an integrated circuit clock network capacitance. [Previous Technology] Today's digital integrated circuits can incorporate millions of transistor components in a small area. These components implement switch control and perform their functions based on the boundary information of the core clock signal. The core clock signal frequency has recently exceeded a gigahertz (G Η z) threshold. The higher the clock frequency, the more difficult it is to control the core clock signal capacitance. At that time, the capacitive coupling of the signal traces that are inevitably routed to the upper and lower signal traces of the layer where the clock traces are located becomes more sensitive. The traditional technique of controlling capacitance is to shield two ground traces on the same layer. Clock routing between. Figure 1 is a partial top view of the integrated circuit (1C) 100, which shows the traditional method of clock trace capacitance control. As can be seen in the figure, the clock traces 1 0 1 are routed on layer 1 0, and the ground traces 1 0 3, 1 0 5 are routed at equal distances to the clock traces 1 0 1 and grounded through two equal widths of the shield. A clock trace 1 0 1 between traces 10 3 and 105 can make the clock trace isolated from other signals π on the same layer 10 7. For example: the width of each ground trace 1 0 3, 1 0 5 is "W π", and the distance between the signal trace 1 0 1 and each ground trace is n D π. The capacitance of the ground terminal of the line is the ground trace 1 0 3, 1 0 5

1244583

_ Case No. 92127914_ year month grid | T V. Description of the invention (2) The width W and the function of the distance between each ground trace 1 0 3, 1 05 and the clock trace 1. By using equal width ground traces 1 0 3, 1 〇5, and placing ground traces 1 0 3, 1 〇5 equidistantly on both sides of clock trace 1 〇1, for the lower clock In terms of frequency, a relatively uniform unit length capacitance of the clock trace can be obtained, that is: C 1 = C2 = C3 = C4. 2. At lower clock frequencies, such as below 1 G Η z, traditional techniques are sufficient to control the clock signal capacitance. However, with the development of sca 丨 ng technology, when the device is allowed to run at higher frequencies, the content of the clock trace 丨 〇1 will inevitably be routed at this clock trace丨 The influence of signal routing on the upper and lower layers is more. This effect is caused by the clock traces 丨 〇1 and ^ lines on the other layer 1 1 1 and at the crossover point 丨 3 from the clock trace 丨 across the signal traces passing under 〇 09 The capacitances c 5 and C 6 are represented. At the crossover point 1 1 3 clock traces 丨 0 1 The capacitance to ground is greater than the capacitance at other points along the clock traces 丨 〇ι. In particular, at crossover points 丨 丨 3:

Cj + C 5 / C 1 'and c 4 + C 6 > C 3. At higher clock frequencies, an additional valley problem will occur. The reason is that at this time, the resistance-capacitance (Rc) network characteristics of the clock trace 1 0 1 at a cross-connect point such as the cross-connect point 丨 3 Significant changes can result in increased rise times, delays, and relatively skewed internal clock signals as will be discussed here. _ h Please refer to FIG. 2. The block diagram 2 0 indicates non-uniform wiring, and the voltage V causes timing problems related to the internal clock skew (c 1 0 c k s k e w). The block jf in FIG. 2 includes two consecutive logic blocks, that is, a logic block 1 2 0 and a logic block 2 2 02, both of which are part of a pipeline data circuit. In this type of circuit, the data is accompanied by an internal clock signal that assumes synchronous operation

1244583 Case No. 92127914 Λ_3 Name Amendment V. Description of the Invention (3) LCLK1 204 and LCLK2 205 are synchronized from one logic block 201 to the next logic block 202. With the help of data bus 2 0 3, data is provided from logical block 1 2 0 1 to logical block 2 2 0 2. It is assumed here that the data bus 2 0 3 is valid and should be latched into the logic block 2 2 0 2 at point A. At point B, the data is no longer valid on the data bus 203. For ease of description, the signal L C L K 2 2 0 5 is described as delayed, so it is not kept relatively synchronized with the operation of the signal L C L K 1 2 0 4. The cause of the skew of LCLK2 205 is the non-uniformity of capacitance caused by the crossover of the traces near the buffer logic (not shown) of LCLK2 204. In this way, the rise and fall time of the main clock distribution signal (not shown in the figure) will increase, so that the buffer logic will generate an internal clock signal LCLK 2 2 0 5 as a delay type . The signal LCLK2 205 at point C has a latching edge, which can latch on invalid data from the bus 203. The situation shown in Fig. 2 is only a typical example of the different timing problems caused by clock skew caused by the non-uniformity of the distributed signal capacitance. Therefore, what is currently needed is a method and a device whose purpose is to provide a clock trace uniform unit length capacitor for wiring circuits and integrated circuits (ICs) including circuits operating at higher clock frequencies. [Summary] According to an embodiment of the present invention, an integrated circuit (IC) clock network capacitance optimization method includes identifying a jumper between a clock trace and a signal trace, and identifying the jumper on the identified jumper. The clock trace capacitance is reduced to the reference trace capacitance. Each clock trace is masked by reference traces distributed on both sides of the clock trace. Reducing the clock trace capacitance to the reference trace capacitance operation can include

1244583 Case No. 92127914 Amendment V. Description of the invention (4) Reduce the reference trace width at the identified crossover points. The method may further include finding the capacitance of the unit length of the clock trace, finding the additional capacitance between the clock trace and the signal trace at the identified crossover point, and finding the required capacitance to offset the additional capacitance. The reference trace width reduction that should be used at the jumper. Clock circuit optimizer control files or applications can be used in the integrated circuit layout and design process.

A method for adding a circuit to an integrated circuit according to an embodiment of the present invention includes wiring (winding) first and second ground traces on both sides of a clock trace on a first layer, and determining that the clock trace and wiring The crossover points between signal traces on the second layer reduce the width of the first and second ground traces at the crossover points, respectively. The two ground traces are approximately the same width when routed, and the distances from the clock traces are also approximately equal. According to an implementation form of the present invention, the integrated circuit includes a clock trace on a first layer located between the first and second reference traces and a distance approximately equal to the two traces, and a second trace across the clock trace. Signal routing on layers. Each reference trace has approximately the same width except that the signal traces and their junctions become narrower.

According to the implementation form of the present invention, the media-incorporated program code running in the circuit wiring database includes a first program code used to identify a crossover point between a signal trace and a clock trace, and is used to calculate a circuit having at least one crossover point. The second program code of the unit length capacitance between the clock trace and the corresponding wiring between the first and second reference traces on both sides of the clock trace is used to calculate the corresponding signal at each crossover point. The third program code of the additional capacitance caused by the trace is used to calculate the corresponding reference trace required to offset the additional capacitance at each crossover point

Page 10 1244583 _Case No. 92127914_year month_iMz_ V. Description of the invention (5) The fourth program code of the line width reduction amount. The media can further include a fifth program code to modify the circuit routing database to reduce the reference trace width based on the calculated width reduction. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Embodiment] The purpose of the following description is to Those skilled in the art can smoothly use the present invention according to specific application fields and requirements. However, it is obvious to those skilled in the art that several preferred implementation forms provided can be modified, and the general principles defined herein are also applicable to other implementation forms. Therefore, the present invention is not limited to the specific embodiments described herein, but is applicable to a wide field related to the principles and novel features of the present invention. The inventors have recognized the quest to maintain the uniformity of the capacitance per unit length of the clock signal traces, especially for integrated circuits running at higher frequencies. Therefore, a method for compensating for fluctuations in the capacitance of clock signal traces has been invented. This method will be described below with reference to FIGS. 3 to 6. Fig. 3 shows a partial top view of an integrated circuit (1C) 300. The integrated circuit is made according to the method of the embodiment of the present invention to provide a uniform capacitance on the core clock signal per unit length. Clock traces 1 0 1 are routed on layer 10 7 and signal traces 10 9 are routed on layer 1 1 1. Similar to the way shown in Figure 1, a jumper 1 1 3 is formed. Compared with the integrated circuit 100, the capacitors C1, C3, C5, and C6 remain substantially unchanged. It ’s worth noting that the term ‘’

Page 11 1244583 Case No. 92127914 Λ_η Revision V. Description of Invention (6) (crossover point) "usually refers to a position where the signal trace is perpendicular to the integrated circuit layer and is in line with the clock trace The theoretical plane crosses or intersects, regardless of the specific reference plane or direction (such as: top, bottom, left, right, etc.). The same signal trace can intersect with a clock trace cross at multiple crossover points, multiple Different signal traces can also cross a given signal trace cross at multiple crossover points. As shown in the figure, the integrated circuit 300 incorporates many transistor components in a relatively small area. The pulse trace 1 0 1 carries the core clock signal with a typical clock frequency (for example: 1 G Η z or higher). However, the circuit according to the present invention includes a printed circuit board (PCB s) or uses a certain operating frequency. The similar operating circuit here refers to the operating frequency at which the crossover point can cause additional capacitance along the length of one or more clock signal traces. Layers / 1 0 7 and 1 1 1 are usually parallel to each other and may Adjacent The present invention considers that there are some intermediate layers (one or more layers) between them, and in these intermediate layers, the memory has additional capacitance, which changes the unit length capacitance along a given pulse line. Reference trace 3 0 3 and 3 0 5 are routed on both sides of the signal trace 1 0 1, and the wiring is similar to that of the ground traces 10 3 and 105. The π reference trace can carry any appropriate reference potential and includes ground The traces in the figure. The reference traces 3 0 3 and 3 0 5 have the same width W and are kept at approximately the same distance D from the signal trace 1 0 1 as shown in Figure 1. Ground traces 1 3 and 1 In the case of 0 5, this usually results in equal uniform unit length capacitors C 1 and C 3, where C 1 = C 3. Jumper 1 1 3 usually results in two additional jumpers 3 0 7 a and 3 0 7 b crossover position at which signal traces 1 0 9 crossover respectively

Page 12 1244583 _ Case No. 92127914 V. Description of the invention (7) Refer to traces 303 and 305. The reference traces 303 and 3Q5 become narrower at their respective junctions 3007a and 3 07b, and their width values become the new values "W2". In the configuration shown in the figure, the reference traces are engraved with arcuate or arc-shaped grooves 3 009 a and 3 009 b. These two pairs of grooves are called two sides of the reference traces 3 〇 03 and 305 To obtain a new width value μ at the junctions 307a and 307b. Notch grooves (η 〇tch) 3 0 9 a and 3 0 9 b are used to reduce the width of the reference traces 3 0 3 and 3 0 5 ', respectively. Therefore, the crossover points 3 0 7a and 3 0 7b Electricity 2 and C4 are reduced to C7 and C8, respectively. In particular, the reduced capacitance C7 is used to offset the additional capacitance C 5 ′ in order to maintain the capacitance value per unit length as c 1, that is, C 7 + C 5 = C 1. In a similar manner, the reduced capacitance c 8 is used to offset the additional capacitance C 6, and the purpose is to ensure that the capacitance value per unit length is c 3, that is, C 8 + C 6 = C 3. In short, at the jumper points 307a and 3 07b related to the jumper point 丨 13, the isolated reference traces 3 〇3 and 305 are notched to reduce the clock-reference trace capacitance. (Eg: C2 to C7, C4 to C8) in order to compensate the clock-adjacent signal trace capacitance (such as C 5 and c 6), the purpose is to make the clock at the jumper 1 1 3 The line 1 0 1 capacitance is substantially equal to the desired uniform unit length capacitance of the clock network. Symmetrically placed and symmetrically shaped arc-shaped grooves provide a simple and easy-to-implement solution for reducing the width of conductive traces for capacitance compensation. However, several deviations should be considered. While maintaining electrical and mechanical uniformity, it is allowed to trim the traces (t r m m i n g) into any shape or form sufficient to meet the required capacitance reduction requirements. Squares can be used at this time, but excessively sharp angles can cause some undesirable results. The curved notches have no sharp corners. At this point ^ change the corners and sides of the square notch to a circle. Consider opening on the side of the conductive trace

Page 13 1244583 Case No. 92127914_Year Month Day_Revision V. Description of the Invention (8) A single groove is used to achieve the required reduction in the width of the trace. It is also possible to use a smaller size for the grooves. In order to reduce the required width, the size of a single arc groove on one side needs to be longer than the desired groove size. To reduce the arc length, a smaller arc radius can be used, but this result may cause the edge of the trace to be sharpened. . Fig. 4 shows a flowchart of an integrated circuit design program 400 for implementing a clock network 'capacitor optimization according to the present invention. As described in the first block 401, e also calculates the circuit description of engineers and students to form an integrated circuit. This circuit description can be provided in any one of many formats known to those skilled in the art, such as any appropriate hardware description language (HDL). Examples of hardware description language (HDL) include register transfer level (RTL), Veri 1 og hardware description language, etc. As shown in the following box 4 0 3, the register transfer level or hardware description language encoding audit Processing with the aid of a suitable circuit diagram input and network list (η et 1 is t) program can be provided, for example, using software such as a master graphics software (Ment 〇r Graph i CS)! Electricity: Diagram ”Rotation and network list tool. Circuit diagram input and network list program generates a database and a network list. The database describes the components of the circuit. The network list describes the internal links of the components (inter C 0 η η ecti on) 〇 Electrical, road map input and network list database can be in any suitable format such as ASCII (American Standard Code for Information Interchange) or a similar format ο circuit diagram 4 input and network as described in box 4 0 5 below 0J table library is used as a drawing and routing tool to route the wafer. 0 An example of drawing and routing tools is the Virtu osoR series of tools provided by Cadence Design Systems. The drawing tools are effective because they contain all design projects.

Page 14 1244583 Case No. 92127914 A_a. Revision V. Various polygons required for the description of the invention (9) These design projects include stacked photomask layers, electrical crystals, interlayer conductive interconnects or vias (v i a s). Auto-routing tools or other similar tools can be used to design 'inner wires' such as Cadence Custom Chip Assembly Router. As shown in box 407, the drawing and routing tool provides a wiring database output file, also called '' tape output (t ape o u t) π. The wiring library archive may follow an industry standard format such as G DS I or similar. The G D S I I file format is also referred to as the '' Ka code stream (C a 1 m a s t r e a m) π format, which was first developed by the Ka code branch of General Electric Company. Ownership of the format now belongs to Cadenee Design Systems. Additional processing steps, such as design rule verification procedures, can also be used to determine if the wiring database file is consistent with the design product provided by the chip manufacturer. The wiring library file can be changed π ”or can be modified to ensure that the design rules used are met. At the next box 409, the final wiring library file is sent to the factory to generate a confirmation mask, and the final wiring database file finally generates the wafer. During the design of the integrated circuit, a clock network optimizer function corresponding to the implementation form of the present invention is used. As an embodiment, the clock network optimizer function is used as the control file 4 1 1, Used by design and routing tools to explain the selected shape or all shapes. The control file 4 1 1 incorporates a programming code that informs the design and routing tool how to perform a particular function, such as: in the case of the present invention, it appears as How to reduce the width of the reference traces at the identified crossover points, trim the reference traces, or make grooves in the reference traces. The control file 4 1 1 includes: the program code for identifying the clockwise crossover junctions and the maintenance Clock trace capacitance uniformity to find appropriate parameters to

Page 15 1244583 _Case No. 92127914_ Year Month Day__ V. Description of the invention (10) Program code for reducing the reference trace width associated with each crossover point. As another example, the clock network optimizer function can be implemented as an application 4 1 3 or similar program, which modifies the entire wiring database file in order to identify the crossover points and reduce the corresponding reference traces Width so as to maintain the uniform capacitance of each clock trace from virtually. The wiring library file is modified accordingly before it is sent to the factory. Figure 5 shows the clock network optimizer control file 4 1 1 or the clock network optimizer application 4 1 3 program coding general function flow chart 5 0 0. The program code can be used for any appropriate media, such as: magnetic media (tape, disk drive, floppy disk, etc.), optical media (CD-ROM, CD-ROM drive, etc.), electronic media (random memory, read-only memory Media, etc.), etc., other media now known or later invented. At the first block 5 0 1, one or more crossover points can be identified or identified. On the next block 5 0 3, calculate the unit length capacitance (for example: C 1 and C 3) with at least one jumper clock trace. At the next block 5 0 5, calculate the additional capacitance at the crossover point (for example: C5 and C6). In the next block 507, determine the parameters required to reduce the reference trace width associated with the jumper for capacitance compensation purposes. For example, the parameters can include reference trace identification, crossover points along the reference trace, implementation of trace width reduction, trace trimming, and parameters required for grooving. In the last block 509, the trace width reduction parameter is used for the wiring library to achieve the purpose of capacitance compensation. Box 5 (H-5 0 9 can be operated one jump point at a time, or one jump point identified in the wiring library can be operated each time. Now refer to Figure 6, the block icon 6 0 0 indicates that How to use the reference signal trace slotting method to eliminate the internal clock at the crossover point according to the present invention

Page 16 1244583 _____ Case No. 92127914_ Year _ Month Day _ Amendment __ V. Description of Invention (11) Timing related to skew. The block diagram 60 shows two consecutive logic blocks, logic block 16001 and logic block 2602, both of which are part of the pipeline data circuit. As in the embodiment described in connection with FIG. 2, the data is transferred from logic block 6 0 1 to the next logic block 6 0 2 in synchronization with the internal clock signals LCLK 1 6 0 4 and LCLK 2 6 0 5 which are supposed to be synchronized. . Data is transferred from logic block 16 0 1 to logic block 2 6 0 2 through the data bus 6 0 3. At this time, it is assumed that the data bus 60 3 is valid and that the bus should be latched into the logic block 2 6 0 2 at the point A. At point B, the data is no longer valid on the data bus 6 0 3. For ease of description, the signal LCLK 2 6 0 5 is described as accelerated because the grooves are notched at the crossover points according to the present invention. In this way, there is a rising boundary of the latch data at point A, which is opposite to the case of point C. The situation of point C is shown by the dashed line in the figure. Here, the non-compensated internal clock routing has a rising boundary. As a result of applying the present invention to a clock distribution signal (not shown) near a buffer circuit (not shown) of the signal LCLK2 605, its operation is synchronized with the signal LCLK1 604. Therefore LCLK2 605 at point B can latch the valid data before bus # 6 0 3 clears the valid data. Figure 6 shows only one embodiment of the present invention in a number of different implementations, and is used to detect and correct timing problems of integrated circuit caused by non-uniform clock capacitance. When the clock network capacitor is optimized according to the embodiment of the present invention, other benefits and advantages of the present invention can be obtained. At this time, the situation between the clock trace and the reference trace at the crossover point can be corrected to cancel the additional capacitance of the signal trace, so as to obtain the uniform unit length capacitance of the clock signal trace. At higher core clock frequencies, the characteristics of the clock trace RC network will not change significantly at the modified crossover points, and the rise time and delay time will not increase significantly. such,

Page 17 1244583 Case No. 92127914_year month day_revision V. Description of the invention (12) At the same clock frequency, the core clock signal shows a more uniform capacitance characteristic per unit length while the clock speed increases. Eliminated or controlled the negative capacitance effect ^ rL, and the personnel can make the wiring work more easily by implementing signal traces and crossover the clock traces. Although the specific preferred implementation form J is used when the present invention is described in detail, other forms or changes are also possible. May be implemented and should be included in the scope of the present invention. For example, in addition to white-motion changes or computer software changes including control software applications, the present invention is also suitable for circuit designers to manually modify the way. In addition, the present invention also considers Many parameters such as groove type and rule Simple trimming of inch or conductive traces 0 Although the present invention illustrates clock trace capacitance compensation, the present invention is also applicable to any reference traces (not clock traces) for high-frequency signal It is expected to maintain a uniform capacitance along the signal traces in the traces. Finally, those familiar with the art should agree that they can use the concepts described herein and several specific embodiments as a basis for using within the spirit and scope of the present invention. The other structures that accomplish the same purpose as the present invention are calculated and changed. Therefore, the scope of protection of the present invention is subject to the scope of the patent application. Although the present invention has been disclosed in the preferred embodiment, it is not useful. In order to limit any person skilled in the art of this invention, they can make some changes without departing from the spirit of the present invention and ΑτλΓ. Thus the retouch protection of the present invention when the visual range of the appended patent requested range bounded by predetermined whichever is square

Page 18 1244583 _Case No. 92127914_Year Month Day _IfJE._ Brief Description of Drawings Figure 1 shows a top view of a partial area of an integrated circuit (IC) used to describe the traditional method of controlling the capacitance of a clock trace. Figure 2 illustrates how non-uniform clock capacitance can cause timing problems in pipelined systems. Fig. 3 shows a partial top view of an integrated circuit (1C), which is made according to the method of the embodiment of the present invention and provides uniform capacitance on the core clock per unit length. Figure 4 shows a flowchart for integrated circuit design according to an embodiment of the present invention, which is integrated with the optimization of the clock network capacitance. Figure 5 shows the general functional flow chart of the clock network optimizer program code in the control file or Figure 4 application. And FIG. 6 shows an appropriate timing chart of the pipeline system according to the present invention. [Illustration of diagrams] 100, 300: integrated circuit, 101: clock trace layer, 1 0 3, 1 0 5: ground trace, 1 0 7, 1 1 1 ·· ground trace, 1 0 9 : Signal routing, 1 1 3, 3 0 7 a, 3 0 7 b: jumper, 2 0 0,: block diagram, 2 0 1, 2 0 2. · Compilation block 1, compilation block 2 2 0 3: data bus' 2 0 4, 2 0 5: internal clock signal LCLK 1, LCLK 2, 3 0 3, 3 0 5 ·. Reference trace, 3 0 9 a, 3 0 9 b: groove, 4 0 0: integrated circuit design program, 401: circuit description of integrated circuit,

Page 19 1244583 _Case No. 92127914_Year Month Day__ Brief description of diagrams 4 0 3: Circuit diagram input and network list, 4 0 5: Drawing and wiring tools, 4 0 7: Integrated circuit wiring database, 4 0 9 _ · Send the final wiring database of the integrated circuit to the chip manufacturer, 4 1 1: Clock network optimizer control file, 4 1 3: Clock network optimizer application, 5 0 0 : Clock network optimizer application program 4 1 3 General function flowchart of program coding, 5 0 1: Identify jumper, 5 0 3: Calculate the unit length capacitance of clock trace with jumper, 5 0 5: Calculate additional capacitance per unit length at the crossover point, 5 0 7: Find the corresponding reference trace width reduction parameter required for capacitance compensation, 5 0 9 ·. Reduce the obtained reference trace width The parameters are applied to the wiring database file, 600: block diagram, 601, 602: logic block 1, logic block 2, 6 0 4, 6 0 5: internal report P-day pulse signal LCLK1, LCLK2, 6 0 3: data Bus

Cl, C2, C3, C4, C5, C6: Capacitance, D: Distance between signal trace and ground trace, W: trace width, W2: width at the crossover point.

Page 20

Claims (1)

1244583 _ Case No. 92127914 g_ifi_ VI. Application scope 1 · An integrated circuit (IC) clock network capacitance optimization method, including: Identifying any crossover points between clock traces and signal traces , Where each clock trace is masked by reference traces routed on both sides of the clock trace; and reduce the clock trace capacitance to the reference trace capacitance at the identified crossover point. 2 · The method for optimizing the clock network capacitance of an integrated circuit as described in item 1 of the scope of the patent application, wherein the method of reducing the clock trace capacitance to the reference trace capacitance includes reducing the capacitance at the identified crossover point. Decrease the reference trace width. 3. The method for optimizing the capacitance of the integrated circuit clock network as described in item 2 of the scope of patent application, wherein the method of reducing the width of the reference trace includes trimming the reference trace. 4 · The method for optimizing the capacitance of the integrated circuit clock network as described in item 3 of the scope of patent application, wherein the method of trimming the reference trace includes grooving the reference trace. 5 · The method for optimizing the capacitance of the clock network of the integrated circuit as described in item 2 of the scope of the patent application, further comprising: obtaining the unit length capacitance of the clock trace with the identified crossover point and signal trace ; Calculate the additional capacitance between the clock trace and the signal trace at the identified crossover point; Calculate the reference trace that needs to be used at the identified crossover point to offset the additional capacitance The amount of width reduction; and Page 21 1244583 Case No. 92127914 Month, Amendment 6. Scope of Patent Application Reduce the reference trace width at the identified crossover points. 6 · The method for optimizing the integrated circuit clock network capacitance as described in item 5 of the scope of the patent application, further comprising: receiving an integrated circuit wiring database by an application program, wherein the application program performs identification of jumper points, Calculate the unit length capacitance of the clock trace with the identified crossover point, calculate the additional capacitance between the clock trace and the signal trace, and calculate the width reduction of the reference trace; and the application modifies the Route the library to reduce the reference trace width. 7. The method for optimizing the integrated circuit clock network capacitance as described in item 5 of the scope of patent application, further comprising: executing a wiring tool to generate a wiring database of the integrated circuit; when wiring, the wiring tool It is a control file that optimizes the capacitance of the clock network of the integrated circuit; the control file identifies the jumper point, and then calculates the unit length capacitor with the clock trace that identifies the jumper point, and calculates the clock The additional capacitance between the trace and the signal trace is used to calculate the width reduction of the reference trace; and the control file and the routing tool are used to reduce the width of the reference trace. 0 · · Add a circuit to the integrated circuit Methods on the circuit, including: Wind the first and second ground traces to both sides of the clock trace on the first layer; determine the crossover point between the clock trace and the signal trace wound on the second layer; as well as Page 22 1244583 _ Case No. 92127914 _ month and month Amendment_ VI. Patent Application Scope Reducing the width of the first and second ground traces at the crossover points, respectively. 9 · A method for adding a circuit to an integrated circuit as described in item 8 of the scope of the patent application, wherein the winding method includes winding the first and second ground traces so that they have approximately equal widths from the clock The distances of the traces are approximately equal. 10 · The method for adding a circuit to an integrated circuit as described in item 8 of the scope of patent application, further comprising: generating a circuit wiring material library, and performing an encoding operation on the wiring database; and This code determines the jumper 'to modify the routing library to reduce the respective widths of the first and second ground traces at the jumper. 1 1 · A method for adding a circuit to an integrated circuit as described in item 10 of the scope of patent application, wherein the method for performing an encoding operation includes: performing drawing and wiring of one of application control network optimizer control files tool. 1 2 · The method for adding a circuit to an integrated circuit as described in item 10 of the scope of patent application, wherein the method for performing an encoding operation includes: performing a clock network optimizer application that modifies a completed wiring database Program. 1 3 · A method for adding a circuit to an integrated circuit as described in item 8 of the scope of patent application, wherein the method for reducing the respective trace width includes: each trace in the first and second ground traces Notch on at least one side. 1 4 / The method for adding a circuit to an integrated circuit as described in # 8 of the scope of patent application, further including: finding a unit length capacitance along a clock trace; finding a clock trace at a crossover point Additional power between the trace and the signal trace Page 23 1244583 _Case No. 92127914_year month__ Six, the scope of the patent application; and the width of the first and second ground traces needed to be used at the crossover point to offset the additional capacitance Decrease the amount. 1 5 · — A kind of integrated circuit, including: a clock trace located on the first layer, the distance between the clock trace and the first and second reference traces is approximately equal; a signal trace located on the second layer On the other hand, the signal trace crosses the clock trace; and the first and second reference traces have approximately the same width except that the width of the clock trace where the signal trace crosses is reduced. 16-The integrated circuit as described in item 15 of the scope of patent application, wherein the first and second reference traces are notched at the places where they cross the clock traces. 17 · The integrated circuit as described in item 15 of the scope of patent application, wherein the clock trace has a substantially uniform capacitance per unit length. 1 8 · ——A computer-readable recording medium incorporating a program code running in a circuit wiring database, where the program code includes: A first program code, identifying a bridge between a signal trace and a clock trace Point; a second program code that calculates a unit-length capacitance between a clock trace with at least one crossover point and the first and second reference traces with corresponding windings on both sides of the clock trace; A third program code to calculate the additional capacitance caused by the corresponding signal trace at each crossover point; and a fourth program code to calculate the additional capacitance at each crossover point Page 24 1244583 _Case No. 92127914_Year Month Date__ VI. Scope of Patent Application The width reduction of the corresponding first and second reference traces required. 1 9 · Incorporate a computer-readable recording medium running in the circuit wiring database program code as described in item 18 of the scope of patent application, where the program code further includes: a fifth program code to modify the circuit wiring database 'Reduce the respective first and second reference trace widths by the calculated width reduction. 20 · The computer-readable recording medium incorporated in the program code of the circuit wiring database as described in item 19 of the scope of the patent application, wherein the fifth program code is the corresponding first The first and second reference traces are slotted. Page 12 1244583 -200 -203 @ © Data bank LCLK1 LCLK2 η 204 r 205 Time 2nd