JP2001160548A - Method of manufacturing semiconductor device and semiconductor device manufacturing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method wherein sufficient resist residual film is ensured on a shoulder part of a large area resist pattern when an interlayer dielectric is etched and dimension shift after etching is restrained, and a semiconductor device manufacturing system. SOLUTION: In dry etching of an interlayer dielectric 14 in which a photoresist mask 16 is used as a mask, the maximal temperature of a substrate is controlled to be lower than a resist heat resistance temperature which is regulated on the basis of the heighest temperature which is applied to the resist by treatment such as baking and UV cure before etching, and etching is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly, to secure a sufficient resist remaining film even at the shoulder of a large-area resist pattern at the time of etching an interlayer film to suppress a dimensional shift after etching. The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing system using dry etching.

[0002]

2. Description of the Related Art At present, dry etching using plasma is mainly used in a processing step of a semiconductor device manufacturing method.
In most cases, a photoresist used in a lithography process is used as a mask for dry etching. In addition, since the photoresist is made of an organic material, the heat resistance temperature is relatively low from 120 ° C. to 150 ° C. Therefore, a process such as UV (ultraviolet) cure is added before the etching process. In this case, the resist heat resistant temperature is determined by the processing temperature at that time. The substrate stage temperature is set so that the substrate temperature during the dry etching process does not exceed the resist heat resistant temperature.

[0003]

However, the photoresist made of an organic material used in the above-described semiconductor device manufacturing method has low etching resistance under some plasma conditions such as metal etching and oxide film etching. . Also, the margin for mask selectivity is small at the shoulder where the sputtering rate is high. In particular, when there is a large-area resist pattern as seen at the time of etching an interlayer film, the resist is largely negatively charged up at the end (shoulder), and ions are locally concentrated. As a result, there is a problem that the mask easily recedes and becomes tapered.

The present invention has been made in view of such a problem, and an object of the present invention is to secure a sufficient resist remaining film even at the shoulder of a large-area resist pattern at the time of etching an interlayer film and to perform etching after etching. It is another object of the present invention to provide a semiconductor device manufacturing method and a semiconductor device manufacturing system that suppress a dimensional shift of a semiconductor device.

[0005]

The gist of the present invention is that, in dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate on which the interlayer insulating film is formed is determined. There is provided a method of manufacturing a semiconductor device, characterized in that etching is performed by controlling the resist to a temperature lower than a resistable heat resistance temperature defined based on the highest temperature applied to the resist by baking or UV curing before etching. Further, the gist of the invention according to claim 2 is that, in dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate at which the interlayer insulating film is formed is baked or etched before the etching. There is provided a method of manufacturing a semiconductor device, characterized in that etching is performed while controlling from a resist heat-resistant temperature of −5 ° C. or more, which is defined based on the highest temperature applied to the resist in the UV curing process, to less than the resist heat-resistant temperature. The gist of the invention described in claim 3 is that after plasma discharge,
0 seconds later, after the substrate temperature reaches the resist heat-resistant temperature of -5 ° C, the surface layer fluidization reflow of the resist is started gradually from the temperature of the resist heat-resistant temperature of -5 ° C to complement the shoulder portion cut by the etching species. A semiconductor device manufacturing method according to claim 2. The gist of the invention described in claim 4 is that, in dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate on which the interlayer insulating film is formed is baked or etched before etching. There is provided a semiconductor device manufacturing system having means for performing etching by controlling the resist to a temperature lower than a resistable heat resistance temperature defined based on the highest temperature applied to the resist in the UV curing process. Also,
The gist of the invention described in claim 5 is that, in dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate on which the interlayer insulating film is formed is baked or UV cured before etching. There is provided a semiconductor device manufacturing system having means for controlling etching from a resist heat-resistant temperature of −5 ° C. or more, which is defined based on the highest temperature applied to the resist in the processing, to less than the resist heat-resistant temperature. Claim 6
The gist of the invention described in the above, after the substrate temperature reaches the resist heat-resistant temperature -5 ℃ 20 to 30 seconds after the plasma discharge,
The semiconductor device manufacturing system according to claim 5, wherein the reflow of the surface layer of the resist is started gradually from the temperature of the resist heat-resistant temperature of -5 ° C to compensate for the shoulder portion shaved by the etching species.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of the present invention is that, in dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate for forming the interlayer insulating film is determined by baking and UV curing before etching. The point that the etching is performed by controlling the temperature below the resist heat resistant temperature defined based on the highest temperature applied to the resist in the processing such as,
Alternatively, the etching is performed by controlling the resist heat-resistant temperature to −5 ° C. or higher and lower than the resist heat-resistant temperature.

When the present invention is applied to dry etching of an interlayer insulating film using a photoresist as a mask, the substrate temperature reaches -5.degree. The surface layer fluidization (reflow) of the resist gradually starts from the temperature of ° C., and complements the shoulder portion cut by the etching species. This is particularly effective for etching a contact hole or a via hole having a large area resist pattern or for etching a groove. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a process flow schematic diagram for explaining a semiconductor device manufacturing method according to a first embodiment of the present invention. In FIG.
10 is a groove for groove wiring, 12 is an etching stopper film, 1
4 denotes an interlayer insulating film, and 16 denotes a photoresist mask.

As a first embodiment, a case where a groove 10 for a 0.3 μm-wide groove wiring is formed by a resist mask will be described. The shape before etching is shown in FIG. 50 nm of Si ₃ N ₄ as the etching stopper film 12 and 1500 nm of SiO ₂ as the interlayer insulating film 14 (nm = 1)
(One billionth of a meter). The photoresist mask 16 (PR) has a thickness of 700 nm and a width of 0.3 μm by KrF (krypton fluoride) excimer laser exposure.
Resolved. The photoresist mask 16 (PR) was processed at 120 ° C. in a bake after the development processing. That is,
The photoresist mask 16 (P
The heat-resistant temperature of R) is 120 ° C. The apparatus used for etching is a general parallel plate RIE (Reactive I
on Etching) apparatus under conditions of CHF ₃ /
CO / Ar = 70/40/200 (sccm: stan)
dar cubic cm), pressure 20mTorr,
The test was performed at a stage temperature of 38 ° C. According to these conditions, SiO
₂ (interlayer insulating film 14) etch rate: 620 nm / sec,
The SiO ₂ (interlayer insulating film 14) / PR selectivity is 6,
The selectivity ratio of SiO ₂ (interlayer insulating film 14) / Si ₃ N ₄ (etching stopper film 12) is 52, and there is no problem in etching of this structure. However, there is little margin for the selection ratio to PR, and there is no particular margin at the shoulder of the large area pattern.

[0010] etching (C _x F _y plasma etching) is started, because until 10-20 seconds radiant heat from the plasma to be absorbed by the chamber wall or the like, the substrate temperature is not sufficiently heated. During that time, the etchant concentrates on the shoulder of the large-area pattern, so that the resist falls off (see FIG. 1B). Twenty to thirty seconds after the start of the etching, the substrate reaches the resist heat-resistant temperature of the photoresist mask 16 (PR) of −5 ° C.
(PR) is directed toward the groove portion (groove 10 for groove wiring) so as to complement the shoulder-dropped portion (the direction of the arrow (→ ←) in the figure).
2) The surface layer reflows (see FIG. 1 (c)). By controlling the substrate temperature with high precision so as not to exceed the resistable heat resistance temperature of the photoresist mask 16 (PR), the degree of registry flow of the photoresist mask 16 (PR) can be controlled. In the case of this condition, the CD difference after etching is -7 nm or more +7
nm or less (see FIG. 1 (d)).

As described above, according to the first embodiment, in the dry etching of SiO ₂ (interlayer insulating film 14) using the photoresist mask 16 (PR) as a mask, the maximum temperature of the substrate temperature is set to Before the etching, baking, UV curing, or the like is performed to control the resist to a temperature lower than the resistable heat resistance temperature specified based on the highest temperature applied to the photoresist mask 16 (PR) by the highest temperature. Etching can be performed while maintaining a sufficient resist residual film margin even at the shoulder of the large area pattern. As a result, the trenches 10 for contact and via hole etching and trench wiring are formed.
It is possible to solve the problem such as the widening of the frontage dimension in the etching such as the above etching. Further, in the case where further miniaturization proceeds in the future, the photoresist mask 16 (PR) tends to be thinner in order to obtain a sufficient resolution, but in such a case, etching can be performed with a sufficient margin.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a schematic process flow chart for explaining a semiconductor device manufacturing method according to a second embodiment of the present invention. In FIG. 2, 12 is an etching stopper film, 14 is an interlayer insulating film,
Reference numeral 16 denotes a photoresist mask, and reference numeral 18 denotes a via hole.

As a second embodiment, a resist mask
To form a via hole 18 having a hole diameter of 0.25 μm
Indicates a match. Etching (C_xF_yPlasma etching)
The previous shape is shown in FIG. Etching stopper film 1
2 is 50 nm in TiN as the interlayer insulating film 14.
SiO₂(Interlayer insulating film 14) having a thickness of 1500 nm
I have. The photoresist mask 16 (PR) has a thickness of 700
0.25 nm in diameter by KrF excimer laser exposure
It was resolved to μm. The photoresist mask 16 (PR)
After baking after development processing, processing at 120 ° C was performed.
Photoresist mask 16 (PR) in the embodiment
Is 120 ° C. For etching
The device used was a general parallel plate RIE device.
CHF₃/ CO / Ar = 80/60/200 (scc
m), pressure 30 mTorr, stage temperature 38 ° C
Was. According to these conditions, SiO₂(Interlayer insulating film 14)
Tilate: 720 nm / sec, SiO₂(Interlayer insulating film 1
4) / PR selectivity is 8, SiO ₂(Interlayer insulating film 14) /
The selectivity of TiN (etching stopper film 12) is 61.
There is no problem on the etching of the present structure. But the stage
When performed at a low temperature of about 0 to 20 ° C,
There was a problem that the frontage of the hall widened in the latter half of the ching.

Since the substrate temperature is not sufficiently heated from 10 to 20 seconds after the start of the etching, the etchant concentrates on the shoulder, so that the photoresist mask 16 (PR) falls off the shoulder (see FIG. 2B). ). After starting etching 2
After 0 to 30 seconds, the substrate becomes a photoresist mask 16
(PR) reaches the resist heat-resistant temperature of -5 ° C., and the photoresist mask 16 (PR) is directed toward the groove (via hole 18) (in the direction of the arrow (→ ←) in FIG. 2) The surface layer reflows (see FIG. 2 (c)). By controlling the substrate temperature with high precision so as not to exceed the resistable temperature of the photoresist mask 16 (PR), the photoresist mask 16 (PR)
Registry flow can be controlled. Under this condition, the CD difference after etching is-
It was not less than 5 nm and not more than +5 nm (see FIG. 2D).

It should be noted that the present invention is not limited to the above embodiments, and each embodiment can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment,
The number, position, shape, and the like suitable for carrying out the present invention can be obtained. In each drawing, the same components are denoted by the same reference numerals.

[0016]

As described above, according to the present invention, in the dry etching of an interlayer insulating film using a photoresist as a mask, the maximum attainment temperature of the substrate temperature is set to the resist by a treatment such as baking or UV curing before etching. Resist heat-resistant temperature -5 specified based on the highest temperature applied
By performing the etching while controlling the temperature to not less than ° C. or less than the resist heat resistant temperature, it is possible to perform etching while maintaining a sufficient resist residual film margin even at the shoulder of a large-area pattern which is originally easily etched.

[Brief description of the drawings]

FIG. 1 is a process flow schematic diagram for explaining a semiconductor device manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a schematic process flow chart for explaining a semiconductor device manufacturing method according to a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Groove for wiring 12 ... Etching stopper film 14 ... Interlayer insulating film 16 ... Photoresist mask 18 ... Via hole

Claims (6)

[Claims] In the dry etching of an interlayer insulating film using a photoresist as a mask, the maximum temperature of the substrate temperature at which the interlayer insulating film is formed is applied to the resist by baking or UV curing before etching. A method for manufacturing a semiconductor device, characterized in that etching is performed by controlling the temperature below a resist heat-resistant temperature specified based on the highest temperature. 2. In dry etching of an interlayer insulating film using a photoresist as a mask, the highest temperature of the substrate temperature at which the interlayer insulating film is formed is applied to the resist by baking or UV curing before etching. Resist heat resistant temperature specified based on the highest temperature-
A method of manufacturing a semiconductor device, wherein etching is performed at a temperature of 5 ° C. or higher and lower than the resistable heat resistance temperature. 3. After 20 to 30 seconds from the plasma discharge, when the substrate temperature reaches the resist heat resistant temperature of -5 ° C., the surface fluidization reflow of the resist is started gradually from the resist heat resistant temperature of -5 ° C. The method according to claim 2, wherein the shoulder cut by the seed is complemented. 4. In dry etching of an interlayer insulating film using a photoresist as a mask, the highest temperature of the substrate temperature at which the interlayer insulating film is formed is applied to the resist by baking or UV curing before etching. A semiconductor device manufacturing system, comprising: means for performing etching by controlling the temperature below a resist heat resistance temperature defined based on the highest temperature. 5. In dry etching of an interlayer insulating film using a photoresist as a mask, the highest temperature of the substrate temperature at which the interlayer insulating film is formed is applied to the resist by baking or UV curing before etching. Resist heat resistant temperature specified based on the highest temperature-
A semiconductor device manufacturing system, comprising: means for controlling etching from 5 ° C. or higher to lower than a resist heat resistant temperature to perform etching. 6. After 20 to 30 seconds from the plasma discharge, when the substrate temperature reaches a resist heat-resistant temperature of -5 ° C., the surface fluidization reflow of the resist is started gradually from the temperature of the resist heat-resistant temperature of -5 ° C. The semiconductor device manufacturing system according to claim 5, wherein the shoulder portion shaved by the seed is complemented.