KR100281866B1 - Critical dimension control in integrated circuit fabrication using plasma etching and plasma polymerization - Google Patents

Abstract

Disclosed herein is a method of etching a first film layer or layers on a wafer. The method can prevent or control critical dimension (CD) microloading and can eliminate or minimize etch bias.

Description

CRITICAL DIMENSION CONTROL IN INTEGRATED CIRCUIT FABRICATION USING PLASMA ETCHING AND PLASMA POLYMERIZATION}

Technical Field

The present invention relates to a method of etching films on a wafer in the manufacture of an integrated circuit device. Specifically, the etching method of the present invention eliminates or controls critical dimension microloads and etch bias.

Background of the Invention

Conventional methods of manufacturing integrated circuit devices use both lithographic and etching processes. In the lithographic process, a layer of resist material is applied on the first film layer (or layers) of the wafer. Optionally, a bottom antireflective coating (BARC) material layer and a top antireflective coating (TARC) material layer are applied to the top and bottom of the resist layer, respectively. The resist layer is then exposed, for example, by irradiating the resist layer with I-line ultraviolet light or deep ultraviolet wavelength light that has passed through the patterned reticle. Thereafter, the exposed resist is developed. At the time of development, depending on whether a positive resist material or a negative resist material is used, portions of the resist layer that have been contacted or not in contact with the light are dissolved, so that the resist developed on the first film layer Leave a patterned mask of material. The pattern of the mask matches the pattern of the reticle.

Thereafter, the first film layer is etched. During the film layer etching step, those portions of the first film layer that are not masked by the mask are etched away. As a result, the pattern of the mask is etched constantly in the first film layer (s).

It is commonly known that semiconductor integrated circuits are decreasing in size but increasing in speed and density. An obstacle to further development is the lithographic phenomenon known as the "optical proximity effect". As a result of the optical proximity effect, the tightly spaced resist lines and openings in the mask for a particular die are formed thinner or smaller than the resist lines and openings, perhaps having substantially the same size, that are substantially separate. Thus, the corresponding densely spaced film layer lines and holes that are etched into the first film layer in subsequent film layer etching steps have different sizes. This phenomenon is known as ″ critical dimension (CD) microloading ″.

CD microloading adversely affects both manufacturing yield and circuit performance. Conventional solutions for reducing CD microloading, such as optical proximity correction masks and abnormal masks, are complex and expensive for mass production.

Another obstacle to further increase in density and further decrease in size is mask corrosion in the step of etching the first film layer. As a result of the mask corrosion, the size of the film layer etched in the first film layer is different from the size of the corresponding mask feature. For example, the width of the line etched in the first film layer is narrower than the width of the resist line used as a mask for that film layer line. As another example, the width of the contact holes etched in the first film layer is slightly larger than the corresponding holes in the resist mask. Manufacturers of integrated circuits consider resist corrosion by forming resist mask features that are slightly larger (lines) or slightly smaller (lines) in size than the size of the corresponding film layer desired to be etched into the first film layer.

The difference in size between the mask feature and the film layer feature substantially etched in the first film layer and masked by the mask feature is known as the "etch bias" of the etching process. The ideal etch bias is zero (0).

The etch bias can be accommodated, for example, in a portion where there is a sufficiently wide space between the resist lines of the mask. However, for a technical level device at some point where the resist lines are densely integrated, the spacing between the mask features cannot be easily reduced. In addition, it is increasingly difficult to print smaller openings in masks for contact holes and vias because conventional I-line photolithography processes are approaching resolution limits.

Thus, there is a great need for an integrated circuit fabrication method that eliminates or controls CD microloading and eliminates or minimizes etch bias.

1 is a flow chart of a method of etching a first film layer of a wafer.

2 is a cross-sectional side view of a portion of a die of a wafer with a patterned mask of developed photoresist material formed thereon, the mask having densely spaced and separated resist features having different widths;

3 is a flow chart of a modification method of etching a first film layer of a semiconductor wafer.

A method of etching a first film layer or layers on a wafer is disclosed and provided examples are provided. The method allows the prevention or control of CD microloading and the removal or control of etch bias.

In one embodiment of the method belonging to the present invention, step 1 provides a semiconductor wafer having a first film layer to be etched. Step 2 forms a patterned mask of resist material exposed and developed on the first film layer. The resist mask masks the first film layer in a subsequent plasma etching step. The mask formed by step 2 has a repeating pattern for each integrated circuit die of the wafer. The portions of the mask for each die have tightly spaced and separated features. Densely spaced and separated resist features have sidewalls and widths.

Due to the optical proximity effect or for some other reason in the lithographic process, the tightly spaced resist features of the mask for the die are narrower in width than the separate resist features of the mask for the same die.

Step 3 plasma etches the first film layer to form etched film layer features and also forms a plasma polymer on the resist mask and the first film layer. The process parameters for step 3 are selected such that upon completion of such a step, the widths of the densely spaced and separated features etched in the film layer are the same, ie no CD micro loading is present. Step 3 The process parameter is also chosen such that there is no etch bias for the separated etched film layer features and only a small etch bias for the closely spaced etched film layer features.

In an alternative method, steps 1 and 2 are the same, but the third step shown herein as step 3A is different. In step 3A, the process parameters are such that upon completion of the plasma etching and plasma polymerization steps, the densely spaced and separated etched film layer features have the same width, i.e. no CD microloading is present, and the densely spaced etching There is no etch bias for the etched film layer features, and only a small etch bias is selected for the separated etched film layer features.

Example

1 is a flowchart of a method of etching a first film layer of a wafer. The method of FIG. 1 achieves zero CD micro loading, zero etch bias for discrete features of the die and minimum etch bias for tightly spaced features of the die.

Step 1 in the FIG. 1 process provides a wafer having a film layer (or layers) to be etched. 2 shows a cross-sectional view of a portion of wafer 20 corresponding to a portion of an integrated circuit die. As you know, there are a plurality of identical dies on a single wafer.

The wafer 20 has a first film layer 21 to be etched. The invention is not limited to the particular type of film (or films) or multiple film layers to be etched. For convenience, the expression ″ first film layer ″ as used herein includes both a single film layer and a stack of two or more film layers. For example, the first film layer 21 may be a polysilicon layer applied with a cap oxide layer. Alternatively, the first film layer 21 may be an aluminum alloy film, a nitride film, or an oxide film layer. There is typically an etch stop layer just below the film layer or layers of the wafer to be etched. The etch stop layer may be a thermal oxide, for example the film layer directly above the thermal oxide is polysilicon, nitride, or metal. Alternatively, a silicon substrate may be under the first film layer 21.

Step 2 in the process of FIG. 1 forms a patterned mask of resist material exposed and developed on the first film layer 21. A conventional lithographic process is used in step 2. The lithographic process used is variable. Suitable lithographic processes include I-line wavelength ultraviolet light, deep ultraviolet wavelength light, electron beams, or X-ray lithography processes. For example, step 2 applies a layer of resist material on the first film layer 21. The resist layer is then exposed using I-line wavelength ultraviolet light. The exposed resist is then developed with a chemical solution to form a patterned mask.

Preferably, the lithographic process is optimized through focus and exposure matrix experiments. Such experiments allow those skilled in the art to select and maximize a process in which the etch bias, and consequently the post etch feature size, is not affected by small changes in focus and exposure.

The resist mask formed by step 2 may be used in a resist feature, such as a mask, to deliver the same resist mask pattern on each of the integrated circuit dies of the wafer 20 during subsequent steps of etching the first film layer 21. It has a repeating pattern of lines and openings. 2 shows a patterned mask 22 of exposed and developed photoresist material on the first film layer 21. Mask 22 of FIG. 2 corresponds to a portion of the mask for etching one integrated circuit die of wafer 20. In a variant embodiment, a BARC material layer is applied between the first film layer 21 and the mask 22.

The mask 22 of FIG. 2 has four identically sized resist lines 23 proximate to each other. Further, in the mask 22, there are openings indicated by the openings 25 between each of the resist lines 23. During step 3, the resist line 23 masks portions of the first film layer 21 so that, upon completion of step 3, the film layer features corresponding to the resist line 23 have a first film layer for each die. It is etched in 21.

Resist line 23 shows the tightly spaced resist characteristics of the mask for a portion of the die of wafer 20. As an example, the resist lines 23 may be spaced apart from each other at intervals up to approximately 0.5 micrometers. Such tightly spaced features may be part of a memory array, for example.

The mask of FIG. 2 also has a separate resist line 24 which is shown to have been moved laterally from the resist line 23. The resist line 24 has a side wall 27. Resist line 24 shows the separate resist characteristics of the mask for the same die of wafer 1. As an example, resist line 24 is separated from other resist features of mask 22 at intervals of approximately 1.0 micrometers or more. As another example, the separated features are spaced from resist features that are at least twice as different as the narrowly spaced features. Resist line 24 may be a mask for part of an analog circuit.

During step 3, the resist line 23 masks a portion of the first film layer 21, so that upon completion of step 3, the film layer feature corresponding to the resist line 24 is etched into the first film layer 21. do.

The resist line 24 of FIG. 2 is shown wider than each resist line 23. The resist line 24 should be equal to each resist line 23 in width, but the resist line 24 is larger than the resist line 23 in size due to the optical proximity effect during lithography step 2 or for some other reason. It is assumed that it is formed widely. As an example, the width of each resist line 23 may be 0.44 to 0.46 micrometers and the width of the resist line 24 may be 0.48 micrometers. The difference in width is from 0.02 to 0.04 micrometers or approximately 8% of the width of the separated resist line 24.

Step 3 of FIG. 1 plasma etches the first film layer 21 of the wafer 20 of FIG. 2 and forms a polymer on the mask 22 and the first film layer 21 by plasma polymerization. The plasma polymer is deposited on the sidewalls of the film layer feature (masked by resist lines 23, 24) that are etched into the first film layer 21 and on the sidewalls 26, 27 of the mask 22. Will be Step 3 balances the plasma etch and plasma polymerization so that precise control of the etched film layer feature size is made for the closely spaced and separated features of each die.

Plasma polymerization refers to the formation of polymers from process gases, photoresists, and substrate fragments among other possible sources. The formation of plasma polymers is facilitated by the addition of halogen-containing species to process gases such as Cl ₂ , HBr, BCl ₃ , C ₂ F ₆ , and other species containing high nonmetallic free radicals or atoms.

Deposition of the plasma polymer in a selected amount on the sidewalls of selected resist lines or openings in the mask can prevent resist corrosion and, if deposited in a sufficient amount, will even allow resist mask features to increase in size Can be. In addition, depositing the plasma polymer in a selected amount on the sidewalls of the film layer features etched into the first film layer 21 can control the degree of inactivation of the sidewalls. For such control, the degree of horizontal etching at the sidewalls of the film layer features, and ultimately the width, can be precisely controlled.

In order to improve CD micro loading and achieve the etch bias objective described above for the process of FIG. 1, step 3 is a separate mask feature (eg, resist line 24) to maintain zero etch bias for the separated feature. A sufficient amount of plasma polymer is formed on the sidewalls of and on the sidewalls of the corresponding discrete film layer features that are etched into the first film 21. In addition, step 3 is relatively large on the sidewalls of the densely spaced mask features (eg, resist lines 23) and on the sidewalls of corresponding densely spaced film layer features that are etched into the first film layer 21. Form positive plasma polymer. A relatively large amount of plasma polymer deposited on the sidewalls of the densely spaced resist lines 23 and corresponding film layer features etched into the first film layer 21 is (1) resist lines 23 Increase the width of the densely spaced resist lines 23 so that the width of N) is equal to the width of the separated resist lines 24; And (2) the sidewalls such that the densely spaced film layer feature etched in the first film layer 21 adjacent the resist line 23 is equal to the width of the separated etched film layer feature masked by the resist line 24. It is sufficient to reduce the degree of horizontal etching of the first film layer 21 adjacent to the resist line 23 through deactivation.

Step 3 of the process of FIG. 1 is designed such that a smaller amount of plasma polymer is formed in the region of the mask and die having more discrete features in the region of the mask and die having dense features. In areas where less amount of plasma polymer is formed, there is more horizontal etching and less sidewall deactivation of the film layer at the sidewalls.

In order to achieve this preferred etch and polymer forming capability, step 3 is a region having dense features of the mask (eg, resist lines 23) rather than being in regions of discrete features (eg, regions of resist line 24). It is designed to take advantage of the relatively high resist concentration present in the region of). Since a large number of resists can be used in areas of tightly spaced features, step 3 is relatively large in areas with the dense features of the mask that require the most inert plasma polymer rather than in the areas of discrete features of the mask. To form an inert plasma polymer.

In addition, step 3 is performed on the sidewalls in the region having the dense features, rather than inactivating the separated sidewalls, in a region having many dense features of the mask for the die, the particular reactive polymer species formed in the plasma reaction is present on the separated sidewalls. It is designed to take advantage of the fact that it has a greater likelihood of deactivating sidewalls in areas with dense features by being present at. To illustrate, certain reactive plasma polymer species may be visualized as ″ sticky balls ″ that collide with the resist or etched film layer feature sidewalls and instantly attach to the resist or etched film layer feature sidewalls. Referring to FIG. 2, in the region having the dense feature of the mask indicated by the resist line 23, the sticky balls entering the openings in the mask 22 in a square shape are formed of one resist line 23 and the adjacent resist line 23. The boundary can be marked before and after the dense space between the side walls 26. In contrast, similar sticky balls striking squarely with the side wall 27 of the separated resist line 24 mark the boundary away from the resist line 24. Thus, at any given point in time, the sticky balls (ie, reactive plasma polymer species) are present on the separated mask or etched film layer sidewalls, thereby densely spaced masks or rather than inactivating the separated mask or etched film layer sidewalls. By being on the etched film layer sidewalls there is a greater possibility of deactivating the densely spaced mask or etched film layer sidewalls.

Step 3 is carried out in a plasma etch reactor capable of anisotropic etching. In a manner known in the art, different plasma etch reactors and processes are useful for etching different types of films, such that those skilled in the art should select the etch reactor and adjust the process according to the application. The chosen plasma etch reactor and process should have a low non-uniformity value that achieves a constant etch rate and is below a certain value. For example, the three sigma non-uniformity value should be less than 10 or 5 and lower values are better. Plasma etch reactors useful in the present invention include, for example, a TCP 9400 high density low pressure plasma etch reactor for etching polysilicon, nitride, and oxide films, and a TCP 9600 high density low pressure plasma etch reactor for etching aluminum alloy films. TCP 9400 and 9600 reactors are commercially available from Lam Research Corporation, Fremont, California. Optionally, the MXP 5000 high density low pressure plasma etch reactor may be used for polysilicon films. MXP 5000 reactors are commercially available from Applied Materials Corporation, Santa Clara, California.

In a manner known in the art, the consistency of the etch rate for a given high density low pressure plasma etch reactor and process is determined by various factors including etch chamber conditioning and cleaning, etch chemicals already used in the same reactor, and etch chamber idle time. get affected. Those skilled in the art should monitor such factors to ensure a consistent etch rate.

If a BARC layer is present between the resist mask 22 and the first mask layer 21, the step of etching the BARC layer must be carried out before etching the first film layer 21. The process parameters for this BARC layer etch step should be chosen to achieve a constant BARC layer etch rate in the lateral direction.

Consistent plasma strike and stable plasma for the BARC layer etch step and the first film layer etch step may be achieved by performing stabilization of the chamber prior to striking the plasma. During this chamber stabilization step, the etch chamber pressure and gas composition are optimized to control the feature size.

Step 4 of the FIG. 1 process removes remaining photoresist, BARC material (if present), plasma polymer, or other byproducts of step 3 from wafer 20. Conventional methods such as wet stripping or a combination of ashing and wet stripping can be used for this step.

3 is a flowchart of a modification method for etching a first film layer of a semiconductor wafer. The method of FIG. 3 is identical to the method of FIG. 1 except for step 3A. The method of FIG. 3 is useful for achieving zero CD micro loading, zero etch bias for the closely spaced features of the die and minimal etch bias for the discrete features of the die. The process of FIG. 3 achieves a different result than the process of FIG. 1 because different methods are used in step 3A of FIG. 3 rather than step 3 of FIG. Step 3A takes a different balance between plasma etching and plasma polymerization.

As with step 3 of FIG. 1, step 3A of FIG. 3 corresponds to a plasma etch of the first film layer 21 and to be etched on the sidewalls 26, 27 of the resist mask feature and within the first film layer 21. The polymer is formed by plasma polymerization on the sidewalls of the film layer features.

Step 3A of FIG. 3, unlike step 3 of FIG. 1, forms and deposits relatively few polymers on the sidewalls of the closely spaced and separated mask and etched film layer features. Nevertheless, the amount of plasma polymer deposited on the mask sidewalls 26 and 27 and corresponding film layer sidewalls during step 3A of FIG. 3 maintains (1) zero etch bias for tightly spaced features and And (2) densely spaced film layer features etched into the first film layer 21 by preventing most of resist corrosion and horizontal etching of the separated mask and film layer features, but not all of them ( For example, a separate film layer feature (eg, film layer line masked by resist line 24) in which the final width of the film layer line masked by resist line 23 is etched into the first film layer 21. It is enough to make it equal to the width of. After step 3A, there is a small amount of etch bias for the isolated feature because there is a controlled small amount of horizontal etching on the sidewall of the isolated feature.

The exemplary process of FIGS. 1 and 3 achieves zero CD micro loading, but results in somewhat different results related to etch bias. In particular, step 3 of the FIG. 1 process achieves zero etch bias for the discrete features of the die, even though they have less etch bias (approximately 0.01 to 0.02 micrometers or less than 8%) for densely spaced features. This solution may be optimal if the discrete features are part of the die's critical analog circuitry. In contrast, step 3A of the FIG. 3 process applies zero etch bias to the densely spaced features of the die, even though they have a small etch bias (less than approximately 0.01 to 0.02 micrometers or less than 8%) for discrete features. Achieve. This second solution may for example be optimal for a memory device.

The process of FIGS. 1 and 3 results in different results because of the different choice of process parameters in step 3 of FIG. 1 relative to step 3A of FIG. One skilled in the art can disclose processes that result in the results of FIG. 1 or 3, or different results suitable for the application.

For example, the process parameters of step 3 or 3A may have a difference in width between the densely spaced etched film features and the separated etched film layer features with a selected non-zero amount, but nevertheless tightly spaced resist. The difference can be adjusted to be less than the difference in width between the feature and the separated resist feature. Although CD microloading is not prevented, the performance and yield can be sufficiently improved for the particular application in which such a solution is useful. For example, a tightly spaced etch, although the difference in width between the tightly spaced and separated resist features of the mask for each die may be less than 8% of the separated resist features or 0.020 to 0.025 micrometers. The width of the separated film layer feature and the separated etched film layer feature may be selected to have a smaller difference, such as 3% or 0.005 micrometers of the width of the separated etched film layer feature. Such results can be obtained by adjusting the amount of plasma polymerization and the ratio of plasma etching.

The invention can also be combined with an optical proximity correction (OPC) mask to maximize the process window. This may be noticeable, for example, where the OPC mask has already been developed for such use and when the mask cost is not an important factor in the decision masking of those skilled in the art for that use.

Because of the variety of uses and etch reactors, the achievement of a given desired result (eg, the result of FIG. 1 or FIG. 3) requires the skilled person to properly select the process parameters. For example, taking a two-electrode reactor such as TCP 9400 or TCP 9600, the following range of process parameters is useful.

Pressure: 0.5 to 500 millitorr (mtorr)

RF power upper electrode: 50 to 1000 watts

RF power bottom electrode: 0-600 watts

Leak back ratio: 1 millitorr / min

Electrode temperature: 50-100 ℃

Chamber wall temperature: 50 to 100 ℃

To make the invention clearer, three detailed examples are provided below.

Example 1

The process of Example 1, like the process of FIG. 1, achieves zero CD micro loading and zero etch bias for discrete features of the die. Minimum etch bias on the order of 0.01 to 0.02 micrometers is achieved for the densely spaced features of the die.

Step 1 provides a wafer with a first film layer 21 to be etched. In this example, the first film layer 21 is a cap oxide layer 50-300 angstroms thick and a P-doped RTP polysilicon film or P-doped furnace (approximately 2,500-4,000 angstroms thick). ) An annealed polysilicon film layer. Underneath the polysilicon film layer is a thermal oxide film layer approximately 30 to 100 angstroms thick.

Step 2 forms a patterned mask of exposed and developed photoresist on the first film layer 21. A conventional I-line ultraviolet light lithography process with focus and exposure optimized through matrix experiments is used in step 2. The mask portion for each of the same dies of the wafer has not only separate features but also densely spaced features. Such masks may be used to separate discrete resist features (eg, resist lines 24) and dense spaced features (eg, resist lines 23) that are approximately 8% or approximately 0.01 to 0.02 micrometers in width of the separated resist features. The resist material is an OLIN OiR 897-9I resist layer with a thickness of 10,000 to 13,000 angstroms, such a resist is available from Olin Corporation, USA The BARC layer is not used.

Step 3 is carried out in a TCP 9400 high density low pressure plasma reactor having an upper electrode and a lower electrode. The electrode temperature is 70 ° C. Chamber temperature is 60 ° C. The gas used in step 3 was carbon tetrafluoride (CF ₄ ), hydrogen bromide (HB _r ), chlorine (Cl ₂ ), helium (He) and 70% helium 30% oxygen mixture (He / O ₂ ) to be.

Step 3 of Example 1 includes a breakthrough etch (BE) operation; Main etch (ME) operations on endpoints; And an overetch (OE) job with a duration that is a percentage of the total time of the main etch job. In addition, although not shown in Example 1 (or Examples 2 and 3 below), in each example a short chamber qualification cycle before each BE, ME, and OE operation where RF discharge is off and process gas is introduced into the chamber. Is present. Those skilled in the art will also appreciate that after the RF discharge is initiated, the plasma should be normalized for a short period of time before the measurement of the etch byproduct is taken.

The parameters for the BE, ME, and OE operations of step 3 are described below.

Parameter BE ME OE Pressure (mtorr) 10 20 80 RF power top (w) 250 200 250 RF power bottom (w) 150 200 200 CF4 (sccm) 100 Cl2 (sccm) 100 HBr (sccm) 150 100 He (sccm) 50 100 He-02 4 complete time To the end point % time 25 sec 90-150 seconds 120%

In an alternative embodiment, if an organic BARC layer was used, the BE step of this example can be lengthened to etch the BARC layer and cap oxide layer if necessary.

Example 2

The process of Example 2, like the process of FIG. 1, achieves zero CD micro loading and zero etch bias for discrete features of the die. Minimum etch bias on the order of 0.01 to 0.02 micrometers is achieved for the densely spaced features of the die.

Step 1 provides a wafer with a first film layer 21 to be etched. In this example, the first film layer 21 is an undoped crystalline polysilicon film or an undoped amorphous polysilicon film layer that is 1,500 to 4,000 angstroms thick. Such polysilicon is an extremely thin native oxide top layer that is approximately 15 Angstroms thick. Underneath polysilicon is a thermal oxide film layer approximately 30 to 100 angstroms thick.

Step 2 forms a patterned mask of exposed and developed photoresist on the first film layer 21. Through focus and exposure matrix experiments, a conventional I-line ultraviolet light lithography process is used in step 2. The mask portions for each of the same dies of the wafer have densely spaced features as well as discrete features. Such masks may include discrete features (eg, resist lines 24) and densely spaced resist features (eg, resist lines 23) that are approximately 0.01 to 0.02 micrometers or approximately 0.01 to 0.02 micrometers in width of the separated features. The difference between the widths of)). The resist material is an OLIN OiR897-RI resist layer that is 10,000 to 13,000 Angstroms thick. BARC layer is not used.

Step 3 is carried out in a TCP 9400 high density low pressure plasma reactor. The electrode temperature is 70 ° C. Chamber temperature is 60 ° C. The gas used in step 3 is a mixture of CF ₄ , HBr, Cl ₂ , He, and 70% He-30% O ₂ . Process parameters for the BE, ME, and OE operations of step 3 are as described below.

Parameter BE ME OE Pressure (mtorr) 10 20 80 RF power top (w) 250 240 250 RF power bottom (w) 150 120 180 CF4 100 Cl2 100 HBr 200 200 He 100 He-02 14 7 complete time To the end point % time 30 sec 90-150 seconds (max) 120%

Again, if an organic BARC layer was used in a variant embodiment, the BE step can be lengthened to etch the BARC layer and the original gate oxide on top of polysilicon if necessary.

Example 3

The process of Example 3, like the process of FIG. 3, achieves zero CD micro loading and zero etch bias for the densely spaced features of the die. Minimum etch biases on the order of 0.01 to 0.02 micrometers are achieved for the discrete characteristics of the die.

Step 1 provides a wafer with a first film layer 21 to be etched. In this example, the first film layer 21 is a first nitride film layer 1,500 to 2,000 angstroms thick and an underlying second thermal oxide film layer about 50 to 250 angstroms thick.

Step 2 forms a patterned mask of exposed and developed photoresist on the first film layer 21. After optimization through focus and exposure matrix experiments, a conventional I-line ultraviolet light lithography process is used in step 2. Mask portions for each of the same dies of the wafer have densely spaced and separated features. Such a mask is formed between the separated feature (eg, resist line 24) and the width of the densely spaced feature (eg, resist line 23) that is approximately 8% of the width of the separated feature or approximately 0.01 to 0.02 micrometers. Indicates a difference. In this example, the resist material is an OLIN OiR8997-9R layer that is 10,000 to 13,000 angstroms thick.

An organic BARC layer is present between the mask 22 and the nitride film layer 21. The organic BARC layer is formed of SHIPLEY AR2-601 organic BARC material and is approximately 660 angstroms thick. Such organic BARC materials are available from Shipley Company, USA.

Step 3A is used in a TCP 9400 high density low pressure plasma reactor. The electrode temperature is 70 ° C. Chamber temperature is 60 ° C. The gases used in step 3A are CF ₄ , HBr, He, and sulfur hexafluoride (SF ₆ ).

Step 3A of Example 3 has BE, ME, and OE operations. However, because of the organic BARC layer, additional work of etching the organic BARC layer is performed prior to the BE operation. Process parameters are described below.

Parameter BARC etch BE ME OE Pressure (mtorr) 10 20 40 20 RF power top (w) 250 600 550 500 RF power bottom (w) 150 50 60 CF4 100 100 80 HBr 50 20 50 SF6 50 He 100 complete time time To the end point time time 5-25 seconds 30 sec 80-120 seconds 50-90 seconds

In view of these examples and other teachings described herein, one skilled in the art can select process parameters suitable for their use. For example, as is known in the art, different etchants are required for different types of film (or laminated film) used as the first film layer 21. Control of the gas flow rate can alter the amount and etch rate of polymer formation. Even for films such as those etched in Examples 1-3, process control takes into account different film thicknesses, different shapes and thicknesses of resists, presence, shape, and thickness of BARC layers, different etch ratios, and different etch reactors. It may be necessary.

The invention is not limited to the examples provided above.

The method of the present invention can prevent or eliminate CD microloading, which adversely affects both manufacturing yield and circuit performance, and the size of the film layer etched in the film layer as a result of corrosion of the mask upon etching the film layer is dependent on the mask characteristics. Etch bias that differs in size can be eliminated or minimized.

Claims (5)

A method of etching a plurality of identical integrated circuit dies on a wafer, Providing a wafer having a first film layer to be etched; Applying a layer of resist material on the first film layer; Exposing and developing the resist material to form a patterned resist mask on the first film layer having a repeating pattern of resist features that equally mask each integrated circuit die of the wafer, wherein the respective integrated circuit die is formed. And wherein the resist feature masking comprises a first resist feature having a predetermined width and a second resist feature having a predetermined width, wherein the width of the first resist feature is narrower than the width of the second resist feature. A resist mask forming step; Plasma etching the first film layer to form a first etched film layer feature masked by the first resist feature and a second etched film layer feature masked by the second resist feature; Forming the first and second etched film layer features, wherein each of the first and second etched film layer features has a predetermined width; Plasma polymer is formed on the resist mask and the first film layer such that the width of the first film layer features the second film layer feature rather than the width of the first resist feature approaches the width of the second resist feature. Step closer to the width of The method comprising a. The method of claim 1 wherein the width of the first etched film layer feature is the same as the width of the second etched film layer feature. 2. The method of claim 1, wherein the resist mask comprises a plurality of first resist features for each integrated circuit die, wherein the first resist features are spaced apart from each other at intervals of less than approximately 0.5 micrometers. A method of etching a plurality of identical integrated circuit dies on a wafer, Providing a wafer having a first film layer to be etched; Applying a layer of resist material on the first film layer; Exposing and developing the resist material to form a patterned resist mask on the first film layer having a repeating pattern of resist characteristics that masks each integrated circuit die of the wafer, thereby masking each integrated circuit die. Wherein the resist feature comprises a first resist feature having a predetermined width and a second resist feature having a predetermined width, wherein the first and second resist features have sidewalls, and the width of the first resist feature is the second resist feature. Forming the patterned resist mask, wherein the patterned resist mask is narrower than the width of the feature; Plasma etching the first film layer to form a first etched film layer feature masked by the first resist feature and a second etched film layer masked by the second resist feature, wherein Forming said first and second etched film layer features having sidewalls; Forming a selected amount of plasma polymer on sidewalls of the first and second resist features and on sidewalls of the first and second etched film layer features, wherein the first film layer sidewalls and the first film are formed. Wherein said selected amount of plasma polymer formed on said resist feature sidewall is greater than said selected amount of plasma polymer formed on said second film layer sidewall and said second resist feature sidewall. The method comprising a. 5. The method of claim 4, wherein the first and second etched film layer features have a width, wherein the width of the first resist feature is not closer to the width of the second resist feature. Said width being closer to the width of said second film layer feature.