JP2001156299A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can be manufactured without hindrance through a wafer process in which even an inexpensive FZ wafer is used and where a part of a high impurity-concentration layer as the outermost surface layer of the rear of the wafer has a distribution of impurity concentration of steep gradient at a point adjacent to its boundary with a low impurity concentration drift layer so as to meet requirements such as reduction in cost and enhancement in performance. SOLUTION: A vertical diode is manufactured by the use of an FZ wafer of N-type low impurity concentration. An element active region (P+ anode layer 4) and an anode electrode 8 are formed on the surface of the FZ wafer where an N- drift layer 3 is formed, the rear of the FZ wafer is scraped down as thick as prescribed, and the FZ wafer is irradiated with protons from behind and then subjected to annealing to form an N-type defect layer which functions substantially as a high-impurity concentration layer (N+ cathode layer 1b). An annealing temperature (e.g. 300 to 500<=) for activating the N-type defect layer is set at a lower temperature than the melting point (700<=) of the anode electrode 8 of aluminum.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device such as a diode or a MOSFET (field effect insulated gate transistor) used in a power converter or the like.
In particular, the present invention relates to a semiconductor device suitable for adopting an FZ (floating zone) wafer and a method of manufacturing the same.

[0002]

BACKGROUND ART epi-type diode shown in FIG. 4, n on the high concentration n-type silicon substrate forming the n ⁺ cathode layer 1 ^-
It is manufactured using an epiwafer formed by growing a low-concentration n-type epitaxial layer functioning as the drift layer 3.
In the n ⁻ drift layer 3, a drift current flows in the on state, and a depletion layer is formed from the pn junction with the p ⁺ anode layer 4 to n ^{+ in the} blocking mode (off state).
It is extended to the cathode layer 1 to help ensure a withstand voltage. The n ⁺ cathode layer 1 has a function of preventing a depletion layer from reaching the cathode electrode 9 in the blocking mode and a function of obtaining a good ohmic contact with the cathode electrode 9. An epi-type diode using this epi-wafer has a high-concentration n-type silicon substrate and an n-type epitaxially grown n-type silicon substrate.
^- because it has a drift layer 3, as shown in the vertical direction dependency graph of the doping concentrations appended in FIG. 4, n ⁺
Since the impurity concentration has a steep gradient on the boundary side of the cathode layer 1 with the n ⁻ drift layer 3, a trade-off between the forward voltage and the breakdown voltage is good. However, since the epi-wafer is expensive, the epi-type diode has a disadvantage that the manufacturing cost is high.

On the other hand, the DW type diode shown in FIG.
^- it is prepared using DW wafer comprising from the back surface of the lightly doped n-type silicon substrate which serves as a drift layer 3 (FZ wafer) by diffusing a high concentration of phosphorus to form the n ⁺ cathode layer 1a. This DW wafer is inexpensive because an epitaxial growth step is not required as compared with an epi wafer,
Although it is possible to reduce the manufacturing cost of the DW diode, as shown in the graph of the vertical dependency of the doping concentration in FIG. 5, the boundary side of the n ⁺ cathode layer 1a with the n ⁻ drift layer 3 is shown. Since the impurity concentration has a gentle gradient, the trade-off between the forward voltage and the withstand voltage deteriorates.

[0004]

In recent years, diodes and M
Power semiconductor devices, such as OSFETs, are required to achieve higher characteristics but to be further reduced in cost. In order to reduce the cost, it is more advantageous to use a low-cost FZ wafer for the wafer process. In order to obtain high characteristics, the back surface side of the FZ wafer on which the surface active region such as the p ⁺ anode layer 4 and the anode electrode 8 are formed is cut to a predetermined thickness, and then the particle beam such as phosphorus or arsenic ion is cut from the back surface. Irradiate (inject)
A method of activating impurities by annealing to form an n ⁺ cathode layer is considered. Since the maximum concentration point can be set at a deep portion by the ion implantation method, the impurity concentration becomes steep at the boundary side with the n ⁻ drift layer in the n ⁺ cathode layer, so that high characteristics comparable to those of an epi-type diode can be expected.

However, in order to sufficiently activate phosphorus or arsenic atoms in a silicon wafer, it is necessary to set the annealing temperature to 1000 ° C. or higher. Therefore, a low melting point (about 700 ° C.) aluminum Anode electrode 8
The above-mentioned annealing process must be completed before depositing. However, even if the annealing process is performed before the anode electrode 8 is attached, if the thin wafer after cutting is annealed at a high temperature of 1000 ° C. or more, the wafer shape is greatly warped. Photolithography for the formation of is no longer possible. For this reason, it was impossible to use a low-cost FZ wafer for the wafer process. Such a problem is not limited to the cathode layer of the vertical diode as described above.
This is also a problem that can be said when an ohmic contact layer (high impurity concentration layer) on the uppermost surface on the rear surface is generally formed, such as a drain layer of T and a collector layer of a non-punch-through type IGBT (conductivity modulation type MOSFET).

In view of the above problems, it is an object of the present invention to provide a low-cost FZ wafer that can be manufactured without any problem even if it is used in a wafer process. It is an object of the present invention to provide a semiconductor device having a steep gradient of the impurity concentration on the boundary side with the drift layer and capable of achieving both low cost and high performance, and a method for manufacturing the same.

[0007]

In order to solve the above-mentioned problems, the present invention is characterized in that a high impurity concentration layer on the outermost side of the back surface (second main surface) can be formed by a low-temperature process.
According to a first aspect of the present invention, there is provided an element active region formed on a first main surface side of a first conductive type low impurity concentration substrate on which a first conductive type low impurity concentration drift layer is formed. In a semiconductor device including the first electrode, a high impurity concentration layer formed on the outermost side of a second main surface of the substrate, and the second electrode, the high impurity concentration layer is configured as an n-type defect layer. It is characterized by having. The n-type defect layer is a single-crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer.

A method of manufacturing a semiconductor device using the n-type defect layer on the outermost side of the second main surface as a high-concentration n-type semiconductor layer such as a contact layer is disclosed in US Pat. And forming a first electrode, shaving the second main surface side of the substrate to a predetermined thickness, irradiating the second main surface with protons, and performing an annealing process to form an n-type defect layer. . Since the annealing temperature for activating the n-type defect layer is sufficiently lower than the melting point of the first electrode layer of aluminum or the like (700 ° C. or less), the deposition of the first electrode on the first main surface side is sufficient. After the process, the n-type defect layer on the second main surface side can be formed without any trouble. Since a low-cost n-type low-impurity-concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the ion implantation method of protons is used, the range is long, the maximum concentration point can be set at a deep portion, and the impurity concentration at the boundary side with the n-type low impurity concentration drift layer in the n-type defect layer which is the high impurity concentration layer. Since the concentration becomes steep, high characteristics comparable to those of a semiconductor device using an epi-wafer can be obtained.

The temperature of the annealing treatment is preferably 300 ° C. or more and 500 ° C. or less. The irradiation energy of the proton irradiation may be 1 MeV or less.

According to a second aspect of the present invention, there is provided an element formed on a first principal surface side of a substrate having a low impurity concentration of a first conductivity type for forming a drift layer having a low impurity concentration of a first conductivity type. In a semiconductor device comprising an active region and a first electrode thereof, a high impurity concentration layer formed on the outermost side of a second main surface of the substrate, and the second electrode, the high impurity concentration layer is an oxygen donor doped layer. There is a feature. When the high impurity concentration layer is an oxygen donor doped layer, the annealing temperature can be set lower than the melting point of the first electrode such as aluminum, so that the second main surface can be formed without any trouble after the step of attaching the first electrode layer. Side high impurity concentration layer can be formed.

In this method of manufacturing a semiconductor device, an element active region and a first electrode are formed on a first main surface side of a substrate, and the second main surface side of the substrate is cut down to a predetermined thickness. The layer is formed by performing oxygen ion irradiation from the second main surface and performing an annealing process. Since a low-cost n-type low-impurity-concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. In addition, since the ion implantation method of oxygen ions is used, the range is long, the maximum concentration point can be set at a deep portion, and the impurity concentration at the boundary side with the n-type low impurity concentration drift layer of the oxygen donor doped layer which is the high impurity concentration layer. Is high, and high characteristics comparable to those of a semiconductor device using an epiwafer can be obtained. A suitable annealing temperature is 300 ° C. or more and 500 ° C. or less.

According to a third aspect of the present invention, there is provided an element formed on a first principal surface side of a first conductive type low impurity concentration substrate on which a first conductive type low impurity concentration drift layer is formed. A method of manufacturing a semiconductor device comprising: an active region and a first electrode thereof; a high impurity concentration layer formed on the outermost side of a second main surface of the substrate; and a second electrode thereof.
After forming the element active region and the first electrode layer on the main surface side and shaving the second main surface side of the substrate to a predetermined thickness, the high impurity concentration layer is removed from the second main surface by impurity ions. Is formed by irradiating the second main surface with light or laser while cooling the first main surface.

As described above, as an annealing process for forming the high impurity concentration layer on the second main surface side, the first main surface side having the first electrode is cooled (by blowing a cooling gas or a heat sink). Since the lamp annealing or laser annealing is performed on the second main surface, the annealing temperature on the second main surface side is set to a temperature (700 ° C. or higher) higher than the melting point of aluminum while securing a temperature gradient in the thickness direction of the substrate. It can be set, and it is possible to sufficiently activate even the introduced impurities having a short range. For example, phosphorus or arsenic can be used as the donor impurities. Low price, low impurity concentration F
Since a Z wafer can be used, the cost of the semiconductor device can be reduced. Also, since the ion implantation method is used, the maximum concentration point can be set at a deep portion, and the impurity concentration becomes steep at the boundary side with the drift layer in the high impurity concentration layer, so that high characteristics similar to those of a semiconductor device using an epiwafer can be obtained. Can be

The irradiation energy of phosphorus or arsenic ions is 1 M
It may be eV or less. The dose of phosphorus or arsenic is 1 × 1.
It is desirable that it is not less than 0 ¹³ cm ^{−2 and not} more than 1 × 10 ¹⁶ cm ⁻² .

Note that the present invention relates to a diode or a MOSFE.
Not only T but also n ⁻ drift layer and n on the outermost side of the second main surface
The present invention can be generally applied to a vertical semiconductor device having a high impurity concentration layer (such as an ohmic contact layer). The third aspect of the present invention is not limited to the particle beam irradiation of the donor impurity, may be a particle beam irradiation of the acceptor impurities (e.g., boron), p ^- drift layer and the lowermost front side of the p-type height of the second main surface The present invention can be generally applied to a vertical semiconductor device having an impurity concentration layer (such as an ohmic contact layer). Non-punch through type I
Like a collector layer of a GBT (conductivity modulation type MOSFET), the present invention can be applied to an ohmic contact layer (a high impurity concentration layer regardless of conductivity type) on the rearmost surface side.

[0016]

Next, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a partial sectional view showing a sectional structure of a vertical diode according to Embodiment 1 of the present invention. The vertical diode of the present embodiment is a 1200 V withstand voltage diode and is manufactured using an n-type low impurity concentration FZ wafer forming the n ⁻ drift layer 3b. On the front side of the FZ wafer, an element active region and an aluminum anode electrode 8 are formed. Here, the element active region (core portion) of the diode means a pn junction between the p ⁺ anode layer 4 and the n ⁻ drift layer 3 b. An n ⁺ cathode layer 1b is formed on the outermost surface side of the rear surface of the FZ wafer, and the n ⁺
An aluminum cathode electrode 9 is adhered on the cathode layer 1b.

As described above, in the vertical diode using the n-type low impurity concentration FZ wafer, the element active region and the anode electrode 8 are formed on the surface side of the FZ wafer,
After shaving the back surface of the wafer to a predetermined thickness, the back surface is irradiated with a particle beam of impurity ions, which will be described later, and subjected to a predetermined annealing process to form an n ⁺ cathode layer 1b. Manufactured by deposition.

[0018]

Embodiment 1 The structure of the vertical diode of Embodiment 1 is such that the n ⁺ cathode layer 1b is composed of an n-type defect layer. The n-type defect layer is a single-crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer. As described above, the method of manufacturing a diode using the n-type defect layer on the rearmost surface side as the n ⁺ cathode layer 1b includes, as described above, the element active region (p ⁺ anode layer 4) and the anode on the front side of the FZ wafer. After the electrodes 8 are formed and the back side of the FZ wafer is scraped off to a predetermined thickness, proton irradiation is performed from the back side of the FZ wafer, followed by annealing (for example, 300 ° C. to 500 ° C.).
To form an n-type defect layer. The irradiation energy of the proton irradiation may be 1 MeV or less because of its long range. The annealing temperature for activating the n-type defect layer is lower than the melting point of the aluminum anode electrode 8 (700 ° C.).
C. or less) is sufficient, so that an n-type defect layer as the n ⁺ cathode layer 1b can be formed without any trouble after the step of attaching the anode electrode 8. Of course, since a low-cost n-type low-impurity-concentration FZ wafer is used, the cost of the diode can be reduced. In addition, since the ion implantation of protons is used in the formation of the n ⁺ cathode layer 1b, the range is long, the maximum concentration point can be set at a deep portion, and the vertical dependency of the doping concentration shown in FIG. , N ⁺ cathode layer 1b
Since the impurity concentration becomes steep on the boundary side with the n ⁻ drift layer 3b in the n-type defect layer, high characteristics similar to a diode using an epiwafer can be obtained.

[0019]

Embodiment 2 The structure of a vertical diode according to Embodiment 2 is n ⁺
The cathode layer 1b is composed of an oxygen donor doped layer. n ⁺ When the cathode layer 1b and oxygen donor-doped layer, since the temperature of the annealing treatment may be to a temperature below the melting point of the aluminum of the anode electrode 8, trouble after deposition step of the anode electrode 8 without n ⁺ cathode layer 1b
Can be formed.

As described above, the method of manufacturing a diode using the oxygen donor doped layer on the rearmost surface side as the n ⁺ cathode layer 1b includes forming the element active region and the anode electrode 8 on the front surface side of the FZ wafer. After shaving the back surface of the FZ wafer to a predetermined thickness, the back surface of the FZ wafer is irradiated with oxygen ions, and an annealing process (for example, 300 ° C. to 500 ° C.) is performed to form an oxygen donor doped layer. . The irradiation energy of the oxygen ion irradiation may be 1 MeV or less because the range is long. An annealing temperature for activating the oxygen donor-doped layer at a temperature lower than the melting point of the aluminum anode electrode 8 (700 ° C. or less) is sufficient, so that n ^{+ is} not hindered after the step of attaching the anode electrode 8.
An oxygen donor doped layer can be formed as the cathode layer 1b. Further, since a low-cost n-type low-impurity-concentration FZ wafer is used, the cost of the diode can be reduced. In addition, since the ion implantation method of oxygen ions is used in the formation of the n ⁺ cathode layer 1b, the range is long, the maximum concentration point can be set at a deep portion, and the vertical dependency of the doping concentration shown in FIG. Thus, the n ⁺ cathode layer 1b, n
Since the impurity concentration becomes steep on the side of the boundary between the type defect layer and the n ⁻ drift layer 3b, high characteristics comparable to a diode using an epiwafer can be obtained.

[0021]

Embodiment 3 The vertical diode of Embodiment 3 is characterized by an annealing method in the manufacturing method. That is, the manufacturing method of this embodiment, the element active region and the anode electrode 8 is formed on the surface side of the FZ wafer, after scraping the rear surface side of the FZ wafer to a predetermined thickness, the n ⁺ cathode layer 1b, FZ The irradiation is performed by irradiating phosphor or arsenic ion particle beams from the back surface of the wafer and irradiating the back surface of the FZ wafer with light or laser while cooling the FZ wafer. The irradiation energy of phosphorus or arsenic ions may be 1 MeV or less. The dose of phosphorus or arsenic may be 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . The cooling method on the FZ wafer surface side is, for example, spraying a cooling gas or a heat sink.

Since the annealing method is short-time lamp annealing or laser annealing on the back surface while cooling the front surface of the FZ wafer, the annealing of the back surface is performed during this annealing while securing a temperature gradient in the thickness direction of the FZ wafer. The temperature can be set to a temperature higher than the melting point of aluminum (700 ° C. or higher), and even an introduced impurity with a short range can be sufficiently activated. For example, phosphorus or arsenic can be used as a donor impurity. Of course, since a low-priced low-impurity-concentration FZ wafer can be used, the cost of the diode can be reduced. In addition, since an ion implantation method, it can set the maximum density point deep, as shown in the vertical direction dependency graph of the doping concentrations appended to Figure 1, n of the n ⁺ cathode layer 1b ^- the drift layer 3b Since the impurity concentration becomes steep on the boundary side, high characteristics comparable to a diode using an epiwafer can be obtained.

FIG. 2 is a partial sectional view showing a sectional structure of a vertical MOSFET according to a second embodiment of the present invention.

The vertical MOSFET of this embodiment is a 600V breakdown voltage MOSFET, n ^- is prepared using the n-type low impurity concentration FZ wafer forming the drift layer 13b. An element active region (core) and an aluminum source electrode 18 are formed on the front side of the FZ wafer. Here, the element active region of the MOSFET is an n ⁻ drift layer 1
Well-shaped p ⁺ base region 1 formed on the surface side of 3b
4 and n formed on the surface side of the p ⁺ base region 14.
^{A +} source region 15, a gate electrode 17 made of polysilicon or the like formed via a gate oxide film 16, a source electrode 18 formed via an interlayer insulating film, and the like. An n ⁺ drain layer 11b is formed on the outermost surface of the back surface of the FZ wafer, and an aluminum drain electrode 19 is deposited on the n ⁺ drain layer 11b.

As described above, in the vertical MOSFET using the n-type low impurity concentration FZ wafer, the element active region and the source electrode 18 are formed on the front side of the FZ wafer,
After the rear surface of the Z wafer is shaved to a predetermined thickness, the back surface is irradiated with particle ions of impurity ions, which will be described later, and subjected to a predetermined annealing treatment to form an n ⁺ drain layer 11b. And manufactured.

[0026]

Embodiment 4 The structure of a vertical MOSFET according to Embodiment 4 is n
⁺ Drain layer 11b is formed of an n-type defect layer. The n-type defect layer is a single-crystal lattice defect layer, but substantially functions as a high-concentration n-type semiconductor layer. As described above, the method of manufacturing a MOSFET using the n-type defect layer on the rearmost surface side as the n ⁺ drain layer 1b is as follows.
The element active region and the source electrode 18 are formed on the front side of the FZ wafer, and the back side of the FZ wafer is scraped off to a predetermined thickness. Then, proton irradiation is performed from the back side of the FZ wafer, followed by annealing (for example, 300 ° C. (500 ° C.) to form an n-type defect layer. The irradiation energy of the proton irradiation may be 1 MeV or less because of its long range. Since the annealing temperature for activating the n-type defect layer is sufficiently lower than the melting point of the aluminum source electrode 18 (700 ° C. or less), the n ⁺ drain layer is not hindered after the step of depositing the source electrode 18. An n-type defect layer as 11b can be formed. Of course, since a low-cost n-type low-impurity-concentration FZ wafer is used, the cost of the MOSFET can be reduced. Moreover, since the ion implantation of protons is used in the formation of the n ⁺ drain layer 1b, the range is long, the maximum concentration point can be set at a deep portion, and the vertical dependence of the doping concentration shown in FIG. The n ⁺ drain layer 11b, n
Since the impurity concentration becomes steep on the boundary side with the n ⁻ drift layer 13b in the type defect layer, the MOSF using the epiwafer is used.
High characteristics comparable to ET can be obtained.

[0027]

Embodiment 5 The structure of a vertical MOSFET according to Embodiment 5 is n
⁺ Drain layer 11b is composed of an oxygen donor doped layer. When the n ⁺ drain layer 11b is an oxygen donor-doped layer, the annealing temperature can be lower than the melting point of the aluminum source electrode 18, so that the n ⁺ drain layer 1 does not interfere after the source electrode 18 is deposited.
b can be formed.

MOSFET using such oxygen donor doped layer on the rearmost surface side as n ⁺ drain layer 11b
As described above, the manufacturing method of the present invention is to form the element active region and the source electrode 18 on the front side of the FZ wafer, scrape the back side of the FZ wafer to a predetermined thickness, and then form the oxygen ions from the back side of the FZ wafer. And an annealing treatment (for example, 300 ° C. to 500 ° C.) is performed to form an oxygen donor doped layer. The irradiation energy of the oxygen ion irradiation may be 1 MeV or less because the range is long. Annealing temperature for the activation of the oxygen donor-doped layer also because at a temperature lower than the melting point of the aluminum of the source electrode 18 (700 ° C. or less) is sufficient, trouble after deposition step of the source electrode 18 without the n ⁺ drain layer 11b As an oxygen donor doped layer. Further, since a low-cost n-type low-impurity-concentration FZ wafer is used, the cost of the MOSFET can be reduced. In addition, since the ion implantation method of oxygen ions is used for forming the n ⁺ drain layer 11b, the range is long, the maximum concentration point can be set at a deep portion, and the vertical dependency of the doping concentration shown in FIG. As described above, since the impurity concentration becomes steep on the boundary side with the n ⁻ drift layer 13b in the n-type defect layer serving as the n ⁺ drain layer 11b, high characteristics similar to those of a MOSFET using an epiwafer can be obtained.

[0029]

Sixth Embodiment A vertical MOSFET according to a sixth embodiment is characterized by an annealing method in a manufacturing method. That is, the manufacturing method of the present example uses the FZ
The device active region and the source electrode 18 are formed on the front side of the wafer.
Is formed and the back side of the FZ wafer is scraped off to a predetermined thickness, and then the n ⁺ drain layer 11b is irradiated with phosphorous or arsenic ion particle beams from the back side of the FZ wafer to cool the FZ wafer while cooling the FZ wafer. Is irradiated with light or laser. The irradiation energy of phosphorus or arsenic ions may be 1 MeV or less. The dose of phosphorus or arsenic may be 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁶ cm ⁻² . FZ
The method of cooling the wafer surface side is, for example, spraying a cooling gas or a heat sink.

Since the annealing method is a short-time lamp anneal or laser anneal to the back surface while cooling the front surface of the FZ wafer, the annealing temperature of the back surface is increased while maintaining a temperature gradient in the thickness direction of the FZ wafer. The temperature can be set to a temperature higher than the melting point (700 ° C. or higher), and even an introduced impurity with a short range can be sufficiently activated. For example, phosphorus or arsenic can be used as a donor impurity. Of course, low cost low impurity concentration F
Since a Z wafer can be used, the cost of the MOSFET can be reduced. In addition, since an ion implantation method, it can set the maximum density point deep, as shown in the vertical direction dependency graph of the doping concentrations appended in FIG. 2, n ⁺
Since the impurity concentration becomes steep on the boundary side of the drain layer 11b and the n ⁻ drift layer 3b, M
High characteristics comparable to OSFET can be obtained.

FIG. 3 is a partial sectional view showing a sectional structure of a vertical MOSFET having a trench gate structure according to a third embodiment of the present invention.

The vertical M of the trench gate structure of the present embodiment
OSFET is also n⁻N-type low layer forming drift layer 13b
It is manufactured using an FZ wafer having an impurity concentration. Embodiment
The difference from the vertical MOSFET according to the second embodiment is that the element active region
(Core). The element active area is a trench gate
The structure, wherein n⁻Formed on the surface side of the drift layer 13b.
P⁺The base region 24 and this p⁺Of the base region 24
N formed on the surface side ⁺Source region 25 and p⁺base
Gates in trenches dug beyond the depth of region 24
Ge such as polycrystalline silicon buried through oxide film 26
Gate electrode 27 and a source formed via an interlayer insulating film.
The electrode 28 and the like. N on the outermost surface on the back side of the FZ wafer⁺
A drain layer 11b is formed, and its n⁺drain
Aluminum drain electrode 19 is deposited on layer 11b.
Have been.

The vertical MOSF having such a trench gate structure
The ET also employs the same manufacturing method as in the first or second embodiment and exhibits the same function and effect. However, since the ET has a trench gate structure in the element active region, the on-resistance is further reduced. Is possible.

[0034]

As described above, the present invention provides a second principal surface functioning as an ohmic contact layer such as a cathode layer of a vertical diode, a drain layer of a vertical MOSFET, and a collector layer of a non-punch through IGBT. The feature is that the high impurity concentration layer on the outermost side can be formed by a low-temperature process, so that the following effects are obtained.

In a semiconductor device using an n-type defect layer as a high-concentration n-type semiconductor layer, after forming an element active region and a first electrode on the first main surface side, proton irradiation is performed from the second main surface, and annealing is performed. Since the n-type defect layer can be formed by performing the treatment, the annealing temperature for activating the n-type defect layer is sufficiently lower than the melting point of the first electrode. After the attaching step, the n-type defect layer on the second main surface side can be formed without any trouble. Therefore, an inexpensive n-type low impurity concentration FZ wafer can be used for the wafer process,
Cost reduction of a semiconductor device can be realized. In addition, since the impurity concentration of the n-type defect layer, which is a high impurity concentration layer, becomes steep on the boundary side with the n-type low impurity concentration drift layer, high characteristics comparable to those of a semiconductor device using an epiwafer can be obtained.

In a semiconductor device using an oxygen donor-doped layer as a high-concentration n-type semiconductor layer, after forming an element active region and a first electrode on the first main surface side, oxygen ion irradiation is performed from the second main surface, and annealing is performed. The treatment can form an oxygen donor-doped layer. Therefore, a low-cost n-type low-impurity-concentration FZ wafer can be used, so that the cost of the semiconductor device can be reduced. Further, since the impurity concentration of the oxygen donor-doped layer becomes steep on the boundary side with the n-type low impurity concentration drift layer, high characteristics comparable to those of a semiconductor device using an epiwafer can be obtained.

After the element active region and the first electrode are formed on the first main surface side, the second main surface is irradiated with particle beams of impurity ions, and the first main surface is cooled while the light is applied to the second main surface. Alternatively, when a manufacturing method of forming a high impurity concentration layer by an annealing method of irradiating a laser is adopted, the annealing temperature on the second main surface side is set to a temperature higher than the melting point of aluminum while securing a temperature gradient in a substrate thickness direction. It is possible to sufficiently activate even the introduced impurities having a short range, and it is possible to use, for example, phosphorus or arsenic as a donor impurity and boron or the like as an acceptor impurity.
Since a low-priced low-impurity-concentration FZ wafer can be used, the cost of the semiconductor device can be reduced. Further, since the impurity concentration becomes steep on the boundary side with the drift layer in the high impurity concentration layer, high characteristics comparable to those of a semiconductor device using an epiwafer can be obtained.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view showing a cross-sectional structure of a vertical diode according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a cross-sectional structure of a vertical MOSFET according to a second embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a cross-sectional structure of a vertical MOSFET according to a third embodiment of the present invention.

FIG. 4 is a partial cross-sectional view showing a cross-sectional structure of a conventional epi-type diode.

FIG. 5 is a partial cross-sectional view showing a cross-sectional structure of a conventional DW diode.

[Explanation of symbols]

1a, 1b ... n ⁺ cathode layer 3, 3b, 13b ... n ^- drift layer 4 ... p ⁺ anode layer 8 ... anode electrode 9 ... cathode electrode 11b ... n ⁺ drain layer 14, 24 ... p ⁺ base region 15, 25 ... n ⁺ source region 16, 26 gate oxide film 17, 27 gate electrode 18, 28 source electrode 19, 29 drain electrode

Claims (11)

[Claims] An element active region formed on a first main surface side of a first conductive type low impurity concentration substrate on which a first conductive type low impurity concentration drift layer is formed, and a first electrode thereof. And a semiconductor device comprising a high impurity concentration layer formed on the outermost side of a second main surface of the substrate and a second electrode thereof, wherein the high impurity concentration layer is formed of an n-type defect layer. Characteristic semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the element active region and the first electrode are formed on the first main surface side of the substrate, and the second main surface of the substrate is formed. A method of manufacturing a semiconductor device, comprising: after shaving a surface side to a predetermined thickness, irradiating a proton from the second main surface and performing an annealing process to form the n-type defect layer. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the temperature of the annealing process is 300 ° C. or more and 500 ° C. or less. 4. The method for manufacturing a semiconductor device according to claim 2, wherein the irradiation energy of the proton irradiation is 1 MeV or less. 5. An element active region formed on a first main surface side of a first conductivity type low impurity concentration substrate on which a first conductivity type low impurity concentration drift layer is formed, and a first electrode thereof. And a first conductivity type high impurity concentration layer formed on the outermost side of a second main surface of the substrate and a second electrode thereof, wherein the first conductivity type high impurity concentration layer is an oxygen donor doped layer. A method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the element active region and the first electrode are formed on the first main surface side of the substrate, and the second main surface of the substrate is formed. A method of manufacturing a semiconductor device, comprising: after shaving a surface side to a predetermined thickness, irradiating oxygen ions from the second main surface and performing an annealing process to form the oxygen donor-doped layer. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the temperature of the annealing treatment is 300 ° C. or more and 500 ° C. or less. 8. An element active region formed on a first main surface side of a first conductive type low impurity concentration substrate on which a first conductive type low impurity concentration drift layer is formed, and a first electrode thereof. And a high impurity concentration layer formed on the outermost side of a second main surface of the substrate and a second electrode thereof, wherein the element active region is provided on the first main surface side of the substrate. And forming the first electrode, and forming the second electrode on the substrate.
After shaving the main surface to a predetermined thickness, the second main surface is irradiated with particle beams of impurity ions, and the second main surface is irradiated with light or laser while cooling the first main surface. Forming the high impurity concentration layer by using the method described above. 9. The method according to claim 8, wherein the impurity ions are phosphorus or arsenic ions. 10. The method according to claim 9, wherein the irradiation energy of the phosphorus or arsenic ion is 1 MeV or less. 11. The method according to claim 9, wherein the dose of the phosphorus or arsenic is 1 × 10 ¹³ cm ⁻² or more and 1
× 10 ¹⁶ cm ⁻² or less.