JP2001156180A - Cmos long distance wiring drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a CMOS long distance wiring drive circuit which is high speed and lower power consumption. SOLUTION: In a precharge period, an SW1 is turned off, and an SW2 is turned on, and a voltage for turning off a Tr2 is applied to the gate of the Tr2 by a B1. In a signal transmission period, the SW1 is turned on, and the SW2 is turned off, and a voltage V2 which is lower than (V1+Vth) is applied to the second gate by a first bias means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit comprising CMOS (complementary metal oxide semiconductor), and more particularly to a circuit for driving long-distance wiring in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art As the chip size of a semiconductor integrated circuit increases, the parasitic capacitance of the wiring on the integrated circuit becomes more dominant than the capacitance of the gate. A critical path that determines the operating frequency of an integrated circuit often includes long-distance wiring in a chip, and even if a local circuit is operated at a higher speed, the performance of the entire integrated circuit is not necessarily improved. Therefore, in order to increase the speed of an integrated circuit, a circuit that drives long-distance wiring at high speed is essential.

As a circuit most commonly used in a conventional long-distance wiring drive circuit, a circuit paired with a CMOS inverter is described in "VLSI System Design-Basics of Circuits and Mounting-(July 1995)". It is described on pages 184 to 185. Also, the circuit that precharges the transmission line is called "VLSI system design-basics of circuit and mounting-
(July 1995) "on page 188 to page 194.

[0004]

In a circuit using a conventional CMOS inverter pair, the signal amplitude on the transmission line becomes large, so that it takes a long time to charge and discharge the parasitic capacitance of the transmission line, and it is difficult to operate at high speed. There was a problem.
Also, in the conventional precharge type circuit, high-speed operation is possible by reducing the signal amplitude on the transmission line.However, since DC power is consumed, power consumption is increased, and signal transmission with small signal amplitude is performed. However, since a receiving circuit precharged to a high sensitivity region is used, there is a problem that the receiving circuit is susceptible to noise.

A first object of the present invention is to provide a CMOS long-distance wiring driving circuit which can operate at high speed, consumes little power, and has high noise resistance.

A second object of the present invention is to provide a CMOS long-distance wiring drive circuit having higher noise resistance.

A third object of the present invention is to provide a CMOS long-distance wiring drive circuit having a short precharge time.

[0008]

In order to achieve the first object, according to the present invention, a first drain is connected to a first connection point, and a first gate is connected via a first switch means. A first N-type MOS transistor connected to a first input terminal and having a first source connected to a first negative power supply;
A first transmission line connecting the second connection point and a connection point of
The first connection point is connected to the first connection point or the second connection point or in the middle of the first transmission line, and is connected to the voltage V1.
The first precharge means for boosting the voltage, the second drain is connected to the third connection point, the second gate is connected to the first bias means, and the second source is connected to the second connection point Connected, a second N-type MOS transistor having a threshold voltage of Vth, and a second connecting the third connection point to the first positive power supply.
, And a first inverter circuit connected between the third connection point and the first output terminal. The first switch is turned off, the second switch is turned on, and the first switch is turned on.
The second N-type MOS is connected to the second gate by the bias means.
A voltage for turning off the transistor is applied to precharge the first transmission line, turning on the first switch means,
The third switch means is turned off, and a voltage V2 lower than (V1 + Vth) is applied to the second gate by the first bias means to transmit a signal from the first input signal to the first output terminal.

Further, in order to achieve the second object, when a low level is inputted to the first input terminal, the first transmission line is precharged.

Further, in order to achieve the third object,
The first precharge means is dispersedly provided in at least two or more locations of the first transmission line.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. Note that the same reference numerals indicate the same components. Hereinafter, Equation 1 is described as “A bar”, which means an inverted signal of the signal A.

[0012]

(Equation 1)

FIG. 1 is a circuit diagram of a CMOS long-distance wiring drive circuit according to a first embodiment of the present invention. CMOS
SW1, which is a transfer gate, and a transistor Tr
1 and a transistor Tr4 constitute a transmission circuit. .PHI.P indicates a precharge signal, and .PHI.P indicates an inverted signal of the precharge signal. This precharge signal Φ
P is at a high level during a period during which the transmission line LINE1 is precharged, and at a low level during other periods. Φ
If P is high and ΦP bar is low, SW1 is off, Tr
4 is on and Tr1 is off. When ΦP is low and ΦP bar is high, SW1 is on, Tr4 is off and T
r1 turns on and off according to the input signal level of the input terminal IN1.

The transistor Tr5 has a precharge circuit P
Construct C1. When ΦP is high, Tr5 is turned on, and LINE1 is precharged with voltage V1.

A bias circuit B1 and a transistor Tr2
And a switch SW2 to form a receiving circuit. B1
Is composed of a CMOS inverter INV2, and when ΦP is high, the gate of Tr2 is biased to a negative power supply VSS1,
When ΦP is low, the gate of Tr2 is biased to voltage V2. The transistor Tr3 forms the switch SW2. When ΦP bar is low, Tr3 turns on and CMO
The voltage VDD1 is applied to the input terminal of the S inverter INV1.

The operation of the embodiment will be described. In the circuit of FIG. 1, in order to transmit a signal from IN1 to the output terminal OUT1, LINE1 is always precharged at the beginning of a signal transmission cycle. When ΦP is high and ΦP bar is low, SW1 and Tr1 are turned off and Tr5 is turned on, so that LINE1 is precharged to V1. Also Tr
2 is biased to VSS1 so that Tr2 is turned off, while Tr3 is turned on and the connection point N3 is at VD
D1 is applied and the output of INV1 goes low. The above is the precharge operation of the present embodiment.

Next, the operation when transmitting a signal from IN1 to OUT1 will be described. Let φP be low and φP bar be high.

When the input to IN1 is low, on the transmitting side, a low level is transmitted to the gate of Tr1 via SW1, so that Tr1 remains off. On the receiving side, Tr3 is turned off, and V2 is applied to the gate of Tr2. If the threshold voltage of Tr2 is set to Vth and the voltage relationship is set so that Equation 2 holds, Tr2 remains off, and the electric charge charged to the input terminal of INV1 during the precharge time is not discharged. OUT1 is fixed at a low level.

[0019]

V2 <(V1 + Vth) When the input level to IN1 is high, the transmission side has Tr
1 turns on, and starts to extract the electric charge charged in LINE1. The voltage of LINE1 is VL1.

When the charge of LINE1 is extracted until Expression 3 holds, Tr2 is turned on.

[0021]

VL1 <(V2−Vth) INV1 via Tr2, LINE1 and Tr1
Pull out the charge stored in the input terminal of When V1 = V2, Tr2 can be turned on only by causing VL1 to change more than Vth. That is, when Vth is sufficiently smaller than V1 and V2, it is not necessary to almost completely discharge the electric charge charged on LINE1, and INV
1 by simply extracting the charge charged to the input terminal of
V1 can be inverted.

In signal transmission by a conventional inverter pair,
The receiving inverter cannot be inverted unless at least half of the charge charged to the positive power supply voltage on the transmission line is discharged. Therefore, in the present embodiment, high-level transmission can be performed at higher speed as compared with signal transmission using a conventional inverter pair.

In this embodiment, LINE1 is recharged (V) only when there is a change in the level of the input signal.
1 is precharged to 1), so that power consumed every cycle is small. Further, V1 and V2 are changed to the power supply voltage VDD1.
By setting the voltage to a lower voltage (for example, 1/2 or less of VDD1), the power and time required for precharging LINE1 can be reduced. According to the present embodiment, although the signal amplitude on the transmission line is small, INV
No. 1 is characterized by high noise resistance because it is driven with a large amplitude.

FIG. 4 shows operation waveforms of the present embodiment. In FIG. 4, 401 is an input waveform to IN1, and 402 is O
It is an output waveform from UT1. V1 is の of VDD1
, And this waveform is the result of transmitting a 10 mm long wire within the chip. 403 is a signal transmission waveform by the conventional inverter pair. This embodiment is about twice as fast as signal transmission by a conventional inverter pair.

FIG. 2 shows a second embodiment of the present invention.
In this embodiment, a CMOS according to the first embodiment is used.
A NAND gate NAND1 is added. NAND1
, The input signal to ΦP bar and IN1 is input. N
By AND1, PC1 sets ΦP low or IN1.
LINE1 is precharged when the input signal to is low.

In the first embodiment, when the input signal is low, both Tr1 and Tr2 are turned off.
INE1 is in a floating state. If VL1 changes due to electric charge leakage or noise on LINE1, Tr2 is turned on and INV1 may malfunction. Therefore, in the present embodiment, when the input signal is at a low level, LINE1 is always precharged by PC1, so that VL1 can be kept constant and noise resistance can be improved.

FIG. 3 shows a third embodiment of the present invention.
In the present embodiment, a precharge circuit PC2 is added to the first embodiment. PC2 is composed of a transistor Tr6, and when ΦP is high, L
Precharge INE1.

According to the present embodiment, PC1 and PC2 can be simultaneously charged with LINE1 in two circuits.
Can be increased, and the precharge time of LINE1 can be shortened. By providing a plurality of precharge means on the LINE 1, the precharge time can be reduced, and the signal transmission cycle can be shortened.

[0029]

As described above, according to the first embodiment of the present invention, the signal amplitude on the transmission line can be reduced and the operation speed of the CMOS long-distance wiring is twice as fast as that of the conventional circuit. Circuit can be provided. Also, since the parasitic capacitance of the transmission line is charged and discharged only when the input signal level switches,
A low power consumption CMOS long-distance wiring drive circuit can be provided. Further, according to the second embodiment, the transmission line does not enter a floating state, so that the noise resistance can be improved. Further, according to the third embodiment, 2
Since a current for charging the transmission line can be supplied from more than one location, the precharge time can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram according to a third embodiment of the present invention.

FIG. 4 is a measurement diagram showing a circuit operation according to the first embodiment of the present invention.

[Explanation of symbols]

Tr1, Tr2, Tr3, Tr4, Tr5, Tr6 ... M
OS transistor, INV1, INV2 ... CMOS inverter, NAND1 ... CMOS NAND gate, LI
NE1: transmission line, N1, N2, N3, N4 ... connection point,
SW1, SW2 ... switch, IN1, OUT1 ... terminal,
ΦP: Precharge signal, VDD1, VSS1, V1,
V2: Power supply, PC1, PC2: Precharge circuit, B1
... Bias circuits, 401, 402, 403.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 19/0175 F term (Reference) 5F038 CD05 CD13 DF01 DF08 EZ20 5F048 AA00 AB04 AB10 AC03 5J056 AA05 BB06 BB14 BB17 BB32 CC19 DD13 DD28 DD29 EE11 FF08 KK01

Claims (3)

[Claims] A first drain connected to a first connection point;
A first N-type MOS transistor having a first gate connected to a first input terminal via first switch means, a first source connected to a first negative power supply, and a first connection point A first transmission line connecting the first transmission line and the second connection point, and a first transmission line connected to the first connection point or the second connection point or the middle of the first transmission line, and boosting the first transmission line to a voltage V1. The first precharge means and the second drain are connected to a third connection point, the second gate is connected to the first bias means, and the second source is connected to the second connection point. A second N-type MOS transistor having a threshold voltage of Vth, a second switch for connecting the third connection point to the first positive power supply, and a second switch for connecting the third connection point to the first output terminal. The first connected between
The first switch means is turned off, the second switch means is turned on, and a voltage for turning off the second N-type MOS transistor is applied to the second gate by the first bias means. Precharging the first transmission line, turning on the first switch means, turning off the third switch means, and applying a voltage V2 lower than (V1 + Vth) to the second gate by the first bias means. And transmitting a signal from a first input signal to a first output terminal. 2. The CMOS long-distance wiring drive circuit according to claim 1, wherein when a low level is input to the first input terminal, the first transmission line is precharged. 3. The CMOS long-distance wiring drive circuit according to claim 1, wherein the first precharge means is dispersedly provided in at least two or more locations of the first transmission line.