JP2001155047A - Device and method for processing logic simulation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate a logic simulation by preventing the occurrence of an unwanted event inside a logic block corresponding to a logic block in a wait state concerning an event-driven simulator. SOLUTION: Concerning the event-driven type logic simulator, the logic block in the wait state of stabilizing an internal state unless an entry from the outside is changed is detected and concerning the logic block in the wait state, the supply of a clock entry from the outside is stopped. Among the logic blocks in the clock entry stop state, a logic block to transit from the wait state to the other state is detected. Concerning the detected logic block to transit from the wait state to the other state, the supply of the clock entry from the outside is restarted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a logic simulation processing apparatus and method for speeding up processing in a logic simulator.

[0002]

2. Description of the Related Art Functional verification at the design stage of an LSI or the like is mainly performed by simulation on a computer using a circuit description using a hardware description language and test vectors. The time required for such a simulation has exponentially increased due to the recent enlargement of the circuit scale, and it has become indispensable to shorten the time by increasing the speed of the simulation processing. In particular, in a simulation for verifying the function of one chip, it is expected that processing time of several weeks to a month will be required to handle a circuit of several million gates. It has become to.

Conventionally, an event-driven simulator has been used as one of logic simulators for verifying the timing and function of a logic circuit. The event-driven simulator performs additional processing for tracing an event, but when simulating a circuit operation in which a signal value changes only in a part of the circuit, the operation of a part of the circuit selected by the event is performed. Since only the calculation is performed, the simulation can be performed efficiently.

More specifically, an event whose logical value changes in response to an externally applied input signal is registered in a time management table called a time wheel for each simulation time, and event processing based on the registered event is performed. Is executed at each time. As a result of performing such event processing, if the logical value changes, if a delay value is specified, it is registered as a new event on the time wheel after the specified time has elapsed. Is removed from the time wheel. The same process is performed for the events registered at each time, and the simulation ends when all the event processes have been completed.

[0005]

However, in the event-driven simulator described above, for example, the logic in which the input signal does not change and the output signal is in a waiting state in which the output signal holds a certain value. Unnecessary event processing that does not affect the output signal also exists inside the block. As a specific example, as a simulation of the entire system of a semiconductor integrated circuit, a case in which cooperative simulation is used that divides the processing of the system into a software simulator and a logic simulator, and enables simultaneous simulation of the entire system by operating these at the same time. In the case where the logic simulator waits for the processing result of the software simulator, unnecessary events such as monitoring whether or not the processing of the software simulator is completed on the logic simulator side occur. There is a possibility that a problem that the simulation speed of the entire system is reduced may occur.

[0006] The present invention provides an efficient logic simulation processing apparatus and method capable of reducing the number of events by preventing the occurrence of unnecessary events during execution of the logic simulation in order to solve the above-mentioned problems. The purpose is to do.

[0007]

In order to achieve the above object, a logic simulation processing apparatus according to the present invention provides a logic simulation processing apparatus in an event-driven logic simulation.
At a predetermined time, a wait state detection unit that detects a logical block in a wait state in which the internal state is stable unless there is a change in an external input, and a logical block in a wait state, A clock input stop unit for stopping the supply of clock input, and a return block detecting unit for detecting a logical block that transitions from a wait state to another state among the logical blocks that have been stopped by the clock input stop unit. And a clock input resuming unit for resuming the supply of an external clock input to the logical block detected by the return block detecting unit.

With this configuration, the supply of the clock input from the outside to the logic block in the waiting state during the execution of the logic simulation is stopped, and the logic block in the clock input stopped state is returned to the execution state or the like. Unnecessary events that occur in the waiting logical block can be eliminated by restarting the supply of the clock input from the outside to the logical block that performs the logic simulation. Can be reduced, so that the speed of the logic simulation can be increased.

Further, in the logic simulation processing device according to the present invention, the waiting state detecting section may detect the waiting logical block based on an external signal for changing the state of the logical block to the waiting state. preferable. This is because the state of the logical block is changed to the wait state by an external signal that makes a transition to the wait state.

Further, in the logic simulation processing apparatus according to the present invention, it is preferable that the waiting state detecting section detects the logical block in the waiting state based on the processing end signal output from the logical block. This is because a standby state is often set when the processing is completed.

Further, in the logic simulation processing device according to the present invention, it is preferable that the return block detecting section detects the return block based on an external signal for changing the state of the logical block from the waiting state to another state. This is because the logical block is released from the wait state by an external signal that causes a transition from the wait state to another state.

Further, in the logic simulation processing device according to the present invention, it is preferable that the return block detection unit detects the return block based on an external signal input to the logic block in the clock input stopped state. This is because, as an external signal input to the logic block in which the clock input is stopped, there can be no other external signal than the external signal for shifting from the waiting state to another state.

Next, in order to achieve the above object, a logic simulation processing apparatus according to the present invention divides the operation of a system to be simulated into operation modes in an event-driven logic simulation, and Register in the data base the waiting logical block whose internal state is stable and the external signal to be returned from the waiting state as long as there is no change in external input, and wait by referring to the database. A wait state detection unit that detects a logic block that is in a state, a clock input stop unit that stops the supply of an external clock input to a logic block that is in a wait state, and a clock input stop unit that outputs a clock. Of the logical blocks in the input stopped state, refer to the database. A return block unit that detects a logical block that transitions from the wait state to another state, and a clock input restart unit that restarts external clock input supply to the logical block detected by the return block detector. It is characterized by including.

With this configuration, by registering in advance a logical block in a waiting state in each operation mode of executing a logic simulation in a database, a logical block in a waiting state can be easily detected. By stopping the supply of external clock input to the logic block, unnecessary events that occur in the waiting logic block can be eliminated, reducing the number of events in the entire logic simulation Therefore, the speed of the logic simulation can be increased.

Next, in order to achieve the above object, according to the logic simulation processing method of the present invention, in an event-driven logic simulation, the internal state is stabilized at a predetermined time unless there is a change in an external input. Detecting the logical block in the waiting state; and
Stopping the supply of the clock input from the outside, detecting the logic block that transitions from the waiting state to another state among the logic blocks in the clock input stopped state, And restarting the supply of the clock input from the outside to the logic block that transitions to the state of (1).

With this configuration, the supply of the clock input from the outside to the logic block in the waiting state during the execution of the logic simulation is stopped, and the logic block in the clock input stopped state is returned to the execution state or the like. Unnecessary events that occur in the waiting logical block can be eliminated by restarting the supply of the clock input from the outside to the logical block that performs the logic simulation. Can be reduced, so that the speed of the logic simulation can be increased.

Further, in the logic simulation processing method according to the present invention, in the step of detecting a logical block in a wait state, the logic state is changed to a wait state based on an external signal for changing the state of the logical block to the wait state. It is preferable to detect the existing logical block. This is because the state of the logical block is changed to the wait state by an external signal that makes a transition to the wait state.

In the logic simulation processing method according to the present invention, in the step of detecting a logical block in a waiting state, the logic block in a waiting state is output based on a processing end signal output from the logical block. Is preferably detected. This is because a standby state is often set when the processing is completed.

Further, in the logic simulation processing method according to the present invention, in the step of detecting a logical block that transitions from a waiting state to another state, an external signal for transitioning the state of the logical block from the waiting state to another state is output. It is preferable to detect the return block based on this. This is because the logical block is released from the wait state by an external signal that causes a transition from the wait state to another state.

Further, in the logic simulation processing method according to the present invention, in the step of detecting a logic block which transitions from a waiting state to another state, the logic simulation processing method may include the steps of: Preferably, a return block is detected. This is because, as an external signal input to the logic block in which the clock input is stopped, there can be no other external signal than the external signal for shifting from the waiting state to another state.

Next, in order to achieve the above object, a logic simulation processing method according to the present invention divides the operation of a system to be simulated into operation modes in an event-driven logic simulation, and Register in the data base the waiting logical block whose internal state is stable and the external signal to be returned from the waiting state as long as there is no change in external input, and wait by referring to the database. Detecting a logic block in a state, stopping supply of an external clock input to a logic block in a waiting state, and a logic block in a clock input stopped state. data·
Detecting a logical block that transitions from the wait state to another state by referring to the base; and, for the logical block that transitions from the detected wait state to another state,
Restarting the supply of the clock input from the outside.

With this configuration, by registering in advance the logical blocks in the waiting state in each operation mode of executing the logic simulation in the database, the logical blocks in the waiting state can be easily detected. By stopping the supply of external clock input to the logic block, unnecessary events that occur in the waiting logic block can be eliminated, reducing the number of events in the entire logic simulation Therefore, the speed of the logic simulation can be increased.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) Hereinafter, a logic simulation processing apparatus according to Embodiment 1 of the present invention will be described with reference to the drawings. FIG. 1 is a configuration diagram of a clock input control unit in the logic simulation processing device according to the first embodiment of the present invention. The clock input control unit exists as a resident process that operates constantly during execution of the logic simulation.

In FIG. 1, reference numeral 11 denotes a waiting state detecting unit for detecting a logical block in a waiting state, and reference numeral 12 stops supply of an external clock input to the logical block in a waiting state. Clock input stop section
Shown respectively.

Reference numeral 13 denotes a return block detecting unit for detecting a logical block that returns to the execution state among the logical blocks in the clock input stopped state, and 14 resumes the supply of the clock input to the return block. Each of the clock input resuming units is shown.

When performing a logic simulation, the processing order of events and the like are determined first, and events are sequentially processed in accordance with the processing order.
By constantly monitoring the state of the logic block during such processing, a logic block that does not require a clock input is extracted, and a clock input is provided only when needed.

That is, in the clock input control unit,
The wait state detection unit 11 detects a logical block in a wait state, and the clock input stop unit 12 stops supply of an external clock input to the logical block detected as the wait state.

On the other hand, the return block detecting unit 13 detects a logical block that returns to the execution state or the like from among the logical blocks in the clock input stopped state, and determines that the logical block is the return block by the clock input resuming unit 14. The supply of the clock input to the detected logic block is restarted.

The flow of such processing will be described with reference to the drawings. FIG. 2 shows a flow chart of the processing of the clock input control device in the logic simulation processing device according to the present invention. In FIG. 2, first, it is determined whether or not there is an event to be processed (step S201), and if all event processes have been completed (step S20)
1: No) The simulation itself is ended.

If there is an event process that has not been completed (step S201: Yes), it is checked whether there is a logical block in the waiting state or a logical block that has transitioned to the waiting state (step S202). If there is a logical block in the waiting state or a logical block that has transitioned to the waiting state (step S202: Ye)
s) The supply of the clock input to the waiting logical block is stopped (step S203).

Next, it is confirmed whether or not there is a logical block that has returned from the wait state to the execution state (step S204).
If there is a logical block that has returned from the wait state to the execution state or the like (step S204: Yes), the supply of the clock input to the logical block that has returned from the wait state to the execution state or the like is restarted (step S205). ).
Then, event processing is performed only on the logical block in the execution state (step S206).

By performing such processing, a clock input is not supplied to a logic block in a waiting state, so that it is possible to prevent occurrence of processing unnecessary for processing of the entire logic circuit. As a result, the simulation time of the entire system can be reduced.

Next, FIG. 3 is an exemplary diagram showing a state transition of a certain logical block. In FIG. 3, the state of the logical block includes a wait state 301, an execution state 302, and a reset state 303. Further, the state of the logic block is changed from the execution state 302 to the waiting state 301 by the external input signal A, the state of the logic block is changed from the waiting state 301 to the execution state 302 by the external input signal B, and the state of the logic block is changed by the external input signal C. It is assumed that the state transits from the waiting state 301 to the reset state 303.

Here, the wait state 301 means that, for example, if there is no change in the input signal from outside the logic block, the output signal keeps the value of the previous time, and the count inside the logic block by a timer irrelevant to the output signal. This means a state in which a process such as an operation is being executed. In other words, it means the state of the logic block that is executing unnecessary processing as the processing of the entire logic circuit.

In FIG. 3, the logic block in the execution state 302 is set to the waiting state 30 by the external input signal A.
In the case of transition to 1, since the internal state of the logical block that has transitioned to the wait state 301 is stable, an event occurring inside the logical block is unnecessary in the logic simulation. In the first embodiment of the present invention, the waiting state detecting unit 1
1 is a wait state 30 for the state of the logical block in FIG.
The logic block is determined to be in the waiting state 301 by detecting the external input signal A to be changed to 1. When the external input signal A is detected,
The clock input stopping unit 102 stops the supply of the clock input from the outside to the logical block in the waiting state 301.

Further, the return block detecting section 13 detects an external input signal B or an external input signal C for making a transition from the waiting state 301 to another state with respect to the logical block in the waiting state 301. It is characterized that the logic block is determined to be in the execution state 302 or the reset state 303, and when the external input signal B or the external input signal C is detected, the execution state 302 or the reset state 303 is set. The clock input restarting unit 104 restarts the supply of the clock input to the logic block.

Here, transitions between a plurality of states in the logic block, which do not particularly affect the output signal, are also treated as the wait state 301, and the supply of the clock input is stopped.

The state transition is not specified in the form shown in FIG.
It suffices if the configuration is made up of an external input signal A for changing the state of the logic block to the waiting state 301, an external input signal B or an external input signal C for changing from the waiting state to another state.

As described above, according to the first embodiment, the supply of the clock input to the logic block in the waiting state is stopped, thereby preventing the occurrence of an unnecessary event during the event-driven simulation. Therefore, the number of events can be reduced, and the speed of the logic simulation can be increased.

Embodiment 2 Hereinafter, a logic simulation processing apparatus according to Embodiment 2 of the present invention will be described.
This will be described with reference to the drawings. The logic simulation processing apparatus according to the second embodiment of the present invention basically controls the stop / supply of the clock input by the clock input control unit similarly to the first embodiment. The standards are different.

FIG. 4 is a block diagram of a clock input control unit in a logic simulation processor for a logic circuit described at a higher level. In FIG.
Is a database reference unit that refers to whether or not the operation mode in which the processing is performed is registered in the database 406; and 402 is a state in which a logical block that matches the operation mode registered in the database 406 is set in a waiting state. The waiting state detection unit that determines the logical block is
Denotes a clock input stop unit for stopping the supply of a clock input from the outside to the logic block in a waiting state.

Also, 404 detects a return signal for returning from the wait state registered in the data base 406 among the logical blocks in the clock input stopped state, so that the logical block is changed from the wait state to another state. And a clock input resuming unit 505 for resuming the supply of the clock input from the outside to the return block.

Here, an example of the configuration of the database 406 is shown in FIG. FIG. 5 shows a case where the operation during the logic simulation in the logic simulation processing apparatus according to the second embodiment of the present invention is divided for each operation mode.
In each operation mode 501, a logical block 502 in a waiting state and an external signal 503 for returning from the waiting state to an execution state are registered.

That is, in a logic circuit or the like described at a higher level, before starting a logic simulation,
The information about the operation mode, the logical block in the waiting state in the operation mode, and the external signal for returning from the waiting state to the execution state and the like are known, and as shown in FIG. It is possible to register in. For example, when the operation mode of the logic circuit to be simulated is set up, not all the logic blocks need to be in the execution state, and only a limited number of logic blocks need to be in the execution state, and the waiting state Can be registered in advance.

Next, the flow of processing in the logic simulation processing apparatus according to the second embodiment will be specifically described with reference to FIGS. FIG. 6 is a flowchart of a process in the logic simulation processing device according to the second embodiment of the present invention.

First, regarding the operation mode during the logic simulation, information on the operation mode 501 whose waiting state is known in advance, the logic block 502 in the waiting state at that time, and the external signal 503 to be returned from the waiting state is stored in the data / data. It is registered in the base 406.

Next, in FIG. 6, it is determined whether or not there is an event to be processed (step S601).
If all event processes have been completed (step S60
1: No) The simulation itself is ended.

If there is an uncompleted event process (step S601: Yes), it is determined whether or not the operation mode of the logic simulation to be executed is registered in the database 406 (step S602). If the operation mode is registered (step S602: Ye
s), using the operation mode as a search key in the database 4
06, a logical block registered as a waiting logical block is detected (step S60).
3) The supply of the clock input to the waiting logical block is stopped (step S604).

When the supply of the clock input to the waiting logical block is stopped or the operation mode is not registered (step S602: N
o), It is determined whether or not an external signal for transitioning from the waiting state registered in the database 406 to the execution state or the like is detected (step S605). When an external signal for transition from the waiting state to the execution state is detected (step S
605: Yes), it is determined that the logical block has returned from the waiting state to the execution state, and the supply of the clock input to the logical block is restarted (step S).
606). Then, event processing is performed only on the logical block in the execution state (step S60).
7).

As described above, according to the second embodiment, the logical blocks to be in the waiting state in each operation mode and the external signals to be returned from the waiting state are registered in the data base in advance, and the logic simulation is performed. When processing is performed in the registered operation mode, the supply of external clock input is stopped, and when an external signal for returning from the registered wait state is detected, the supply of clock input is restarted. In addition, unnecessary operation processing in the waiting logical block can be reduced, and the processing speed of the entire logic simulation can be increased.

Embodiment 3 Hereinafter, a logic simulation processing apparatus according to Embodiment 3 of the present invention will be described.
This will be described with reference to the drawings. The logic simulation processing apparatus according to the third embodiment of the present invention basically controls the stop / supply of the clock input by the clock input control unit similarly to the first embodiment. The standards are different.

FIG. 7 is a view showing an example of the configuration of a logic circuit in the logic simulation processing apparatus according to the third embodiment of the present invention. 7, reference numeral 701 denotes a processing control unit such as a CPU; 702, a logical block control unit such as a bus control unit; and 703, a logical block.

During the logic simulation, the processing of each event is executed in each logic block 703 via the logic block control unit 702. Then, the end of the processing in the logical block 703 is notified to the logical block control unit 702 by the processing end signal D,
The logical block control unit 702 controls a specific logical block 703 in a waiting state by the processing start signal E.
Then, the start of the process is notified.

More specifically, the wait state detection unit 11 determines that the logical block is in the wait state by detecting the processing end signal D from the logical block 703, and the clock input stop unit 12 determines that the logical block is in the wait state. The supply of the clock input from the outside to the logic block in the state is stopped.

Further, the return block detector 13 detects the processing start signal E for the logical block in the clock input stopped state, and the logical block transitions from the waiting state to another state. Thus, the clock input restarting unit 14 restarts the supply of the clock input to the logical block.

In the case where the processing end signal D from the logic block 703 in FIG. 7 does not exist, a state in which the input signal does not change and the output signal holds a constant value is set to a waiting state. Needless to say, a logic circuit that outputs the processing end signal D when the logic block 703 itself is in such a state can be created in the logic block 703 and supply of the clock input can be stopped.

As described above, according to the third embodiment, by detecting the processing end signal D from the logic block and the processing start signal E to the logic block in the clock input stopped state, each of the signals during the logic simulation is detected. The supply of the clock input to the logic block can be controlled, and the speed of the logic simulation can be increased.

[0058]

As described above, according to the logic simulation processing apparatus and method according to the present invention, a wait state is detected by an external signal for transiting to a wait state, and the detected wait state logic block is externally detected. Can be stopped, the number of events in the logic simulation can be reduced, and the execution speed of the logic simulation can be improved.

According to the logic simulation processing apparatus and method according to the present invention, a logic block in a waiting state, which is known in advance for an operation mode, and an external signal for making a transition from the waiting state to another state are registered in the database. Then, by detecting a logic block that is in a waiting state by referring to a database during the logic simulation, and stopping supply of an external clock input to the logic block, the execution speed of the logic simulation can be improved more. It can be easily realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a clock input control unit in a logic simulation processing device according to a first embodiment of the present invention;

FIG. 2 is a processing flowchart of a clock input control unit in the logic simulation processing device according to the first embodiment of the present invention;

FIG. 3 is an exemplary diagram of state transition in the logic simulation processing device according to the first embodiment of the present invention;

FIG. 4 is a configuration diagram of a clock input control unit in the logic simulation processing device according to the second embodiment of the present invention;

FIG. 5 is a diagram illustrating a configuration example of a database in a logic simulation processing apparatus according to a second embodiment of the present invention;

FIG. 6 is a processing flowchart of a clock input control unit in the logic simulation processing device according to the second embodiment of the present invention;

FIG. 7 is a configuration diagram of a logic circuit in the logic simulation processing device according to the third embodiment of the present invention;

[Description of Signs] 11, 402 Waiting state detecting unit 12, 403 Clock input stopping unit 13, 404 Return block detecting unit 14, 405 Clock input resuming unit 301 Waiting state 302 Running state 303 Reset state 501 Operating mode 502 Waiting for operating mode Logical block 503 to be in state External signal for returning from the waiting state for the operation mode 401 Database reference section 406 Database 701 Processing control section 702 Logical block control section 703 Logical block

Claims (12)

[Claims] In a logic simulation of an event-driven system, a waiting state detecting section for detecting, at a predetermined time, a logical block in a waiting state in which an internal state is stabilized unless an external input is changed; A clock input stop unit for stopping supply of an external clock input to a logic block in a wait state, and a logic block in a clock input stop state by the clock input stop unit. A return block detection unit that detects a logic block that transitions to another state; and a clock input restart unit that restarts external clock input supply to the logic block detected by the return block detection unit. A logic simulation processing device characterized by the above-mentioned. 2. The logic simulation processing device according to claim 1, wherein the waiting state detection unit detects the logic block in the waiting state based on an external signal for changing a state of the logical block to the waiting state. . 3. The logic simulation processing device according to claim 1, wherein the waiting state detection unit detects the waiting logical block based on a processing end signal output from the logical block. 4. The logic simulation processing device according to claim 1, wherein the return block detection unit detects a return block based on an external signal that causes the state of the logical block to transition from the wait state to another state. 5. The logic simulation processing device according to claim 1, wherein the return block detector detects a return block based on an external signal input to the logic block in a clock input stopped state. 6. In an event-driven logic simulation, an operation of a system to be simulated is divided into operation modes, and an internal state is stabilized unless an external input changes for each of the operation modes. A waiting state detecting unit for registering a logical block in a waiting state and an external signal for returning from the waiting state in a database, and detecting the logical block in the waiting state by referring to the database; A clock input stop unit for stopping supply of an external clock input to the logic block in the waiting state; and a logic block in a clock input stop state by the clock input stop unit. Theory of transition from the waiting state to another state by referring to the database A logic simulation processing apparatus comprising: a return block unit that detects a logical block; and a clock input restart unit that restarts supply of a clock input from the outside to the logical block detected by the return block detection unit. . 7. In an event-driven logic simulation, at a predetermined time, a step of detecting a logic block in a waiting state in which an internal state is stabilized unless there is a change in an external input; Stopping the supply of a clock input from the outside to the logic block that has been turned off, and detecting a logic block that transitions from the waiting state to another state among the logic blocks in the clock input stopped state. And a step of resuming the supply of an external clock input to the detected logic block that transits from the waiting state to another state. 8. The logical block in the waiting state is detected in the step of detecting the logical block in the waiting state based on an external signal for changing the state of the logical block to the waiting state. Item 7. A logic simulation processing method according to Item 7. 9. The logic block according to claim 7, wherein, in the step of detecting the logic block in the waiting state, the logic block in the waiting state is detected based on a processing end signal output from the logic block. Logic simulation processing method. 10. In the step of detecting a logical block that transitions from the waiting state to another state, a return block is detected based on an external signal that causes the state of the logical block to transition from the waiting state to another state. The logic simulation method according to claim 7. 11. The recovery block is detected based on an external signal input to a logic block in a clock input stopped state in the step of detecting a logic block that transitions from the wait state to another state. Logic simulation processing method. 12. In an event-driven logic simulation, an operation of a system to be simulated is divided into operation modes, and an internal state is stabilized as long as there is no change in an external input for each of the operation modes. Registering, in a data base, a logical block in a waiting state and an external signal to be returned from the waiting state, and detecting the logical block in the waiting state by referring to the data base; Stopping the supply of a clock input from the outside to the logic block in a waiting state; and, from the waiting state by referring to the database among the logic blocks in the clock input stopped state. Detecting a logical block transitioning to another state; and the detected wait state From relative logical block transitions to another state, logic simulation processing method which comprises a step resuming the supply of the clock input from the outside.