JP2006178663A - Information processor, method for processing information, verification apparatus, and method of verification - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for permitting the optimum host computer to execute a program requested to be executed. <P>SOLUTION: When a simulation execution accepting part 100 accepts a request to execute software, a memory usage predicting part 101 calculates the memory usage required to execute the software, and the job for executing the software is stored in a queue 120, 121, 122 corresponding to a group 130, 131, 132 to which computers each with the memory capacity allowing the calculated memory usage belong. Any of the computers belonging to the group corresponding to the queue that stores the job is given permission to use the job. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique related to management of shared software.

  Regarding logic verification of semiconductor circuits, for the purpose of effective use of a simulation tool license and a host computer, these resources are collectively managed and shared by a plurality of people. For example, one tester (logic verifier) that performs a logic verification simulation makes a resource request to a system (program) that manages these resources, and the management system sequentially requests the resources, that is, a tool license and a host. Assign a computer. When the simulation ends, the resources are released and the management system returns to the management.

  With such a system, each tester can perform a simulation without worrying about the number of tool licenses or the usage status of the host computer. If another simulation is run on a host computer that is already running simulation, the workload of the CPU is limited, and the simulation speed is slowed down. For this reason, when there are a plurality of host computers, resource management is performed so that as few simulations as possible are performed on the same host computer.

  In addition, if the tool license is not managed in a batch and assigned to each tester, the other testers will use this resource even if the resource is idle when the tester is not simulating. I can't. Furthermore, when the number of resources is less than the number of testers, resources cannot be allocated to all testers.

  Therefore, a system (program) that collectively manages resources can realize that a desired number of resources is allocated to those who want to use the resources, and resources can be used effectively.

  In addition, large-scale integrated circuits (hereinafter referred to as LSIs) continue to be highly functional and highly integrated in order to meet the ever-increasing demand for electronic device performance. Built-in central control circuit (hereinafter referred to as CPU) and peripheral circuits that are electrically connected to the CPU. Larger system LSI, and the design and development period of the logic circuit due to the increased scale and complexity of this system LSI. In particular, functional verification that confirms that this circuit operates correctly occupies a large percentage. Therefore, it is important to perform verification efficiently.

  Generally, in a logic verification test for an integrated circuit such as a system LSI, a plurality of peripheral circuits included in the integrated circuit are individually verified (hereinafter referred to as individual verification) and a plurality of peripheral circuits are operated simultaneously. The test (hereinafter referred to as “system verification”), which was performed separately, was described separately, but this was improved and the test for individual verification could be used in the system verification. A frequently performed invention is disclosed in Patent Document 2.

  In such an invention, a mechanism for simultaneously starting a plurality of individual verification tests as a system verification test, and in the system verification test, a CPU command and a memory access request described in each individual verification test collide to cause a malfunction. It describes a mechanism for preventing the occurrence of

  Further, a mechanism for diverting an individual data path verification test in system verification has been disclosed.

  Here, a general system LSI integrated circuit will be described. FIG. 6 is a block diagram showing a basic configuration of a general system LSI integrated circuit. In the figure, reference numeral 601 denotes an integrated circuit of a system LSI, and reference numeral 602 denotes a CPU that controls each unit described below and executes verification processing described later. Reference numeral 604 denotes a memory controller that has a built-in memory and controls reading / writing of data to / from the memory. Programs and data described below are held in this memory. Reference numerals 605 and 606 denote I / O devices that function as interfaces for data communication between the integrated circuit of the system LSI and the outside. Reference numeral 607 denotes a data path for performing various data processing such as image processing on data input to the memory included in the memory controller 604 via the I / O device. A bus 603 connects the above-described units.

  In the integrated circuit of the system LSI having such a configuration, first, verification processing of each data processing block when the data path 607 has a configuration in which three data processing blocks are connected in series as shown in FIG. explain. FIG. 7 is a block diagram showing a configuration of a data path 607 in which three data processing blocks are connected in series. Reference numerals 702 to 704 denote data processing blocks, which perform processing in this order.

  FIG. 8 is a diagram showing a flow of individual verification processing of the data processing block (data processing 1 block in the figure). The input data file 801 used for verification in the figure is interpreted by the input bus model 802 and sent to the data processing 1 block 806 to be verified.

  The parameter data file 803 for setting the operation mode and the like at this time is set through the CPU I / F model 805, and the data processing 1 block 806 uses the input data file 801 according to the set operation mode. Works. The operation result is output as an output data file 810 through the output bus model 807.

  On the other hand, an expected value data file 808 as correct answer data to be output by the data processing 1 block 806 is previously generated from the input data file 801 and the parameter data file 803 using the data processing 1 program 804 for generating correct answer data. When the processing of the data processing 1 block 806 to be verified is completed, the end result is compared with the expected value data file 808 to verify whether the data processing 1 block 806 has performed the expected operation.

  Further, in the verification method shown in FIG. 3, the expected value comparison is performed after the operation of the data processing 1 block 806 ends. However, as another method, a method shown in FIG. 11 is generally known.

  FIG. 11 is a diagram showing a flow of individual verification processing of a data processing block (data processing 1 block in the figure) different from the above processing.

  The method for inputting data to the data processing 1 block 1106, which is the circuit to be verified, and the parameter setting method are the same as those shown in FIG. 3, but the method for comparing expected values is different.

  In FIG. 11, the output bus model 1107 performs only a handshake operation with the data processing 1 block 1106 and does not create an output data file. If the specification of the bus connecting the data processing 1 block 1106 and the output bus model 1107 does not require handshaking, the output bus model 1107 is not necessarily required. In this verification environment, a data 1 monitor 1111 is newly provided.

  The data 1 monitor 1111 monitors the processing result data output from the data processing 1 block 1106 every clock cycle, and compares it with an expected value 1 data file 1108 created in advance on the fly. Since this verification environment compares expected values on the fly compared to the verification environment of FIG. 8, the data processing 1 block 1106 does not perform the expected operation during the processing. However, before the block finishes all processing, it can be detected as an error, and no extra simulation is required.

  In the verification of this data processing 1 block, conventionally, the test description shown in FIG. 9 is defined and executed. FIG. 9 is a diagram showing a configuration example of a test description used conventionally.

  In the figure, the sequence class for data processing 1 block is created by inheriting a common verification function (common sequence basic class) that defines a verification sequence common to all data processing blocks. In the sequence function of this sequence class, processes such as initialization, parameter setting, expected value creation, test start, process end wait, expected value comparison, etc., which are verification sequences for one block of data processing, are defined. It is also defined that the processes are executed in this order (in the figure, they are executed in the order in which they are numbered). The data processing block 1 is individually verified by using the sequence class for the data processing 1 block and the common verification function. Since such verification processing is well known, detailed description thereof will be omitted.

  Further, as shown in FIG. 7, when there are a plurality of data processing blocks, a sequence class is similarly created for each. FIG. 10 is a diagram showing the sequence class created for each data processing block in FIG. 7 and the execution order of each sequence. The common verification function can perform system verification by sequentially calling sequence functions of each sequence class, and the test description in the individual verification can be used for system verification.

  Further, as shown in FIG. 12, a test bench for system verification can be configured from a test bench created by individual verification. FIG. 12 is a diagram that summarizes the verification flow ((a) to (c)) for each data processing block into one ((d)). The system here is a system having three data processing blocks.

  FIG. 13 is a block diagram showing a basic configuration of a verification apparatus of a system having three data processing blocks. In the figure, reference numeral 1315 indicates each part for performing the individual verification test bench for the data processing 1 block, and 1325 indicates each part for performing the individual verification test bench for the data processing 2 block. These show each part for performing an individual verification test bench about data processing 3 blocks.

In this way, the data monitor used in the individual verification is also effective in the test bench for system verification, and when an expected value comparison error occurs in the system verification, it is specified which data processing block block is caused by a bug. Is easy.
JP 2000-031284 A JP 2002-55843 A

  The semiconductor circuit to be verified and the test bench (test program) for verifying the semiconductor circuit have become larger year by year as the semiconductor process has evolved. In order to perform logic verification using this large test bench in order to verify the logic of this large semiconductor circuit, it is necessary to mount a large-sized memory in the host computer. However, since the memory is expensive, it is difficult to load as much memory as possible in all the host computers.

  On the other hand, there is a difference in the circuit scale to be verified and the size of the test bench of each tester, and not all testers require a large memory.

  For this reason, some host computers are equipped with the maximum amount of memory within the limits of the budget, so that the amount of memory varies depending on the host computer, and the host computer depends on the size of the test bench and the content of the test. There was a request to change the allocation. However, there is a problem that the above-described method for managing resources collectively is not sufficient.

  In other words, if the memory capacity of the host computer allocated by the management system is less than the memory capacity required by the test (test bench), the simulation ends abnormally.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique for permitting execution of a requested program to an optimal host computer.

  Further, when verifying each data processing block with the configuration shown in FIG. 13, each data monitor monitors the processing output data in each cycle of the clock as described above, and the number of times of monitoring can be increased. There was a problem that the simulation time was affected more and more slowly. That is, the more data monitors, the longer the simulation time. On the other hand, there is a method in which only the last stage data monitor, that is, the data 3 monitor 1333 in FIG. 13 is enabled, but in this case, when an error is detected in this monitor, which data processing block processing There was a problem that it was very difficult to identify whether the error was incorrect. These problems prolong integrated circuit logic verification and have a significant impact on product development schedules.

  Therefore, another object of the present invention is to provide a technique for performing operation verification of a data processing block at a higher speed.

  In order to achieve the object of the present invention, for example, an information processing apparatus of the present invention comprises the following arrangement.

That is, an information processing apparatus holding software shared by a plurality of computers,
A queue holding means for holding a queue corresponding to each group when the plurality of computers are divided into a plurality of groups according to the installed memory capacity;
Upon receiving the execution request for the software, calculation means for obtaining the memory usage necessary for the execution of the software,
Corresponding to a queue corresponding to a group to which a computer having an installed memory capacity allowing the memory usage obtained by the calculation means belongs, and a queue storing the execution job of the software Permission means for granting permission to use the execution job to any of the computers belonging to the group.

  In order to achieve the object of the present invention, for example, the verification apparatus of the present invention comprises the following arrangement.

That is, a plurality of data processing blocks that process input data and output to the subsequent stage are connected in series, and after the data is input to the data processing block on the data input side, the subsequent data processing block is operated sequentially. , A verification device that performs operation verification processing of each data processing block,
For each data processing block,
Monitoring means for monitoring the output of the data processing block at predetermined time intervals;
Storage means for storing the output monitored by the monitoring means;
Holding means for holding correct data that the output monitored by the monitoring means should follow originally;
Judgment means for judging whether or not the output monitored by the monitoring means matches the correct data corresponding to the output;
For the terminal data processing block on the output side, the monitoring unit, the storage unit, and the determination unit of the terminal data processing block are operated, and only the storage unit is operated for data processing blocks other than the terminal data processing block. When the operation verification process is performed and it is determined that the determination unit does not match, the output of each data processing block is output to the storage unit of each data processing block at the most recent time at the time of the determination. A control means for resetting the saved output value and restarting the operation of each data processing block;
After the operation is resumed by the control means, a specifying means for specifying a data processing block having a determining means determined to be inconsistent among the determining means of each data processing block.

  In order to achieve the object of the present invention, for example, an information processing method of the present invention comprises the following arrangement.

In other words, when a plurality of computers holds software shared and the plurality of computers are divided into a plurality of groups according to the installed memory capacity, a queue holding unit that holds a queue corresponding to each group is provided. An information processing method performed by an information processing apparatus,
Upon receiving the execution request for the software, a calculation step for obtaining a memory usage necessary for executing the software;
Corresponding to the storage step for storing the execution job of the software and the queue for storing the execution job in the storage step in the queue corresponding to the group to which the computer having the installed memory capacity allowing the memory usage obtained in the calculation step belongs A permission step of giving permission to use the execution job to any of the computers belonging to the group.

  In order to achieve the object of the present invention, for example, a method for controlling a verification apparatus of the present invention comprises the following arrangement.

That is, a plurality of data processing blocks that process input data and output to the subsequent stage are connected in series, and after the data is input to the data processing block on the data input side, the subsequent data processing block is operated sequentially. , A method of controlling a verification device that performs an operation verification process of each data processing block,
For each data processing block,
A monitoring step of monitoring the output of the data processing block at predetermined time intervals;
A storage step for storing the output monitored in the monitoring step;
A holding step for holding correct data that the output monitored in the monitoring step should originally follow;
A determination step of determining whether or not the output monitored in the monitoring step matches the correct data corresponding to the output;
For the terminal data processing block on the output side, the processing in the monitoring step, the storage step, and the determination step of the terminal data processing block is operated, and for the data processing blocks other than the terminal data processing block, the processing in the storage step When the operation verification processing is performed by operating only the data, and it is determined that they do not match in the determination step, the output of each data processing block is displayed at the most recent time at the time of the determination. After resetting the output value stored in the storage step, the control step of restarting the operation of each data processing block,
And a specifying step of specifying a data processing block having a determination step that is determined not to match among the determination steps of the respective data processing blocks after the operation is resumed by the control step.

  According to the configuration of the present invention, it is possible to permit execution of a requested program to an optimal host computer.

  Hereinafter, the present invention will be described in detail according to preferred embodiments with reference to the accompanying drawings.

[First Embodiment]
First, a conventional system will be described.

<Conventional system>
FIG. 3 is a diagram showing a functional configuration of a conventional system. This system is for permitting execution of a simulation program for performing logic verification of a circuit on a requested computer.

  Reference numeral 300 denotes a simulation execution receiving unit that receives a simulation execution request from a user. When a simulation execution request is input, the simulation execution accepting unit 300 inputs a job for executing the requested simulation (software) to the simulation queue 320. The simulation queue 320 functions as a queue that sequentially holds jobs submitted from the simulation execution receiving unit 300 and monitors the execution status of software.

  Here, for the sake of explanation, the number of software licenses is the same as the number of host computers described later. That is, in order to perform the simulation at high speed, control was performed so that only one simulation is performed on one host computer (only one simulation software operates).

  Reference numeral 330 denotes a host computer group. If there is any host computer that is not currently processing (free), a license for executing software is given to this host computer, and a job that can be taken out from the simulation queue 320 next. Is assigned to this host computer, the host computer executes the assigned job (executes the software).

  When the execution of the job is completed, the host computer notifies the simulation queue 320 that the job has been completed, so that the simulation queue 320 knows the host computer that is executing the simulation software and puts it into the simulation queue 320. The assigned job is assigned to a free host computer in the host computer group 330.

  FIG. 4 is a flowchart of processing performed by the simulation queue 320. First, it is checked whether there is a free host computer in the host computer group 330 (step S410). If there is no vacant host computer, it waits for an instruction to end simulation execution (step S450). If this instruction is received, the process proceeds to step S420, and a simulation software license is issued to the host computer that issued this instruction (step S450). Together with step S420), the execution permission of this simulation software is given (step S430).

  As a result, the host computer executes the simulation software to which the execution permission is given. When the execution is completed, the license is released, and the simulation queue 320 waits for and accepts this (step S440).

  Here, for example, it is assumed that the simulation software is a logic verification simulation of a semiconductor circuit. Then, the execution load of the simulation software for the host computer varies depending on the scale of the semiconductor circuit to be logically verified and the scale of the verification program (test and test bench). That is, if these are large, more memory is used on the computer. Sometimes, the execution load of the simulation software exceeds the capacity of the host computer, that is, the memory capacity necessary for executing the simulation software exceeds the memory size of the host computer, causing a problem that the simulation fails.

  For this reason, the host computer is required to be equipped with a larger size memory. However, since the memory is expensive, there is a problem that it is difficult to install a sufficient memory in all the host computer groups described above.

  As described above, since the execution load of the simulation software varies depending on the scale of the semiconductor circuit to be verified and the verification program, if these are relatively small, it is not necessary to install a large memory in the host computer. There is a problem that a simulation can be performed and it is useless to install more memory than necessary.

<System according to this embodiment>
In order to solve the above problem, the system according to the present embodiment has the configuration shown in FIG. FIG. 1 is a diagram illustrating a functional configuration of a system according to the present embodiment. The system according to the present embodiment also manages the execution of simulation software requested from the host computer. In the following description, this simulation is assumed to be a logic verification simulation of a semiconductor circuit. . However, the following description may be other types of simulations, and is not limited to the types of simulations. Further, the type of software for managing execution is not particularly limited.

  The system according to the present embodiment is roughly divided into a server device 190, a memory capacity A group 130, a memory capacity B group 131, and a memory capacity C group 132.

  The server device 190 includes a simulation execution receiving unit 100, a memory usage amount prediction unit 101, a resource management unit 110, a simulation queue A120, a simulation queue B121, and a simulation queue C122.

  In the present embodiment, the simulation execution receiving unit 100, the memory usage prediction unit 101, the resource management unit 110, the simulation queue A120, the simulation queue B121, and the simulation queue C122 are described as each unit constituting one apparatus (server apparatus 190). However, it goes without saying that each may be a separate device.

  In the system according to this embodiment, first, a plurality of host computers are divided in advance into a plurality of groups according to the installed memory capacity. In the figure, the data is divided into three groups, and the groups are a memory capacity A group 130, a memory capacity B group 131, and a memory capacity C group 132, respectively. Here, it is assumed that the host computer belonging to the memory capacity C group 132 has the largest memory capacity, the host computer belonging to the memory capacity B group 131 has the next largest memory capacity, and the host computer belonging to the memory capacity A group 130 Have the smallest memory capacity.

  Here, in the following description, the memory size (may be an average value or a minimum value) of the host computers belonging to the memory capacity A group 130 is A, and the memory possessed by the host computers belonging to the memory capacity B group 131 is the memory size. Is represented by B, and the memory size of the host computer belonging to the memory capacity C group 132 is represented by C.

  In this embodiment, a queue is provided for each group, a simulation queue A120 is provided for the memory capacity A group 130, and a simulation queue B121 is provided for the memory capacity B group 131. A simulation queue C122 is provided for the memory capacity C group 132.

  FIG. 5 is a block diagram showing a basic configuration of the server device 190.

  In the figure, reference numeral 501 denotes a CPU, which controls the entire server device 190 using programs and data stored in a RAM 502 and a ROM 503, and executes each process described later performed by the server device 190.

  Reference numeral 502 denotes a RAM which includes an area for temporarily storing programs and data loaded from the external storage device 506 and a work area used when the CPU 501 executes various processes. The “queue” that appears in the following description is provided in the RAM 502. Further, an area for temporarily storing programs and data received from the outside via the NIC 507 described later is provided.

  A ROM 503 stores setting data of the server device 190, a boot program, and the like.

  An operation unit 504 includes a mouse and a keyboard, and can input various instructions to the CPU 501.

  A display unit 505 includes a CRT, a liquid crystal screen, and the like, and can display processing results by the CPU 501 with images, characters, and the like.

  Reference numeral 506 denotes an external storage device, which is a large-capacity information storage device such as a hard disk drive device. Here, an OS (Operating System) and a program or data for causing the CPU 501 to execute each process described below performed by the server device 190. Are stored in the RAM 502 under the control of the CPU 501 and are processed by the CPU 501.

  Reference numeral 507 denotes a NIC (network interface) that functions as an interface for performing data communication with each host computer described later.

  A bus 508 connects the above-described units.

  Next, processing performed by a system including the server device 190 having such a configuration will be described. Since the simulation software execution request input from the user is input via the simulation execution receiving unit 100, the memory usage prediction unit 101 determines the amount of memory to be used when executing the requested simulation software, It asks whether to simulate a circuit of scale. For example, even if the same simulation software is executed, a larger memory capacity is required to perform logic verification of a large scale circuit, and conversely, a smaller memory is required to perform logic verification of a small scale circuit. Capacity is good. Therefore, if you know the minimum amount of memory required to run the simulation software and the scale of the logic to be verified, the amount of memory required to run the requested simulation is obtained ( Predict).

  The memory capacity necessary for executing the simulation is obtained, for example, by acquiring in advance the size of data used for the simulation and the amount of memory used by the subprogram from the simulation software program received by the simulation reception execution unit 100. The total usage amount is set as the maximum usage amount.

  When the required maximum memory usage is obtained, the resource management unit 110 performs simulation software execution jobs (logic verification of the requested scale circuit) in any of the simulation queue A120, simulation queue B121, and simulation queue C122. Whether to submit a simulation software execution job) based on the memory usage calculated by the memory usage prediction unit 101 and the capacity of each queue.

  For example, when the memory usage obtained by the memory usage prediction unit 101 is N and A <N <B, that is, when the memory usage is larger than A, such a simulation software execution job is executed. Only a host computer belonging to the memory capacity B group 131 or a host computer belonging to the memory capacity C group 132 can be executed. Therefore, even if it is not a host computer belonging to the memory capacity C group 132, a host computer belonging to the memory capacity B group 131 is sufficient, so an execution job is submitted to the simulation queue B121 corresponding to the memory capacity B group 131.

  However, for example, if the simulation queue B121 is in a waiting state (a state where a job cannot be submitted) and the simulation queue C122 has a free space, it is overspec that the host computer belonging to the memory capacity C group 132 execute the job. However, the job may be submitted to the simulation queue C122.

  When a job is submitted, the simulation queue B 121 is so-called “free”, such as not performing processing among the host computers belonging to the memory capacity C group 132, or having sufficient capacity to perform other processing. The host computer is searched, a job execution license is given to the host computer, and job execution permission is given.

  All of the job execution processing may be performed by the host computer, or part of the job execution processing may be performed by the server device 190. In any case, even if you want the host computer to do everything, this host computer is chosen because it has the memory size required to execute the job, so this job Can always be executed, and there is no interruption of processing due to insufficient memory size.

  FIG. 2 is a flowchart of processing performed by the server device 190 described above. Note that a program and data for causing the CPU 501 to execute the processing according to the flowchart of FIG. 10 are pre-loaded from the external storage device 506 to the RAM 502, and the server device 190 will be described below when the CPU 501 executes the program and data. Processing will be executed. In addition, since the process in each following step is as above-mentioned, it demonstrates easily here.

  First, when the CPU 501 detects a simulation software execution request input by the user via the operation unit 504, it analyzes data described in the simulation software (step S201) and uses it when the requested simulation software is executed. As a result, the amount of memory used when this simulation software is executed to perform logic verification of the requested circuit scale is obtained ( Prediction) (step S202).

  Of the memory amounts (A, B, and C in FIG. 1) installed in the host computers of each group, a memory amount that allows the memory usage amount N obtained in step S202 is selected (step S203). Here, if there is no memory amount that allows the memory usage amount N obtained in step S202 among the memory amounts installed in the host computers of each group, the process proceeds to step S205, and a warning is issued. Is issued (step S205), but if this is set to “valid” due to the preset setting, the process is terminated via step S206.

  As a result, it can be seen that the predicted memory usage exceeds the memory capacity installed in the host computer, and the simulation program can be reviewed without executing useless simulation. Even if the expected memory usage exceeds the memory capacity installed in the host computer, the simulation does not necessarily fail, so it may be desired to execute the simulation. At this time, by setting the above-described setting to “invalid”, the setting can be put into the simulation queue of the host computer equipped with the maximum memory. As described above, when the simulation program is reviewed, it is effective to set the above setting to “invalid” even when there is no room for change.

  On the other hand, when the setting is “invalid”, the process proceeds to step S210 via step S206.

  On the other hand, if there is a memory amount that allows the memory usage amount N obtained in step S202 among the memory amounts (A, B, C in FIG. 1) installed in the host computers of each group, the processing is performed. Advances to step S204. Here, a description will be given assuming that the memory capacity B group 131 corresponds to this. Therefore, in step S204, the memory capacity B group 131 is selected (step S204).

  Then, it is determined whether there is a vacant host computer among the host computers belonging to the memory capacity B group 131 (step S210). If not, the process proceeds to step S250 and waits for an instruction to end simulation execution (step S210). If this instruction is received, the process proceeds to step S220, a license for the simulation software is issued to the host computer that issued this instruction (step S220), and permission to execute the simulation software is given (step S230).

  As a result, the host computer executes the simulation software to which the execution permission is given. When the execution is completed, the license is released, and the CPU 501 waits for this and accepts it (step S240).

  As described above, according to the present embodiment, execution of the requested program can be permitted to an optimal host computer. As a result, for example, in logic verification of a semiconductor circuit, it is possible to minimize the investment in the memory installed in the host computer that performs the logic verification simulation, and to provide a logic verification system that does not run a useless simulation. I can do it.

[Second Embodiment]
In the present embodiment, a case where operation verification of three data processing blocks coupled in series is performed will be described. However, the essence of the following description is not limited to the number of data processing blocks. It will be clear from the explanation.

<Conventional verification system>
First, a conventional verification method for three data processing blocks (data processing block 1, data processing block 2 and data processing block 3) included in the system LSI 601 shown in FIG. 2 will be described.

  FIG. 13 shows the configuration of an apparatus for verifying these three data processing blocks by a conventional method as described above. In the figure, the logic circuits to be verified are a data processing 1 block 1106, a data processing 2 block 1320, and a data processing 3 block 1330. In the following description, the CPU 602 executes the program and controls various processes.

  The input data file 1101 used for verification in the figure is interpreted by the input bus model 1102 and sent to the data processing 1 block 1106.

  The parameter data file 1103 for setting the operation mode at this time is set to the operation mode through the CPU I / F model 1105, and the data processing 1 block 1106, the data processing 2 block 1320, and the data processing 3 block 1330 are set. Operate according to the specified operation mode. In other words, the data processing 1 block 1106 processes the input data file 1101 input via the input bus model 1102 according to the set operation mode and sends it to the subsequent data processing 2 block 1320. The data processing 2 block 1320 processes the data output from the data processing 1 block 1106 according to the set operation mode and sends the processed data to the subsequent data processing 3 block 1330. The data processing 3 block 1330 processes the data output from the data processing 2 block 1320 according to the set operation mode and outputs the processed data through the output bus model 1340 at the subsequent stage.

  On the other hand, the expected value 1 data file 1108 as correct data to be output by the data processing 1 block 1106 is generated in advance from the input data file 1101 and the parameter data file 1103 using the data processing 1 program 1104 for generating correct data. ing. The output of the data processing 1 block 1106 is monitored by the data 1 monitor 1111 at predetermined time intervals. The data 1 monitor 1111 compares the monitored output with the expected value 1 data file 1108, and the data processing 1 block 1106 is compared. Verify whether the expected processing has been performed.

  In addition, the expected value 2 data file 1322 as correct data to be output by the data processing 2 block 1320 is previously generated using the data processing 2 program 1321 that generates correct data (previously generated by the data processing 1 program 1104). ) It is generated from the expected value 1 data file 1108 and the parameter data file 1103. The output of the data processing 2 block 1320 is monitored by the data 2 monitor 1323 at predetermined time intervals. The data 2 monitor 1323 compares the monitored output with the expected value 2 data file 1322, and the data processing 2 block 1320 Verify whether the expected processing has been performed.

  Further, the expected value 3 data file 1332 as correct data to be output by the data processing 3 block 1330 is generated in advance using the data processing 3 program 1331 that generates correct data (previously generated by the data processing 2 program 1321. ) It is generated from the expected value 2 data file 1322 and the parameter data file 1103. The output of the data processing 3 block 1330 is monitored by the data 3 monitor 1333 at predetermined time intervals, and the data 3 monitor 1333 compares the monitored output with the expected value 3 data file 1332, and the data processing 3 block 1330. Verify whether the expected processing has been performed.

  In the verification performed by the system having the above configuration, if the data processing block to be verified performs an incorrect operation, each data monitor connected to the output bus of each data processing block can detect this. It is easy to specify whether the data processing block has performed an error, and there is an advantage of improving the verification efficiency. On the other hand, since these data monitors monitor the bus for each cycle, communication occurs between the bus and the data monitor each time, causing a reduction in simulation speed. Since the number of connected data monitors increases as the system becomes larger, the simulation speed is significantly reduced.

  Therefore, the verification system according to the present embodiment is made in view of this. Hereinafter, the verification system according to the present embodiment will be described.

<Verification system according to this embodiment>
FIG. 15 is a block diagram illustrating a basic configuration of the verification system according to the present embodiment. In the figure, the same parts as those in FIGS. 11 and 13 are denoted by the same reference numerals, and the description thereof is omitted.

  The configuration shown in FIG. 15 is different from the configuration shown in FIG. 13 in that a switch 1501 for switching monitoring / non-monitoring of each data monitor (data 1 monitor 1111, data 2 monitor 1323, data 3 monitor 1333). 1502 and 1503 are provided. For example, when the switch 1501 is turned on, the output line from the data processing 1 block 1106 is connected to the data 1 monitor 1111. Therefore, the data 1 monitor 1111 can monitor the output from the data processing 1 block 1106. When 1501 is turned off, since the output line from the data processing 1 block 1106 is not connected to the data 1 monitor 1111, the data 1 monitor 1111 cannot monitor the output from the data processing 1 block 1106. The same applies to the switch 1502.

  In this way, monitoring / non-monitoring can be switched by this switch by the data monitor. The monitoring / non-monitoring control means by the data monitor is not limited to such means.

  In such a system, operation verification of each data processing block is performed as follows. In addition, control of each process demonstrated below shall be performed by CPU602.

  First, since the CPU 602 sends an instruction to turn off both the switches 1501 and 1502, the switches 1501 and 1502 both receive this and turn off themselves, and then the CPU 602 controls the verification process. That is, the data processing 1 block 1106 processes the input data file 1101 input via the input bus model 1102 according to the set operation mode and sends it to the subsequent data processing 2 block 1320. The data processing 2 block 1320 processes the data output from the data processing 1 block 1106 according to the set operation mode and sends the processed data to the subsequent data processing 3 block 1330. The data processing 3 block 1330 processes the data output from the data processing 2 block 1320 according to the set operation mode and outputs the processed data through the output bus model 1340 at the subsequent stage. The data 3 monitor 1333 monitors the output of the data processing 3 block 1330 at predetermined time intervals, compares the monitored output with the expected value 3 data file, and determines whether or not they match. Therefore, the data 3 monitor 1333 performs a determination process as to whether or not they match at every predetermined time interval.

  In addition, the CPU 602 performs a process of sampling the output of each data processing block at predetermined time intervals and storing it in the memory in the memory controller 604.

  In this way, each data processing block repeats the process of processing the input data and outputting it to the subsequent stage, and the CPU 602 samples the output of each data processing block every predetermined time interval, and the memory controller 604. Store in memory. Further, the data 3 monitor 1333 determines whether the output of the data processing 3 block 1330 and the expected value 3 data file 1332 coincide with each other at predetermined time intervals.

  Here, when the data 3 monitor 1333 determines that “they do not match” at a certain time (when Error is detected), the CPU 602 detects this and stops the operation of each unit. Here, the fact that the data 3 monitor 1333 determines that “they do not match” means that either one or both of the data processing 1 block 1106 and the data processing 2 block 1302 are different from the expected value data file. It will be. Therefore, in the following, the data processing block whose operation is not normal is identified by detecting the data processing 1 block 1106 and the data processing 2 block 1302 that do not match the expected value data file.

  First, the CPU 602 turns on the switches 1501 and 1502. Then, the output data of each data processing block stored in the memory in the memory controller 604 (that is, the most recently stored in the memory) is read out at the timing closest to the time point when the CPU 602 detects the “not coincident” determination. , Reset the output of each data processing block. That is, the verification process is performed again from the state at the timing closest to the time point when the CPU 602 detects the determination of “not matching”. At this time, since the switches 1501 and 1502 are turned on, the output of the data processing 1 block 1106 and the data processing 2 block 1302 is monitored when the verification process is performed again.

  When the CPU 602 controls each unit to resume the operation of each unit, the data 1 monitor 1111 and the data 2 monitor 1323 monitor the outputs of the data processing 1 block 1106 and the data processing 2 block 1302, respectively. Thus, the data 1 monitor 1111 and / or the data 2 monitor 1323 determines that “they do not match”.

  As a result, not all the data monitors are operated at the start of the verification process, and only one data monitor is operated, so that a large amount of data communication for data monitoring does not occur, and the verification process is faster than the conventional one. Can be done.

  FIG. 14 is a flowchart of the verification process according to the present embodiment. Note that the CPU 602 controls the processing according to the flowchart of FIG.

  First, since the CPU 602 sends an off instruction to the switches 1501 and 1502 (step S900), the switches 1501 and 1502 turn themselves off. As a result, monitoring by the data 1 monitor 1111 and the data 2 monitor 1323 is not performed.

  Next, the CPU 602 sets a time interval for storing the output data of each data processing block in the memory in the memory controller 604 (step S901). This is set in advance in the memory in the memory controller 604. You may make it preserve | save and you may make it set according to the clock of CPU602.

  Next, the process is advanced by one cycle (step S902). Here, when the process is advanced by one cycle, the data processing 1 block 1106 processes the input data file 1101 input via the input bus model 1102 in accordance with the set operation mode and sends it to the subsequent data processing 2 block 1320. Then, the data processing 2 block 1320 processes the data output from the data processing 1 block 1106 according to the set operation mode and sends it to the subsequent data processing 3 block 1330. Next, the data processing 3 block 1330 The data output from the data processing 2 block 1320 is processed according to the set operation mode and output through the output bus model 1340 in the subsequent stage, and the data 3 monitor 1333 outputs the data processing 3 block 1330 at predetermined time intervals. Monitored output and expected value 3 data It compares with the file, determines whether the match refers to performing a series of processes called.

  If the data 3 monitor 1333 determines that “they do not match” as a result of performing one cycle of processing (step S903), the processing proceeds to step S908, and the switches 1501 and 1502 are turned on (step S908). Then, the output of each data processing block most recently stored in the memory in the memory controller 604 is reset to each data processing block (step S909), and then one cycle of processing is resumed (step S910).

  The one-cycle processing here includes monitoring processing and determination processing by the data 1 monitor 1111 and the data 2 monitor 1323 in addition to the processing in step S902.

  If at least one of the data 1 monitor 1111 and the data 2 monitor 1323 detects an error, the CPU 602 detects this and identifies the data processing block that generated the error (step S912).

  More specifically, if the data 1 monitor 1111 detects an error, the data processing 1 block 1106 is identified as the data processing block that generated the error (the output does not match the expected value 1 data file 1108), and the data If the 2 monitor 1323 detects an error, the data processing 2 block 1320 is identified as the data processing block that generated the error (the output does not match the expected value 2 data file 1322).

  On the other hand, if there is no data monitor that has detected an error in step S911, processing step S910 is repeated. The iterative process is performed until the CPU 602 detects Error in step S903.

  On the other hand, if it is determined in step S903 that the data 3 monitor 1333 has not made a “mismatch” determination, the process proceeds to step S904. If the operation of each data processing block has not been completed, the process proceeds to step S904. In S905, it is determined whether or not the time set in Step S901 has elapsed since the start of the process in Step S902. If not, the process returns to Step S902, and the subsequent processes are repeated. If it has elapsed, the process proceeds to step S907, and the CPU 602 stores the output of each data processing block in the memory in the memory controller 604 (step S907).

  Here, when the output of each data processing block is stored in the memory, it is assumed that the memory stores the previous two times. When the current storage is performed, the previous data (the data output from each previous data processing block) is erased, and the current data (the output data from each current data processing block) is newly stored. Store. If the output data is read from the memory in step S909, the previous data is read twice.

  In this way, the previous two minutes are stored, but if this is stored only up to the previous one, if Error is detected in step S903 in the next stored cycle. The simulation state can be returned only one cycle before, and even if all the switches are turned on, the data processing block in which the error has occurred cannot be specified. Therefore, in this embodiment, the output of each data processing block is stored up to the previous two times.

  In this embodiment, each data monitor detects an error when the output of the data processing block and the expected value data file do not match even once, but the data monitor is not limited to once, but is set in advance. It may be the number of times.

[Other Embodiments]
Also, an object of the present invention is to supply a recording medium (or storage medium) in which a program code of software that realizes the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (or CPU or Needless to say, this can also be achieved when the MPU) reads and executes the program code stored in the recording medium. In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium on which the program code is recorded constitutes the present invention.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Furthermore, after the program code read from the recording medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function is based on the instruction of the program code. It goes without saying that the CPU or the like provided in the expansion card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

  When the present invention is applied to the recording medium, program code corresponding to the flowchart described above is stored in the recording medium.

It is a figure which shows the function structure of the system which concerns on the 1st Embodiment of this invention. It is a flowchart of the process which the server apparatus 190 performs. It is a figure which shows the function structure of the conventional system. 5 is a flowchart of processing performed by a simulation queue 320. 3 is a block diagram showing a basic configuration of a server device 190. FIG. It is a block diagram which shows the basic composition of the integrated circuit of a general system LSI. It is a block diagram which shows the structure of the data path 607 in which three data processing blocks are connected in series. It is a figure which shows the flow of a process of the individual verification of a data processing block (Data processing 1 block in the same figure). It is a figure which shows the structural example of the test description used conventionally. FIG. 8 is a diagram illustrating a sequence class created for each data processing block in FIG. 7 and an execution order of each sequence. It is a figure which shows the flow of a process of the individual verification of a data processing block (Data processing 1 block in the same figure). It is the figure which put together the flow ((a)-(c)) of verification with respect to each data processing block into one ((d)). It is a block diagram which shows the basic composition of the verification apparatus of the system which has three data processing blocks. It is a flowchart of the verification process which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the basic composition of the verification system which concerns on the 2nd Embodiment of this invention.

Claims (8)

An information processing apparatus holding software shared by a plurality of computers,
A queue holding means for holding a queue corresponding to each group when the plurality of computers are divided into a plurality of groups according to the installed memory capacity;
Upon receiving the execution request for the software, calculation means for obtaining the memory usage necessary for the execution of the software,
Corresponding to a queue corresponding to a group to which a computer having an installed memory capacity allowing the memory usage obtained by the calculation means belongs, and a queue storing the execution job of the software An information processing apparatus comprising: permission means for giving permission to use the execution job to any of the computers belonging to the group.   The information processing apparatus according to claim 1, wherein the execution job is an execution job of logic verification software for a circuit of a designated scale. A plurality of data processing blocks that process input data and output to the subsequent stage are connected in series, and after the data is input to the data processing block on the data input side, the subsequent data processing block is operated sequentially, A verification device that performs an operation verification process of the data processing block of
For each data processing block,
Monitoring means for monitoring the output of the data processing block at predetermined time intervals;
Storage means for storing the output monitored by the monitoring means;
Holding means for holding correct data that the output monitored by the monitoring means should follow originally;
Judgment means for judging whether or not the output monitored by the monitoring means matches the correct data corresponding to the output;
For the terminal data processing block on the output side, the monitoring unit, the storage unit, and the determination unit of the terminal data processing block are operated, and only the storage unit is operated for data processing blocks other than the terminal data processing block. When the operation verification process is performed and it is determined that the determination unit does not match, the output of each data processing block is output by the storage unit of each data processing block at the most recent time at the time of the determination. A control means for resetting the saved output value and restarting the operation of each data processing block;
A verification apparatus comprising: a specifying unit that specifies a data processing block having a determination unit that is determined not to match among the determination units of each data processing block after the operation is resumed by the control unit.   The specifying unit specifies a data processing block having a determination unit that is determined not to match among the determination units of each data processing block between the time point after the operation is resumed by the control unit and the time point. The verification apparatus according to claim 3. Information processing provided with queue holding means that holds software shared by a plurality of computers and holds a queue corresponding to each group when the plurality of computers are divided into a plurality of groups according to the installed memory capacity An information processing method performed by a device,
Upon receiving the execution request for the software, a calculation step for obtaining a memory usage necessary for executing the software;
Corresponding to the storage step for storing the execution job of the software and the queue for storing the execution job in the storage step in the queue corresponding to the group to which the computer having the installed memory capacity allowing the memory usage obtained in the calculation step belongs And a permission step of granting permission to use the execution job to any of the computers belonging to the group. A plurality of data processing blocks that process input data and output to the subsequent stage are connected in series, and after the data is input to the data processing block on the data input side, the subsequent data processing block is operated sequentially, A method for controlling a verification apparatus that performs an operation verification process of the data processing block of
For each data processing block,
A monitoring step of monitoring the output of the data processing block at predetermined time intervals;
A storage step for storing the output monitored in the monitoring step;
A holding step for holding correct data that the output monitored in the monitoring step should originally follow;
A determination step of determining whether or not the output monitored in the monitoring step matches the correct data corresponding to the output;
For the terminal data processing block on the output side, the processing in the monitoring step, the storage step, and the determination step of the terminal data processing block is operated, and for the data processing blocks other than the terminal data processing block, the processing in the storage step When the operation verification processing is performed by operating only the data, and it is determined that they do not match in the determination step, the output of each data processing block is displayed at the most recent time at the time of the determination. After resetting the output value stored in the storage step, the control step of restarting the operation of each data processing block,
And a specifying step for specifying a data processing block having a determination step that is determined not to match among the determination steps of each data processing block after the operation is resumed by the control step. Control method.   A program causing a computer to execute the information processing method according to claim 5.   A computer-readable storage medium storing the program according to claim 7.

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