WO2023233616A1

WO2023233616A1 - Method for verifying logic circuit, program for verifying logic circuit, and system for verifying logic circuit

Info

Publication number: WO2023233616A1
Application number: PCT/JP2022/022468
Authority: WO
Inventors: 明宏江口
Original assignee: 三菱電機株式会社
Priority date: 2022-06-02
Filing date: 2022-06-02
Publication date: 2023-12-07
Also published as: JPWO2023233616A1

Abstract

Provided is a technology with which it is possible for a user to stop an unnecessary function block and quickly execute a simulation of a logic circuit. This method for verifying whether or not there is an abnormality in a logic circuit includes: a step (S825) for extracting a clock signal and a resetting signal that are inputted to each of a plurality of function blocks included in a logic circuit; a step (S810) for referring to a test bench; s step for referring to a stoppability assessment table in which is stored information indicating whether each of the plurality of function blocks can be stopped within a test in which the test bench is used; and a step (S840, S845, S855) for stopping the clock signal and the resetting signal inputted to one or more function blocks that do not affect the activity of a function block being verified, in accordance with information acquired from the stoppability assessment table, and executing a test of the function block being verified based on the test bench.

Description

Logic circuit verification method, program for logic circuit verification, and system for logic circuit verification

The present disclosure relates to logic circuit verification technology, and more specifically, to speeding up logic circuit verification.

In the development of semiconductor products such as LSI (Large Scale Integration) having large-scale logic circuits, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), etc. are sometimes used. In either case, a logic circuit simulator is used to verify the consistency of logic circuits included in the semiconductor.

However, in recent years, the scale of semiconductors has progressed, and an increase in simulation time has become a problem. Therefore, there is a need for a technique for shortening the simulation time of semiconductor logic circuits.

Regarding technology for shortening the simulation time of logic circuits, for example, Japanese Patent Laid-Open No. 2006-185202 (Patent Document 1) discloses a circuit simulation device and method. The device and method require ``writing in advance a non-verification block information description indicating the conditions for a non-verification block in the test bench information, or preparing simulation results performed in advance and activation conditions for each module. By doing so, the unverified block information search means automatically detects the unverified blocks in the target circuit, and describes the unverified blocks with at least the minimum information including input/output terminal information. By generating circuit information for resource-saving simulation that is described as a module as a dummy block and performing verification using this circuit information for resource-saving simulation, verification work can be performed with high efficiency while performing verification with high validity. (See [Summary]).

Japanese Patent Application Publication No. 2006-185202

According to the technology disclosed in Patent Document 1, it is necessary to manually set conditions for blocks that are not subject to verification in logic circuit simulation, and the user is required to understand the operation of the logic circuit in detail. Ta. Therefore, there are problems in that the number of engineers who can perform logic circuit simulations is limited, or the learning cost for logic circuit simulations becomes high. Therefore, there is a need for a technique that allows even users who are not familiar with the operation of logic circuits to stop unnecessary functional blocks and execute logic circuit simulations at high speed.

The present disclosure has been made in view of the above-mentioned background, and in one aspect, the purpose is to enable even users who are not familiar with the operation of logic circuits to stop unnecessary functional blocks and perform logic operations. The objective is to provide technology that allows circuit simulation to be executed at high speed.

According to an embodiment, a method for verifying a logic circuit is provided. The verification method includes the steps of extracting clock signals and reset signals input to each of multiple functional blocks included in a logic circuit, referencing a test bench, and testing multiple functional blocks using the test bench. a step of referring to a stopability determination table that stores information indicating whether each of the function blocks can be stopped; and one or more functional blocks that do not affect the operation of the functional block to be verified according to the information obtained from the stopability determination table. and performing a test of the functional block to be verified based on the test bench.

According to an embodiment, even a user who is not familiar with the operation of logic circuits can stop unnecessary functional blocks and execute logic circuit simulations at high speed.

These and other objects, features, aspects, and advantages of this disclosure will become apparent from the following detailed description of the disclosure, taken in conjunction with the accompanying drawings.

1 is a diagram illustrating an example of the configuration of a semiconductor 100 that can be verified by a verification system 200 according to the present embodiment. FIG. 2 is a diagram showing an example of the hardware configuration of a verification system 200 according to the present embodiment. 3 is a diagram showing an example of a functional block table 300. FIG. 4 is a diagram showing an example of a test bench 400. FIG. 5 is a diagram showing an example of a stop target table 500. FIG. 6 is a diagram showing an example of a first stopability determination table 600. FIG. 7 is a diagram illustrating an example of a second stopability determination table 700. FIG. 2 is a diagram illustrating an example of a procedure for verifying a logic circuit (semiconductor) by the verification system 200. FIG. 5 is a diagram illustrating an example of a procedure for extracting a clock and a reset signal for each functional block 110. FIG. FIG. 3 is a diagram illustrating an example of a procedure of trial processing. It is a figure which shows an example of the result of trial processing. 5 is a diagram illustrating an example of criteria for determining whether an input signal affects a functional block 110. FIG. 13 is a diagram illustrating an example of a list 1300 indicating the presence or absence of changes in input signals of all functional blocks 110 included in a semiconductor to be verified. FIG. 14 is a diagram showing an example of a trial result file 1400. FIG.

Hereinafter, embodiments of the technical idea according to the present disclosure will be described with reference to the drawings. In the following description, the same parts are given the same reference numerals. Their names and functions are also the same. Therefore, detailed descriptions thereof will not be repeated.

Embodiment 1.
<A. Overview of logic circuit verification>
FIG. 1 is a diagram showing an example of the configuration of a semiconductor 100 that can be verified by the verification system 200 (see FIG. 2) according to this embodiment. With reference to FIG. 1, the structure of the semiconductor 100, simulation of a logic circuit included in the semiconductor 100, and problems when simulating the logic circuit will be described. Note that the verification system 200 can perform operation verification of a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), or any other semiconductor.

(a. Structure of semiconductor)
The semiconductor 100 includes one or more functional blocks 110 and one or more interconnects 120. One or more functional blocks 110 may be connected to each other via wiring 120.

The functional block 110 is a group of circuits for realizing a certain function. In this specification, a "logic circuit" refers to the entire configuration of a semiconductor (for example, the semiconductor 100), each functional block included in the semiconductor (for example, the functional blocks 110 (funcA to funcG)), an AND circuit, an OR circuit, a NAND circuit. It includes minimum unit logic circuits such as, or a combination thereof. Therefore, it can be said that the functional block 110 is included in the logic circuit (semiconductor 100). It can also be said that the functional block 110 is composed of one or more logic circuits (AND circuit, OR circuit, NAND circuit, etc.).

The simulation of the logic circuit (semiconductor) is executed in units of this functional block. Furthermore, logic circuit simulation is usually performed to verify whether each logic circuit that constitutes a semiconductor operates normally. Therefore, hereinafter, "logic circuit simulation" may also be referred to as "logic circuit (semiconductor) verification or test, or functional block verification or test." "Semiconductor verification or functional block verification" also includes simulating the operation of one or more logic circuits included in a semiconductor. Further, from now on, when referring to individual functional blocks shown in FIG. 1 etc., they will be described as funcA to funcG, and when these functional blocks are collectively referred to as functional block 110.

The wiring 120 propagates signals generated within the semiconductor 100. The wiring 120 outputs a signal inside the semiconductor 120 to the outside, inputs a signal from the outside into the semiconductor 120, or inputs an output signal of one functional block 110 to another functional block 110. The arrow on the wiring 120 indicates the direction of the signal.

As shown in FIG. 1, each functional block 110 is connected to other functional blocks 110 via wiring 120. Further, each functional block 110 may cooperate to execute one process. Therefore, for example, when verifying the operation of funcA, it is necessary to also verify the operation of other functional blocks 110 that may affect the operation of funcA. In the example of FIG. 1, funcB, funcD, funcF, and funcG output signals directly to funcA, which may affect the processing and operation of funcA. funcB outputs a signal to funcA via funcG, which may affect the processing and operation of funcA. Furthermore, funcE outputs a signal to funcD, which may affect the processing and operation of funcD. As a result, funcE can affect the processing and behavior of funcA.

However, there is a possibility that each output signal of funcB to funcG does not affect the processing and operation of funcA. Therefore, as will be described later, the verification system 200 analyzes the design specifications or verification specifications, or executes a test in auto mode in advance to reduce the influence of other functional blocks 110 on the functional block 110 to be verified. The presence or absence can be determined.

Note that the influence of a certain functional block 110 on the functional block 110 to be verified means that a change in the output signal of a certain functional block 110 causes a change in the internal processing of the functional block 110 to be verified, and A change in the output signal includes a change in the output signal of the functional block 110 to be verified.

(b. Functional block test)
A test bench 400 (see FIG. 4) is used to verify the inside of the semiconductor 100. A "test bench" is a configuration file for verifying whether a logic circuit operates according to specifications. For example, it includes settings for input signals used in simulation.

The verification system 200 according to this embodiment verifies the operation of each functional block 110 with reference to the test bench 400. The verification system 200 generates an input signal to the input pin of the semiconductor 100 or an input signal to each functional block 110 based on the description of the test bench 400, and simulates the operation of each functional block 110. The verification system 200 determines that the semiconductor 100 is normal if the operation (output signal) of each functional block 110 in the simulation is in accordance with the specifications.

Note that the test bench 400 may be created for each function or specification to be verified, and one or more test benches 400 may exist. Therefore, when a design change occurs in a semiconductor under development, the verification system 200 needs to perform verification again using a plurality of test benches 400.

(c. Issues when verifying functional blocks)
As described above, the verification system 200 may use one or more test benches 400 to verify the operation of each functional block 110 included in the semiconductor 100. However, in recent years, the functions mounted on semiconductors have continued to increase and become more complex. Therefore, the execution time of simulations for verifying each function (functional block) of a semiconductor continues to increase.

For example, assume that a design change occurs in the semiconductor 100. In this case, the verification system 200 needs to perform the verification of the functional block 110 again using the plurality of test benches 400. However, if a test is executed by operating all the functional blocks 110 every time a semiconductor design is changed, a huge amount of time will be spent verifying the operation of the semiconductor, which may cause a delay in the development schedule.

Therefore, the verification system 200 according to the present embodiment speeds up the simulation (operation verification of the functional block 110) by stopping the operation of the functional block that does not affect the operation of the functional block to be verified.

More specifically, the verification system 200 according to the present embodiment transmits a clock signal to one or more functional blocks 110 that does not affect the operation of the functional block 110 to be verified (that is, does not affect the test). By stopping the reset signal, the operation of one or more functional blocks 110 that does not affect the operation of the functional block 110 to be verified is stopped.

Note that in this specification, "stopping the clock signal and reset signal to a certain functional block 110" includes changing the clock signal and the reset signal so that the certain functional block 110 is in a stopped state. For example, assume that a certain functional block 110 operates with a reset signal (LOW) and stops with a reset signal (HIGH). In this case, "stopping the reset signal to a certain functional block 110" means making the reset signal HIGH (that is, stopping the supply of the reset signal (LOW) that operates a certain functional block 110). .

To this end, the verification system 200 extracts a clock signal and a reset signal that are input to each of the plurality of functional blocks 110 included in the logic circuit. In addition, the verification system 200 refers to the test bench 400, and further refers to a stopability determination table that stores information indicating whether each of the plurality of functional blocks 110 can be stopped in a test using the test bench 400. The verification system 200 stops the clock signal and reset signal to one or more functional blocks 110 that do not affect the operation of the functional block 110 to be verified according to the information obtained from the stopability determination table, and the test bench 400 A test of the functional block 110 to be verified is executed based on the following.

Note that in this specification, the "stoppability determination table" includes the "first stoppability determination table (see FIG. 6)", the "second stoppability determination table (see FIG. 7)", or both. . The first stopability determination table, the second stopability determination table, and the trial result file (see FIG. 14) may be collectively referred to as the stopability determination table.

<B. Verification system configuration>
FIG. 2 is a diagram showing an example of the hardware configuration of verification system 200 according to this embodiment. The hardware configuration of verification system 200 will be described with reference to FIG. 2. The configuration of software executed by the verification system 200 will also be described.

In this specification, the term "system" includes a configuration consisting of one or more devices, a server, a virtual machine or container built in a cloud environment, or a configuration consisting of at least a portion of these. In one aspect, the verification system 200 may be used by a user by being connected to input/output devices such as a display and a keyboard. In other aspects, the verification system 200 may provide various functions to the user as a cloud service or a web application via a network. In this case, the user may use the functionality of the verification system 200 via a browser or client software installed on his or her terminal.

The verification system 200 includes a processor 201, a memory 202, a storage 203, an external device IF (Interface) 204, an input IF 205, an output IF 206, and a communication IF 207 as main hardware configurations. These configurations are interconnected by an internal bus 208.

The processor 201 can execute programs for realizing various functions of the verification system 200. Processor 201 is configured, for example, by at least one integrated circuit. The integrated circuit may be configured by, for example, at least one CPU, at least one GPU, at least one FPGA, at least one ASIC, or a combination thereof.

The memory 202 stores programs executed by the processor 201 and data referenced by the processor 201. In one aspect, the memory 202 may be implemented by DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), or the like.

The storage 203 is a non-volatile memory and may store programs executed by the processor 201 and data referenced by the processor 201. In that case, the processor 201 executes the program read from the storage 203 to the memory 202 and refers to the data read from the storage 203 to the memory 202. In one aspect, the storage 203 is a HDD (Hard Disk Drive), an SSD (Solid State Drive), an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory), or a flash memory. may be realized by .

The external device IF 204 can be connected to any external device such as a printer, scanner, or external HDD. In one aspect, the external device IF 204 may be realized by a USB (Universal Serial Bus) terminal or the like.

The input IF 205 can be connected to any input device such as a keyboard, mouse, touch pad, or game pad. In one aspect, the input IF 205 may be realized by a USB terminal, a PS/2 terminal, a Bluetooth (registered trademark) module, or the like.

The output IF 206 can be connected to any output device such as a cathode ray tube display, a liquid crystal display, or an organic EL (Electro-Luminescence) display. In one aspect, the output IF 206 may be realized by a USB terminal, a D-sub terminal, a DVI (Digital Visual Interface) terminal, an HDMI (registered trademark) (High-Definition Multimedia Interface) terminal, or the like.

The communication IF 207 is connected to other devices via a wired network or a wireless network. In one aspect, the communication IF 207 may be realized by a wired LAN (Local Area Network) port, a Wi-Fi (registered trademark) (Wireless Fidelity) module, or the like. In other aspects, the communication IF 207 may transmit and receive data using communication protocols such as TCP/IP (Transmission Control Protocol/Internet Protocol) and UDP (User Datagram Protocol).

The simulator 210 is software for verifying the semiconductor 100 (logic circuit) and is stored in the storage 203. The processor 201 can implement various functions described with reference to FIGS. 3 to 14 by reading the simulator 210 from the storage 203 to the memory 202 and executing the simulator 210. In some aspects, simulator 210 may be implemented as hardware. The simulator 210 includes a signal extraction section 211, a test bench acquisition section 212, a stopability determination section 213, and a test execution section 214 as main functional components.

The signal extraction unit 211 extracts the clock signal and reset signal (or the source or path of the signal) provided to each functional block 110. Extracting the clock signal and reset signal may include determining the wiring 120 that supplies the clock signal to each functional block 110 and the wiring 120 that supplies the reset signal to each functional block 110. Furthermore, extracting the clock signal and the reset signal may include specifying the location where various signals are cut off to each functional block 110 in the semiconductor 100 (logic circuit). The signal extraction unit 211 stores information on the extracted clock signal and reset signal in the functional block table 300 (see FIG. 3). Function block table 300 is stored in storage 203.

In one aspect, the signal extraction unit 211 extracts the clock signal and reset signal (or the source or path of the signal) provided to each functional block 110 by analyzing a code written in a hardware description language. good. Code 220 is an example of a code in a hardware description language. An example of the analysis procedure of the signal extraction unit 211 will be described with reference to the code 220. The signal extraction unit 211 can analyze the code 220 and determine that "CLK", which only appears in the always statement, is a clock signal. Further, the signal extraction unit 211 can determine that (rstl) appearing in both the always syntax and the begin/end syntax is a reset signal.

Note that the user can store the source code of the semiconductor 100 for performing operation verification in advance in the storage 203 via the external device IF 204, input IF 205, communication IF 207, or the like. The signal extraction unit 211 extracts the clock signal and reset signal provided to each functional block 110 by reading the source code stored in the storage 203.

The test bench acquisition unit 212 reads the test bench 400 from the storage 203. Further, the test bench acquisition unit 212 outputs the test information read from the test bench 400 and the test execution request to the test execution unit 214. Note that the user may store one or more test benches 400 in the storage 203 in advance via the external device IF 204, input IF 205, communication IF 207, or the like.

The stoppage determination unit 213 analyzes the test execution log when the test bench 400 is executed. The stopability determining unit 213 determines whether an input signal from one or more other functional blocks 110 to a certain functional block 110 has an influence on an output signal of a certain functional block 110, based on the analysis result of the execution log. Determine whether or not. Based on the determination result, the stoppage determination unit 213 writes information about other function blocks 110 into the first stopability determination table 600 or the second stopability determination table 700 when verifying the operation of a certain function block 110. Stores information for determining whether to stop.

More specifically, it is assumed that there are test benches 400A, 400B, 400C, 400D, 400E, and 400F. Assume that the test execution unit 214 uses the test bench 400A to verify the operation of a certain functional block 110. In this case, the stopability determination unit 213 can determine which other function blocks 110 can be stopped (does not affect the test) when verifying the operation of a certain function block 110 using the test bench 400A. Alternatively, when verifying the operation of a certain functional block 110 using the test bench 400A, the stoppability determining unit 213 may determine which other functional blocks 110 cannot be stopped (affecting the test). The stoppage determination unit 213 stores the determination result in either the first stoppage determination table 600 or the second stoppage determination table 700 based on the contents of the test bench 400 used. Note that the first stopability determination table 600 and the second stopability determination table 700 are stored in the storage 203. When executing trial processing, which will be described later, the stoppage determination unit 213 stores the determination result in a trial result file 1400 (see FIG. 14).

The test execution unit 214 executes the function block 110 based on the test information and the test execution request, the function block table 300, the first stopability determination table 600, the second stopability determination table 700, or the trial result file 1400. Execute the test (operation verification).

The test execution unit 214 can execute a test based on the test bench 400 by referring to the test information. Furthermore, the test execution unit 214 identifies one or more functional blocks 110 that can be stopped during test execution by referring to the first stopability determination table 600, the second stopability determination table 700, or the trial result file 1400. can be determined. Furthermore, by referring to the function block table 300, the test execution unit 214 determines the clock signal and reset signal to one or more function blocks 110 that can be stopped during test execution, and stops these signals. , one or more stoppable functional blocks 110 may be stopped during test execution.

Note that if there is no information on the first stopability determination table 600, the second stopability determination table 700, or the trial result file 1400 corresponding to the test bench 400 used, the test execution unit 214 uses the test information and test execution information. Based on the request, a test (operation verification) of the functional block 110 may be performed. That is, the test execution unit 214 may execute the test without stopping one or more functional blocks 110 that can be stopped during test execution.

<C. Setting information used for verification process>
Next, setting information used by the verification system 200 to verify logic circuits will be described with reference to FIGS. 3 to 7. The verification system 200 can execute the processes shown in the flowcharts of FIGS. 8 to 10 by referring to each setting information shown in FIGS. 3 to 7.

In a certain aspect, each setting information shown in FIGS. 3 to 7 may be expressed as a table in a relational database, or in other formats such as CSV (Comma Separated Value) or JSON (JavaScript (registered trademark) Object Notation). It may be expressed in any data format.

(a. Each setting information)
FIG. 3 is a diagram showing an example of a functional block table 300. An example of the configuration of the functional block table 300 will be described with reference to FIG. 3.

The functional block table 300 stores information on the clock pin and reset pin of each functional block 110. The functional block table 300 includes a functional block name item 301, a module name item 302, a clock pin item 303, and a reset pin item 304 as main items.

The functional block name item 301 is a name or identifier for uniquely identifying the functional block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the functional block name item 301.

The module name item 302 indicates the function (module) that each functional block 110 realizes. In a certain aspect, a plurality of functional blocks 110 may cooperate to realize one module. In other aspects, a single functional block 110 may implement one module.

The clock pin item 303 indicates the clock signal input port in each functional block 110 or the wiring 120 connected to the input port. When each functional block 110 is considered as an individual semiconductor chip, each functional block 110 includes a plurality of ports (pins), and receives a clock signal from one of the plurality of ports (clock pin).

The reset pin item 304 indicates the reset signal input port in each functional block 110 or the wiring 120 connected to the input port. When each functional block 110 is considered as an individual semiconductor chip, each functional block 110 includes a plurality of ports (pins), and a reset signal is inputted from one of the plurality of ports (reset pin). In some aspects, each functional block 110 may be reset when the signal on the reset pin goes from 1 (HIGH) to 0 (LOW). In other aspects, each functional block 110 may be reset when the signal on the reset pin goes from 0 (LOW) to 1 (HIGH).

The verification system 200 can determine the clock pin and reset pin of the functional block 110 to be stopped by referring to the functional block table 300. Furthermore, when stopping the functional block 110 on a module-by-module basis, the verification system 200 can determine the clock pin and reset pin that correspond to the module name item 302 of the module to be stopped.

FIG. 4 is a diagram showing an example of a test bench 400. An example of the configuration of the test bench 400 will be described with reference to FIG. 4.

The test bench 400 is a configuration file for verifying whether the logic circuit operates according to specifications. The test bench 400 is prepared by the user before performing the operation verification (simulation) of the functional block 110. The user inputs the created test bench 400 into the verification system 200. In one aspect, the user may create the test bench 400 using any means such as a test bench editor provided by the verification system 200. In other aspects, verification system 200 may automatically generate some settings for test bench 400.

The test bench 400 includes, as main items, a verification target item 401, a control mode item 402, a manual mode setting item 403, a spec mode setting item 404, and a verification mode item 405. Note that the test bench 400 may include arbitrary information such as signals input to each functional block 110 in addition to the items shown in FIG.

The verification target item 401 indicates the functional block 110 to be verified. In the example of FIG. 4, funcA is designated as the functional block 110 to be verified.

The control mode item 402 indicates the control mode of verification (test) executed by the verification system 200. The control modes include manual mode, auto mode, and high-speed control OFF mode.

The manual mode (MANUAL) is a mode in which a test (verification) of the functional block 110 to be verified is executed according to the description of a specification document created in advance by the user. The specifications include design specifications created from a design perspective and verification specifications created from a verification perspective. When the manual mode is selected, the verification system 200 stops other functional blocks 110 that do not affect the functional block 110 to be verified during the test, according to the description of the analyzed specification. If manual is selected in the control mode item 402, the verification system 200 selects the type of manual mode based on the manual mode setting item 403.

The auto mode (AUTO) is a mode in which operation verification of the functional block 110 to be verified is automatically performed. The verification system 200 determines whether the operation of the functional block 110 to be verified will be affected based on the execution log of the trial process, the execution log of the acceleration control OFF mode, or the execution log of the manual mode, which will be described later with reference to FIG. It may be determined that the functional block 110 is not present. In the auto mode, the functional block 110 to be verified is selected based on information obtained from the execution log of the verification process executed in advance (list information of functional blocks 110 that does not affect the operation of the functional block 110 to be verified). Run the test. That is, the auto mode can be said to be a mode in which the execution log of a test once executed is used to stop the functional blocks 110 that do not affect the operation of the functional block 110 to be verified in the second and subsequent tests. By using the auto mode, the user can appropriately test each functional block 110 even if the user does not have sufficient knowledge of the semiconductor 100.

The speed-up control OFF mode (OFF) is a mode in which a test is performed without stopping all functional blocks 110. In one aspect, when the high speed or control OFF mode is selected, the verification system 200 obtains a test execution log, and from the log selects a functional block 110 that does not affect the operation of the functional block 110 to be verified. You may judge. Further, the verification system 200 may register the determination result in the first stopability determination table 600 or the second stopability determination table 700.

The manual mode setting item 403 is an item for selecting the type of manual mode. The manual mode includes a specification mode (SPEC) and a verification mode (VERIFICATION). Spec mode is a test based on design specifications. Based on the selection of the spec mode, the verification system 200 refers to the first stoppage determination table 600 and stops the function blocks 110 that do not affect the operation of the function block 110 to be verified during the test. let In addition, based on the selection of the verification mode, the verification system 200 refers to the second stopability determination table 700 and determines which functions do not affect the operation of the functional block 110 to be verified during the test. Block 110 is stopped.

The spec mode setting item 404 is a setting used when spec mode is selected in the manual mode setting item 403. The specification mode setting item 404 is set to one of a plurality of operation modes created based on design specifications.

The verification mode item 405 is a setting used when verification mode is selected in the manual mode setting item 403. The verification mode item 405 is set to one of a plurality of operation modes created based on the verification specifications.

FIG. 5 is a diagram showing an example of a stop target table 500. An example of the configuration of the stop target table 500 will be described with reference to FIG. 5. The stop target table 500 includes information on whether each functional block 110 can be stopped for each verification mode. The verification system 200 may refer to the stop target table 500 to determine which functional blocks 110 can be stopped (which are permitted to be stopped during testing). The verification system 200 stops the functional blocks 110 that are permitted to be stopped during the test, for example, based on the stopability determination table.

The stop target table 500 includes, as main items, a functional block name item 501, a manual mode setting item 502, and an auto mode setting item 503.

The functional block name item 501 is a name or identifier for uniquely identifying the functional block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the functional block name item 301.

The manual mode setting item 502 indicates whether each functional block 110 can be stopped in the manual mode. In the example of FIG. 5, funcA is non-target in manual mode. Conversely, funcB to funcG can be stopped (target) in manual mode.

The auto mode setting item 503 indicates whether each functional block 110 can be stopped in the manual mode. In the example of FIG. 5, funcA to funcG are stoppable (target) in auto mode.

In one aspect, the verification system 200 may receive a setting input for the suspension target table 500 from the user before executing the test. For example, the user may set the functional block 110 that must be operated in manual mode to be unstoppable. In other aspects, the verification system 200 may automatically input settings into the auto mode setting item 503 or automatically update the auto mode setting item 503.

FIG. 6 is a diagram showing an example of the first stopability determination table 600. An example of the configuration of the first stopability determination table 600 will be described with reference to FIG. 6. The first stopability determination table 600 includes a functional block name item 601 and a design specification mode item 610 as main items. In the example of FIG. 6, the design specification mode item 610 includes six design specification modes (specA to specF).

The first stoppage determination table 600 is a table created from the viewpoint of design specifications. The verification system 200 analyzes the design specification input into the verification system 200 by the user, and generates or updates the first stopability determination table 600. More specifically, the verification system 200 determines whether the output signal of a certain function block 110 is different from that of another function based on information such as the wiring connection relationship of each function block 110 and the signal input/output direction described in the design specifications. It may be determined whether block 110 is affected.

In one aspect, the verification system 200 may analyze multiple design specifications to determine whether each functional block 110 can be stopped. For example, suppose that a design specification is created for each function (corresponding to each of specA to specF) to be implemented in the semiconductor 100. In this case, the verification system 200 can analyze each design specification and extract information on whether or not each functional block 110 can be stopped for each specification (corresponding to each column of specA to specF).

In other aspects, the verification system 200 may determine whether each functional block 110 can be stopped by analyzing a single design specification in which specifications for a plurality of functions are described. For example, assume that a single design specification document that describes specifications for all functions (corresponding to each of specA to specF) to be implemented in the semiconductor 100 is created. In this case, the verification system 200 can analyze the single design specification and extract information on whether or not each functional block 110 can be stopped for each specification (corresponding to each column of specA to specF).

Note that the design specification may be data expressed in text data, HTML (Hyper Text Markup Language) data, XML (Extensible Markup Language) data, or any other format.

In another aspect, the verification system 200 may execute a test in auto mode and generate information to be stored in the first stopability determination table 600 from the execution log of the test. For example, assume that the test bench 400 is specified to test in spec mode (specA). It is also assumed that the first stopability determination table 600 does not have a specA column, or that the specA column is empty. In this case, the verification system 200 operates all functional blocks 110 according to the test bench 400 to execute the test. Then, the verification system 200 can generate stoppability information for each functional block 110 during test execution of specA from the execution log, and store the stoppability information in the specA column.

The functional block name item 601 is a name for uniquely identifying the functional block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the functional block name item 601.

The design specification mode item 610 indicates whether each functional block 110 can be stopped in a test based on each design specification mode. In the example in Figure 6, when executing a test based on specA, which is one of the design specification modes, funcA, funcC, funcF, and funcG must operate (cannot be stopped), and funcB, funcD, and funcE must not operate. Good (can be stopped). Similarly, when executing a test based on specB, which is one of the design specification modes, funcA and funcB must operate (cannot be stopped), and funcC, funcD, funcE, funcF, and funcG do not need to operate ( (can be stopped).

The verification system 200 refers to the first stopability determination table 600 when a test in the spec mode and a design specification mode (specA to specG) used for the test are specified in the test bench 400. Then, it is possible to determine which functional blocks 110 can be stopped in the specified design specification mode.

FIG. 7 is a diagram showing an example of the second stopability determination table 700. An example of the configuration of the second stoppability determination table 700 will be described with reference to FIG. 7. The second stopability determination table 700 includes a functional block name item 701 and a verification specification mode item 710 as main items. In the example of FIG. 7, the verification specification mode item 710 includes six verification specification modes (verificationA to verificationF).

The second stoppage determination table 700 is a table created from the viewpoint of verification specifications. The verification system 200 analyzes the verification specification input into the verification system 200 by the user, and generates or updates the second stoppage determination table 700. More specifically, the verification system 200 determines whether the output signal of a certain functional block 110 affects other functional blocks 110 based on the operational information (input/output signals, etc.) of each functional block 110 described in the verification specification. It can be determined whether the A design specification is a specification created by a designer based on design data, whereas a verification specification is a specification created by a person in charge of verification from the viewpoint of verification (testing). Note that the person who creates the design specifications or the verification specifications may be different from the person who uses the verification system 200. If each specification is registered in the verification system 200 in advance, a person using the verification system 200 can use the functions of the verification system 200 to check the specifications of the semiconductor 100 (logic circuit), even if the person using the verification system 200 is not familiar with the specifications of the semiconductor 100 (logic circuit). Test execution of the semiconductor 100 can be accelerated.

In one aspect, the verification system 200 may analyze a plurality of verification specifications to determine whether each functional block 110 can be stopped. For example, assume that a verification specification is created for each function (corresponding to each of verificationA to verificationF) to be implemented in the semiconductor 100. In this case, the verification system 200 can analyze each verification specification and extract information on whether or not each functional block 110 can be stopped for each specification (corresponding to each column of verificationA to verificationF).

In other aspects, the verification system 200 may determine whether each functional block 110 can be stopped by analyzing a single verification specification that describes specifications for a plurality of functions. For example, assume that a single verification specification is created that describes specifications for all functions (corresponding to each of verificationA to verificationF) to be implemented in the semiconductor 100. In this case, the verification system 200 can analyze the single verification specification and extract information on whether or not each functional block 110 can be stopped for each specification (corresponding to each column of verificationA to verificationF).

Note that the verification specification may be data expressed in text data, HTML data, XML data, or any other format.

In another aspect, the verification system 200 may execute a test in auto mode and generate information to be stored in the second stopability determination table 700 from the execution log of the test. For example, assume that the test bench 400 is designated to test in verification mode (verificationA). It is also assumed that the second stopability determination table 700 does not have a column for verificationA, or that the column for verificationA is empty. In this case, the verification system 200 operates all functional blocks 110 according to the test bench 400 to execute the test. Then, the verification system 200 can generate stoppability information for each functional block 110 during test execution of verificationA from the execution log, and store the stoppability information in the column of verificationA.

The functional block name item 701 is a name or identifier for uniquely identifying the functional block 110. Taking the semiconductor 100 as an example, funcA to funcG correspond to the functional block name item 701.

The verification specification mode item 710 indicates whether each functional block 110 can be stopped in a test based on each verification specification. In the example in Figure 7, when executing a test based on verificationA, which is one of the verification specification modes, funcA must operate (cannot be stopped), and funcB, funcC, funcD, funcE, funcF, and funcG must not operate. Good (can be stopped). Similarly, when executing a test based on verificationB, which is one of the verification specification modes, funcB must operate (cannot be stopped), and funcA, funcC, funcD, funcE, funcF, and funcG do not need to operate ( (can be stopped).

If the test bench 400 specifies a test in verification mode and a verification specification mode (verificationA to verificationG) used for the test, the verification system 200 refers to the second stopability determination table 700. By doing so, it is possible to determine which functional blocks 110 can be stopped in the specified verification specification mode.

(b. An example of the procedure for using each setting information)
Next, a typical procedure for using the function block table 300, test bench 400, stop target table 500, first stop possibility determination table 600, and second stop possibility determination table 700 in the verification system 200 will be described. Note that the procedure for using each table below is an example, and the verification system 200 may refer to each table in any order or concurrently.

First, the verification system 200 refers to the test bench 400 to determine the test contents such as the functional block 110 to be verified, the test mode, and the input signals used for the test.

Next, the verification system 200 refers to the stop target table 500 to determine which functional blocks 110 can be stopped and which functional blocks 110 cannot be stopped. Note that the stoppage information stored in the stoppage target table 500 indicates whether each functional block 110 specified by the user or the system can be stopped. On the other hand, the stoppage information stored in the first stopability determination table 600 and the second stopability determination table 700 determines whether or not it affects the test (the operation of the functional block 110 to be verified). shows.

Next, when the spec mode is selected as the manual mode on the test bench 400, the verification system 200 refers to the first stoppability determination table 600 to identify the function blocks 110 that can be stopped during the spec mode test. Discern. Alternatively, if the verification mode is selected as the manual mode in the test bench 400, the verification system 200 refers to the second stopability determination table 700 and determines which functions can be stopped during the test in the verification mode. Block 110 is determined.

Next, the verification system 200 refers to the functional block table 300 and determines the clock signal and reset signal (or clock pin and reset pin) of the functional block 110 that can be stopped during the test in the spec mode or the verification mode. .

By turning off the clock signal and reset signal of each stoppable function block 110, the verification system 200 can stop one or more function blocks 110 that are unnecessary for the test, thereby shortening the test time.

<D. Logic circuit verification process>
Next, an example of an internal processing procedure of the verification system 200 will be described with reference to FIGS. 8 to 10. In one aspect, the processor 201 may load a program for performing the processes shown in FIGS. 8 to 10 from the storage 203 into the memory 202, and execute the program. In other aspects, part or all of each process may be realized as a combination of circuit elements configured to perform each process.

FIG. 8 is a diagram illustrating an example of a procedure for verifying a logic circuit (semiconductor) by the verification system 200.

In step S805, the verification system 200 reads the verification target circuit data. As an example, the verification target circuit data is code written in a hardware description language. In one aspect, the verification system 200 may acquire verification target circuit data via the external device IF 204, the input IF 205, or the communication IF 207. Alternatively, the verification system 200 may refer to verification target circuit data stored in the storage 203.

In step S810, the verification system 200 reads the test bench 400. As an example, the verification system 200 may read the test bench 400 stored in the storage 203 into the memory 202 and refer to it.

In step S815, the verification system 200 refers to the test bench 400 and determines whether the high-speed test function is ON or OFF. The high-speed test function is a function that stops functional blocks 110 that do not affect the operation of the functional blocks 110 to be verified during test execution. More specifically, the verification system 200 determines that the high-speed test function is OFF when the control mode item 402 is the high-speed control OFF mode. If the high-speed test function is ON, the verification system 200 moves control to step S825. If the high-speed test function is OFF, the verification system 200 moves control to step S820.

In step S820, the verification system 200 operates all functional blocks 110 to perform a test (simulation). Taking FIG. 1 as an example, the verification system 200 operates all the functional blocks 110 from funcA to funcG to test funcA, which is the functional block 110 to be verified.

In step S825, the verification system 200 executes extraction processing of the clock and reset signals of each functional block 110. Details of step S825 will be explained with reference to FIG. 9. The verification system 200 generates or refers to the functional block table 300 by executing the process of step S825.

In step S830, the verification system 200 refers to the test bench 400 and determines whether the control mode is manual mode (MANUAL) or automatic mode (AUTO). More specifically, verification system 200 determines that the control mode is manual mode when control mode item 402 is MANUAL. Furthermore, when the control mode item 402 is AUTO, the verification system 200 determines that the control mode is the auto mode. If the verification system 200 determines that the control mode is the manual mode, the verification system 200 moves control to step S835. When the verification system 200 determines that the control mode is the auto mode (that is, when the control mode is set not to use the stopability determination table), the verification system 200 moves control to step S850.

In step S835, the verification system 200 selects a table to be used for speed-up control in manual mode. More specifically, the verification system 200 selects the first stopability determination table 600 based on the fact that the manual mode setting item 403 is spec mode (SPEC). Furthermore, the verification system 200 selects the second stopability determination table 700 based on the fact that the manual mode setting item 403 is verification mode (VERIFICATION). When the verification system 200 selects the first stoppage determination table 600, the control moves to step S840. When the verification system 200 selects the second stoppability determination table 700, the verification system 200 moves control to step S845.

In step S840, the verification system 200 executes a spec mode test based on the function block table 300 and the first stopability determination table 600. More specifically, verification system 200 executes the test while stopping clock signals and reset signals to one or more functional blocks 110 that do not affect the operation of functional block 110 to be verified.

Taking the example of executing a specA test on funcA of the semiconductor 100, the verification system 200 refers to the specA column of the first stopability determination table 600 and determines whether funcB, funcD, and funcE can be stopped. It is determined that there is. Next, the verification system 200 refers to the function block table 300 and obtains information on the funcB, funcD, and funcE clock pins and reset pins. The verification system 200 stops the operations of funcB, funcD, and funcE based on the acquired clock pin and reset pin information.

In step S845, the verification system 200 executes a verification mode test based on the function block table 300 and the second stopability determination table 700. More specifically, verification system 200 executes the test while stopping clock signals and reset signals to one or more functional blocks 110 that do not affect the operation of functional block 110 to be verified.

Taking the example of executing the verificationA test on funcA of the semiconductor 100, the verification system 200 refers to the verificationA column of the second stopability determination table 700, and tests funcB, funcC, funcD, funcE, funcF. , determines that funcG can be stopped. Next, the verification system 200 refers to the function block table 300 and obtains information on the clock pins and reset pins of funcB, funcC, funcD, funcE, funcF, and funcG. The verification system 200 stops the operations of funcB, funcC, funcD, funcE, funcF, and funcG based on the acquired clock pin and reset pin information.

In step S850, the verification system 200 executes trial processing. The trial process is a process of automatically determining which functional blocks 110 can be stopped based on the results of a test using the test bench 400. Details of the trial process will be explained with reference to FIG. 10. By executing the process of step S850, the verification system 200 can acquire information on the stoppable functional blocks 110 and save the information in the trial result file 1400. Verification system 200 may use the previously generated trial results file 1400 when running the test based on test bench 400 again. In one aspect, the verification system 200 may store information about the stoppable functional blocks 110 in the first stoppability determination table 600 or the second stoppability determination table 700.

In step S855, the verification system 200 executes an auto mode test based on the function block table 300 and the trial result file 1400. More specifically, verification system 200 executes the test while stopping clock signals and reset signals to one or more functional blocks 110 that do not affect the operation of functional block 110 to be verified.

It is assumed that the verification system 200 stores information about the stoppable functional blocks 110 in the first stoppability determination table 600 or the second stoppability determination table 700 in step S850. In this case, the verification system 200 may refer to the first stopability determination table 600 or the second stopability determination table 700 in step S855.

FIG. 9 is a diagram illustrating an example of a procedure for extracting the clock and reset signals of each functional block 110. The process in FIG. 9 is executed as a subroutine of step S825.

In step S910, the verification system 200 reads the functional block table 300. The verification system 200 can read the functional block table 300 from the storage 203 to the memory 202 and refer to the functional block table 300.

In step S920, the verification system 200 determines whether the clock signal and reset signal have been stored in the functional block table 300. If the verification system 200 determines that the clock signal and reset signal have been stored in the functional block table 300 (YES in step S920), the verification system 200 ends the process and returns the control to the next step along with the data stored in the functional block table 300. Return to S825. Otherwise (NO in step S920), verification system 200 moves control to step S930.

In step S930, the verification system 200 extracts the clock signal. More specifically, the verification system 200 analyzes the verification target circuit data acquired in step S805, and obtains information on the clock signal (clock pin) of one functional block 110 defined in the verification target circuit data. Extract. For example, the verification system 200 can extract information about the clock signal (clock pin) of the functional block 110 from the verification target circuit data using the procedure described with reference to FIG. 2 .

In step S940, the verification system 200 extracts a reset signal. More specifically, the verification system 200 analyzes the verification target circuit data acquired in step S805, and obtains information on a reset signal (reset pin) of a certain functional block 110 defined in the verification target circuit data. Extract. For example, the verification system 200 can extract information about the reset signal (reset pin) of the functional block 110 from the verification target circuit data using the procedure described with reference to FIG. 2 .

In step S950, the verification system 200 determines whether the processes of step S930 and step S940 have been repeated for all the functional blocks 110. If the verification system 200 determines that the processes of steps S930 and S940 have been repeated for all functional blocks 110 (YES in step S950), control is transferred to step S960. Otherwise (NO in step S950), verification system 200 moves control to step S930.

In one aspect, the verification system 200 may collectively extract information on clock signals (clock pins) of all functional blocks 110 defined in the verification target circuit data in step S930. Similarly, in step S940, the verification system 200 may extract information on reset signals (reset pins) of all functional blocks 110 defined in the verification target circuit data at once. In this case, the process of step S950 may not be executed.

In step S960, the verification system 200 stores information on the clock signal (clock pin) and reset signal (reset pin) of each functional block 110 in the functional block table 300. Additionally, the verification system 200 returns control to step S825 together with the data stored in the function block table 300.

FIG. 10 is a diagram illustrating an example of the procedure of trial processing. The process in FIG. 10 is executed as a subroutine of step S850.

In step S1005, the verification system 200 determines whether the trial result file 1400 exists. As an example, the verification system 200 may store the past trial result file 1400 in the storage 203. In this case, the verification system 200 can refer to the storage 203 and determine whether there is a trial result file 1400 that can be used in the current test bench 400. If the verification system 200 determines that the trial result file 1400 exists (YES in step S1005), the verification system 200 moves control to step S1010. Otherwise (NO in step S1005), verification system 200 moves control to step S1015.

In step S1010, the verification system 200 reuses the past trial result file 1400 and executes the test. The verification system 200 leaves test execution logs in the memory 202 or storage 203.

In one aspect, the verification system 200 may receive an operation to edit the past trial result file 1400 from the user. For example, when a user adds a new function to an existing circuit, by modifying a part of the past trial result file 1400 (such as changing whether or not some function blocks 110 can be stopped), the user can modify the past trial processing. The results can be used for this test.

In another aspect, when the verification system 200 stores the trial result in the first stoppability determination table 600 or the second stoppability determination table 700, the verification system 200 stores the trial results in the first stoppability determination table 600 or the second stoppability determination table 600 The information included in the stoppage determination table 700 may be used as the past trial result file 1400.

In step S1015, the verification system 200 executes the test without using the past trial result file 1400. As an example, the verification system 200 may execute the test in the acceleration control OFF mode.

In step S1020, the verification system 200 refers to the execution log to confirm and list changes in the input signals of all functional blocks 110. As an example, the verification system 200 generates a list 1300 (see FIG. 13). The list 1300 shows changes in the input signals of all the functional blocks 110 included in the semiconductor to be verified. Taking the semiconductor 100 as an example, the list 1300 includes information on changes in each of the input signals of funcA to funcG.

In step S1025, the verification system 200 checks the change in the input signal of the functional block 110 to be verified by referring to the list 1300 or by referring to the execution log.

In step S1030, the verification system 200 determines whether there is a change in the input signal of the functional block 110 (for example, funcA) to be verified. When the verification system 200 determines that there is a change in the input signal of the functional block 110 to be verified (YES in step S1030), the verification system 200 moves control to step S1035. Otherwise (NO in step S1030), verification system 200 moves control to step S1050.

In step S1035, the verification system 200 determines whether a signal (input signal or output signal) of a certain functional block 110 affects the operation of the functional block 110 to be verified. As an example, verification system 200 selects one of the signals (or wires 120 carrying the signal) from list 1300 that is changing. Then, the verification system 200 determines whether the selected signal affects the operation of the functional block 110 to be verified.

The verification system 200 identifies the selected signal as the functional block to be verified by referring to the line containing the selected signal and the output signal of the functional block 110 to be verified from the execution log of the trial process. It may be determined whether the operation of 110 is affected. Taking the semiconductor 100 as an example, the verification system 200 can determine that the output signal of funcC affects the operation of funcA (the functional block 110 to be verified).

When the verification system 200 determines that the signal of a certain functional block 110 affects the operation of the functional block 110 to be verified (YES in step S1035), the verification system 200 moves control to step S1040. Otherwise (NO in step S1035), verification system 200 moves control to step S1050.

In step S1040, the verification system 200 adds the function block 110 (a certain function block 110 in step S1035) to the unstoppable list.

In step S1045, the verification system 200 determines whether there is a signal that causes a change in the output signal of the functional block 110 registered in the unstoppable list in step S1040. For example, suppose that the output signal of funcC influences the operation of funcA (the output signal of funcA). In this case, the verification system 200 determines whether the input signal (upstream signal) to funcC affects the operation of funcC. The verification system 200 can make this determination by referring to the execution log of the trial process.

If the verification system 200 determines that there is a signal that causes a change in the output signal of the functional block 110 added to the unstoppable list in step S1040 (YES in step S1045), the verification system 200 moves control to step S1040. Otherwise (NO in step S1045), verification system 200 moves control to step S1050.

For example, assume that the output signal of the functional block 110 upstream of funcC affects the operation of funcC. In this case, the output signal of the upstream functional block 110 will indirectly affect the operation of funcA (the output signal of funcA). Therefore, the verification system 200 adds not only funcC but also the upstream functional block 110 to the unstoppable list.

In step S1050, the verification system 200 determines whether the processes from step S1030 onward have been executed for the number of changing input signals (in the functional block 110 to be verified). That is, the verification system 200 determines whether all signals that affect the operation (output signals) of the functional block 110 to be verified have been detected. If the verification system 200 determines that the processes from step S1030 onwards have been executed for the number of input signals that are changing (in the functional block 110 to be verified) (YES in step S1050), control is transferred to step S1055. . Otherwise (NO in step S1050), verification system 200 moves control to step S1030.

In step S1055, the verification system 200 stores the results of the trial process in the trial result file 1400 (stoppability determination table). In one aspect, the verification system 200 may store the results of the trial process in the first stopability determination table 600 or the second stopability determination table 700.

<E. Trial processing>
Next, a method for determining whether each functional block 110 can be stopped in trial processing, and a list 1300 and trial result file 1400 generated during trial processing will be described.

FIG. 11 is a diagram showing an example of the results of trial processing. In the example of FIG. 11, as a result of the trial process, the verification system 200 determines that funcB, funcD, and funcE can be stopped in the test of funcA. Broadly speaking, there are two types of functional blocks 110 that can be stopped.

The first is a functional block 110 that does not affect the operation of the functional block 110 to be verified. In the example of FIG. 11, funcB corresponds to a functional block 110 that does not affect the operation of the functional block 110 (funcA) to be verified. Although the output signal of funcB (the input signal to funcA) may change, the output signal of funcB does not affect the operation of funcA.

The second is a functional block 110 whose output signal does not change. In the example of FIG. 11, funcD corresponds to the functional block 110 whose output signal does not change. Although the output signal of funcD (the input signal to funcA) may change, the output signal of funcD does not affect the operation of funcA.

Further, it is also possible to stop functional blocks 110 (such as funcE) located upstream of the functional block 110 that does not affect the operation of the functional block 110 (funcA) to be verified, such as funcB and funcD.

FIG. 12 is a diagram illustrating an example of criteria for determining whether an input signal affects the functional block 110. There are three types of signals input to the functional block 110 (funcA) to be verified:

signals

1201, 1202, and 1203.

The signal 1201 is a signal that does not change (the signal is always fixed at 0 (LOW) or 1 (HIGH)). Signal 1201 does not affect the operation of functional block 110 to be verified. Therefore, the verification system 200 determines that the functional block 110 that outputs the signal 1201 can be stopped. For example, funcD in FIG. 11 corresponds to the functional block 110 that outputs the signal 1201.

The signal 1202 is a signal that may change but does not affect the operation of the functional block 110 to be verified. For example, a signal that is not used inside the functional block 110 to be verified corresponds to the signal 1202. Signal 1202 also does not affect the operation of functional block 110 under verification. Therefore, the verification system 200 determines that the functional block 110 that outputs the signal 1202 can be stopped. For example, funcB in FIG. 11 corresponds to the functional block 110 that outputs the signal 1202.

The signal 1203 is a signal that changes and is used inside the functional block 110 to be verified (a signal that affects the operation of the functional block 110 to be verified). Therefore, the verification system 200 determines that the functional block 110 that outputs the signal 1203 cannot be stopped. For example, funcC, funcF, and funcG in FIG. 11 correspond to the functional block 110 that outputs the signal 1203.

FIG. 13 is a diagram illustrating an example of a list 1300 indicating the presence or absence of changes in the input signals of all the functional blocks 110 included in the semiconductor to be verified. The verification system 200 creates a list 1300 from the execution log of the trial process. Taking the semiconductor 100 as an example, the verification system 200 allocates an identifier to each input signal of all the functional blocks 110 (funcA to funcG), and creates a list 1300 containing the identifier and the presence or absence of a state change of each input signal. to be recorded.

Each signal recorded in the list 1300 is given a uniquely identifiable identifier such as signal 1, signal 2. Further, in the list 1300, information indicating the presence or absence of a change in each signal is recorded in association with the identifier of each signal. As an example, signal 1 is YES (signal change). Further, signal 2 is NO (no signal change (fixed at 0)). Further, signal 3 is NO (no signal change (fixed at 1)).

FIG. 14 is a diagram showing an example of a trial result file 1400. The trial result file 1400 stores information indicating whether each functional block 110 can be stopped during test execution. More specifically, the trial result file 1400 stores information indicating whether each functional block 110 can be stopped in a test based on the test bench 400 referred to in the trial process. For example, assume that the test bench 400 includes settings for spec mode (specA). In this case, the trial result file 1400 stores information indicating whether each functional block 110 can be stopped in the spec mode (specA) test. In the example of FIG. 14, funcA, funcC, funcF, and funcG are ON (cannot be stopped), and funcB, funcD, and funcE are OFF (can be stopped).

In a certain aspect, the verification system 200 executes a test based on all test benches 400 (specA to specG, verificationA to verificationG, etc.) that have been input in advance to the verification system 200 in trial processing, and supports all test benches 400. A trial result file 1400 may be generated. Verification system 200 may use trial results file 1400 when re-running tests based on test bench 400. Verification system 200 may reuse trial results file 1400 when executing tests based on other test benches 400. At this time, the verification system 200 can accept editing of the trial result file 1400 from the user.

As explained above, the verification system 200 according to the present embodiment automatically determines whether each functional block 110 can be stopped during test execution by analyzing the design specifications, analyzing the verification specifications, or performing trial processing. can be determined. Thereby, the verification system 200 can speed up the test by stopping the functional blocks 110 that are unnecessary for the test.

Furthermore, even if the user executing the test has insufficient knowledge about the semiconductor 100 (logic circuit), he or she can easily speed up the test by using trial processing. Alternatively, the user who executes the test can have the verification system 200 analyze various specifications prepared in advance by a designer or a person in charge of verification, without requiring any knowledge of the semiconductor 100 (logic circuit). You can easily speed up testing.

Additionally, the verification system 200 provides the user with a function to reuse the past trial result file 1400 for a new test. This allows the user to immediately speed up the test if there is a usable trial result file 1400. Furthermore, when there is a design change of the semiconductor 100, the user can also rewrite and use a part of the past trial result file 1400.

The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and it is intended that all changes are included within the meaning and scope equivalent to the claims. Furthermore, the disclosures described in the embodiments and each modification are intended to be implemented alone or in combination to the extent possible.

100 semiconductor, 110 functional block, 120 wiring, 200 verification system, 201 processor, 202 memory, 203 storage, 204 external device IF, 205 input IF, 206 output IF, 207 communication IF, 208 internal bus, 210 simulator, 211 Signal extraction Part, 212 Test bench acquisition part, 213 Stoppability judgment part, 214 Test execution part, 220 Code, 300 Function block table, 301, 501, 601, 701 Function block name item, 302 Module name item, 303 Clock pin item, 304 Reset pin item, 400, 400A test bench, 401 Verification target item, 402 Control mode item, 403, 502 Manual mode setting item, 404 Spec mode setting item, 405 Verification mode item, 500 Stop target table, 503 Auto Mode setting item, 600 First stopability determination table, 610 Design specification mode item, 700 Second stopability determination table, 710 Verification specification mode item, 900 Information processing device, 1201, 1202, 1203 Signal, 1300 List, 1400 Trial result file.

Claims

A method for verifying a logic circuit, the method comprising:
extracting a clock signal and a reset signal input to each of a plurality of functional blocks included in the logic circuit;
a step that references the testbench;
Referring to a stopability determination table that stores information indicating whether each of the plurality of functional blocks can be stopped in a test using the test bench;
The clock signal and the reset signal to one or more of the functional blocks that do not affect the operation of the functional block to be verified are stopped according to the information obtained from the stopability determination table, and the clock signal and the reset signal are stopped based on the test bench. and executing a test of the functional block to be verified.
The stopability determination table includes a first stopability determination table that stores information indicating whether each of the plurality of functional blocks can be stopped, which is determined based on design specifications of the logic circuit;
The verification method is
reading a design specification for the logic circuit;
extracting mutual connection relationships of each of the plurality of functional blocks described in the design specification;
The verification method according to claim 1, further comprising: updating the first stoppage determination table based on the connection relationship.
The stopability determination table includes a second stoppage determination table that stores information indicating whether or not each of the plurality of functional blocks can be stopped, which is determined based on the verification specifications of the logic circuit;
The verification method is
reading a verification specification for the logic circuit;
extracting from the verification specification a description of one or more of the functional blocks to be verified in each of a plurality of tests;
The verification method according to claim 1, further comprising: updating the second stoppage determination table based on the description.
executing a test that uses all of the plurality of functional blocks based on the fact that the test bench is set not to use the stopability determination table;
extracting the plurality of functional blocks that do not affect the operation of the functional block to be verified based on the execution result of a test using all of the plurality of functional blocks;
2. The verification method according to claim 1, further comprising the step of newly storing the plurality of functional blocks that do not affect the operation of the functional block to be verified in the stoppage determination table.
a step of referring to information newly registered in the stopability determination table when executing the test bench again or when executing another test bench;
stopping the clock signal and the reset signal to some of the plurality of functional blocks based on information newly registered in the stopability determination table;
5. The verification method according to claim 4, further comprising: executing a test based on the other test bench.
When executing the other test bench, the method further includes the step of, after referring to the information newly stored in the stopability determination table, accepting an operation to change the information newly stored in the stopability determination table; The verification method according to claim 5.
A program for causing a computer to execute the method according to any one of claims 1 to 6.
A storage storing the program according to claim 7;
A verification system comprising: a processor for executing the program.