JP2001154977A - Data processor and data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve data transfer efficiency in a device capable of executing a continuous data input/output operation like a page access mode. SOLUTION: A data processor 1 is provided with a data transfer controller 3 having a dual-address mode. The controller 3 is provided with a data buffer circuit which has a plurality stage of buffers 10 and a counter 11 and by which a data is inputted/outputted by a FIFO system concerning a data bus (IDB) in response to the counting operation of the counter. Since the data buffer circuit is provided with the plurality stage of buffers, the data is continuously read from a transfer source address with the number of buffer stages as an upper limit and stored in the data buffer circuit in the dual-address mode and the stored data is continuously written in a transfer destination address. The alternate execution of reading and writing is not required in the dual-address mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to direct memory access (DMA) control, and relates to continuous access or block data access of a synchronous memory in a data processor having a DMA controller and a data processing system having a synchronous memory. Alternatively, the present invention relates to DMA control applicable to pipeline burst access.

[0002]

2. Description of the Related Art A conventional data transfer controller such as a conventional DMA controller has only one data buffer, and when transferring a plurality of data, reads data from a transfer source address and temporarily stores the data in a data buffer. Then, the next data could not be read unless the data was written to the transfer destination address.

A memory device such as a DRAM (Dynamic Random Access Memory) which is generally used at present has a page access mode in which data can be accessed at high speed by continuous access. There are many. In the page access mode, when data is first read, data existing on the same page (on the same word line) as the data is latched in a sense amplifier, thereby speeding up the next data reading in the same page. Mode. Initial data access is called initial access, and high-speed access within the same page is called page access.

[0004] Further, with the speeding up of microcomputers, there has been an increasing demand for using a synchronous DRAM which can access data in synchronization with a clock. The synchronous DRAM transfers addresses and data in synchronization with a clock. Synchronous DR
When reading data from an AM, there is a time lag between input of an address and output of data, and this time lag is called latency. Usually, the latency of the synchronous DRAM is a value of 2 to 3 clocks. The synchronous DRAM has a pipeline burst mode. For example, when a read command is continuously input, the data read by the first read command must wait for the number of cycles corresponding to the latency, but the read data by the subsequent command is successive. Data reading is performed continuously and in a pipeline manner as a whole. That is, in the pipeline burst mode, a read address is received every clock, and processing is performed in a pipeline manner internally, so that data can be output one after another after the number of clock cycles corresponding to the latency has elapsed. This is the operation mode.

The DMA controller is disclosed in, for example, CMO published by Nikkan Kogyo Shimbun (September 29, 1987).
It is described in pages 809-812 of the S Device Handbook.

[0006]

However, in a method of alternately performing reading and writing as in a conventional data transfer controller, generally, a reading address and a writing address are not in the same page. Even when using memory with access mode,
The present inventor has revealed that there is a problem that the page cannot be accessed.

Further, in the conventional data transfer controller that alternately performs reading and writing, the operation cannot proceed to the writing operation unless the data reading is completed. Therefore, every time the reading and the writing are alternately performed, the clock cycle of the latency is always required. The inventor of the present invention has to wait for the progress, and cannot fully utilize the performance of the memory having the pipeline burst mode, and the data transfer speed is reduced. Revealed.

An object of the present invention is to provide a data processor and a data processing system capable of improving data transfer efficiency for a device capable of continuous data input / output operation such as a page access mode or a pipeline burst mode. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] The data processor includes a data transfer controller having a dual address mode for reading data from a transfer source address via a data bus and writing the read data from the data bus to a transfer destination address. The data transfer controller has a data buffer circuit and a transfer control circuit. The data buffer circuit has a plurality of stages of buffers and a counter.
Data can be input / output in advance format. In the dual address mode, the transfer control circuit repeats data reading from the transfer source address a plurality of times and stores the data in the data buffer circuit, and sequentially writes the data stored in the data buffer circuit to the transfer destination address a plurality of times. Address control is possible.

Since the data buffer circuit has a plurality of buffers, in the dual address mode, data is continuously read from the source address and stored in the data buffer circuit with the number of buffer stages being the upper limit, and the stored data is continuously stored. Writing to the transfer destination address is possible. In other words, reading and writing do not have to be performed alternately in the dual address mode. Therefore, high-speed dual address transfer using a page mode can be realized for a page accessible memory. The performance of the memory having the pipeline burst mode can be sufficiently utilized. As a result, it is possible to contribute to improvement of data transfer speed and efficiency of data processing.

[2] The data transfer controller includes:
A control register for programmably specifying the number of buffers used in the data buffer circuit is further provided, and the counter is caused to perform a counting operation with the number specified by the control register as a count-up value, and The address output operation of data read and the address output operation of data write are repeated continuously for the number of times corresponding to the number specified by the control register. As a result, it is easy to increase the degree of freedom in performing the data transfer control by setting the number of continuous accesses in the page mode or the number of continuous accesses in the pipeline burst mode in a programmable manner.

[3] The data processor is connected to the internal bus to which the data transfer controller is coupled, a central processing unit connected to the internal bus and capable of setting transfer control conditions by the data transfer controller, and connected to the internal bus. A bus controller that controls a bus outside the data processor. The bus controller is responsive to the data transfer control by the data transfer controller and outputs a first control signal to the data transfer controller to notify the data transfer controller of the decision on the internal bus of the data to be read from the outside.

The first control signal is transferred between the data transfer control controller and the external memory due to a difference in operation timing (operation speed) between the data buffer circuit and the data transfer target or a difference in bus width between the internal and external buses. A situation in which the timing is shifted can be easily adjusted.

[4] The data transfer controller causes the bus controller to output a second control signal indicating continuous access. The bus controller outputs the second control signal during a continuous access instruction of the second control signal from the data transfer controller. The access instruction command may be continuously output while the access address is sequentially incremented so that the external access is continued.

Thus, when the memory to be transferred by the data transfer controller can perform the pipeline burst operation, the bus controller having a memory interface for the purpose can easily bear the address generation and the command output of the pipeline burst operation. it can. Then, the number of bursts, which is the number of continuous accesses in the pipeline burst operation, and the number of stages of the buffer in the data buffer circuit can be easily matched.

[5] The synchronous memory can perform a pipeline burst access operation in response to a command given from the data processor. In a data processing system including a synchronous memory and a data processor operated in synchronization with a synchronous clock signal of the data processor, the address generation of the pipeline burst operation is performed by the bus controller as described above and output to the synchronous memory. Alternatively, it may be performed by the data transfer controller and the bus controller may output to the synchronous memory.

[0019]

FIG. 1 shows an example of a data processor according to the present invention. Although not particularly limited, the data processor 1 shown in FIG. 1 is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon by a CMOS integrated circuit manufacturing technique or the like.

The data processor 1 includes, but is not limited to, a central processing unit (CP) connected to the internal bus 6.
U) 2, Data transfer controller (DMAC) 3, RO
It has an internal memory 4 such as M (read only memory) or RAM, and the internal bus 6 can be interfaced to an external bus 7 by a bus controller 5. The data processor 1 receives a clock signal (operation reference clock signal) C
LK is operated synchronously.

The external bus 7 includes an external address bus EAB, an external data bus EDB, and an external control bus ECB.
including. For example, a page accessible D
The RAM 8 is connected.

The internal bus 6 has an internal data bus IDB,
Internal address bus IAB and internal control bus I
Includes CB. The internal control bus ICB is
And the size information of the data to be accessed from DMAC3,
An access strobe signal such as a read signal indicating data input, a write signal indicating data output, and a signal indicating continuous access are included.

The internal data bus and the external data bus may have the same or different bus width. The difference in the access mode due to the difference between the two bus widths is caused by the bus controller 5
Controls.

The bus controller 5 determines whether the information of the access data size and the access speed of the device mapped for each address area is
The PU is initialized by the PU and controls the bus of the external bus (output of device address, data access size, insertion of wait state, etc.) according to the area of the address supplied from the internal address bus. The bus controller 5 has a D
In response to the data transfer control by the MAC 3, the wait signal WAIT as the first control signal for notifying the DMAC 3 of the decision on the internal bus 6 of the data to be read from the outside is output to the D.
Output to MAC3. The wait signal WAIT indicates a difference in operation timing (operation speed) between the data buffer circuit 10 and the data transfer target memory or the internal bus 6 and the external bus 7.
Is used for optimizing the timing of data transfer between the DMAC 3 and the DRAM 8 according to the difference in the bus width of the DMAC.

The DMAC 3 includes a buffer register 10, a counter 11, a transfer control channel 12, and a control logic circuit 1.
3. It has a control register 14. Buffer register 10
Has a plurality of stages, for example, eight stages of buffers BUF0 to BUF7. The buffer register 10 constitutes a data buffer circuit (also simply referred to as the data buffer circuits 10 and 11) together with the counter 11, and transfers data to the internal data bus IDB in a first-in first-out manner in response to the counting operation of the counter 11. Input / output is possible. The counter 11 has, for example, a number of bits corresponding to the number of stages of the buffer of the buffer register 10. For example, when the number of stages of the buffer constituting the buffer register 10 is eight, the counter 11 has 3 bits.
Is a bit. A signal obtained by decoding the output of the counter 11 may be used for selecting the buffers BUF0 to BUF7.

The control register 14 is made accessible by the CPU 2. For example, control information for determining how many buffers of the buffer register 10 are used is set, and the set value is given to the control logic circuit 13. The set value of the control register 14 also specifies the number of times of continuous reading or continuous writing to be described later.

The data transfer control channel 12 includes a source address register (not shown) for specifying a transfer source address (source address), a destination address register for specifying a transfer destination address (destination address), and the number of words to be transferred. , A transfer word number register, and an address adder.
Source address specified by the source address register,
The update of the destination address instructed by the destination address register is generated by adding the count value of the counter 11 to the immediately preceding source address (or destination address) by the adder. The data transfer control channel 12 and the control logic circuit 13 constitute a transfer control circuit.

Although not particularly limited, the control logic circuit 13 is provided with a state transition control format according to a transfer request, a set value of the control register 14, a state of the wait signal WAIT, and the like.
A logical configuration for controlling the data transfer operation of AC13,
Schematically, input / output control for the buffer register 10, count control of the counter 11, and read / write control for the transfer control channel are performed. This control logic circuit 13
Has a dual address mode in which data is read from a source address and the read data is written to a destination address. In the input / output control by the control logic circuit 13, when the transfer control channel 12 performs a read operation, the buffer register 10 is operated to perform an input operation,
When the transfer control channel 12 performs a write operation, the buffer register 10 performs an output operation. In the counting control, the counter 11 is operated as a counter of the number of bits according to the number of used buffer stages designated by the control register 14. In the read / write control, the transfer control channel 1
2 generates an address and an access strobe for read or write access in response to a data transfer request.

The transfer control channel 12 and the control logic circuit 13 store data in the buffer register 10 by repeating data read from a source address a plurality of times in a dual address mode in order to correspond to the page mode of the DRAM 8. Address control for repeatedly writing data stored in the buffer register 10 to a destination address a plurality of times is possible. In addition, the control logic 13 may have a single address mode in which either the source or the destination is an input / output circuit that does not require addressing. However, since this is not particularly related to the present invention, a detailed description will be given. Description is omitted.

FIG. 2 illustrates a state transition diagram of the data transfer control in the dual address mode in the control logic circuit 13.

The DMAC 3 is waiting for a transfer request in a waiting loop 22 of the idle state 21. When the transfer request 23 arrives, the state transits to the read state 24, and gives a read operation instruction 25 to the bus controller 5. Since the number of states required for read access is controlled by the bus controller 5, the wait signal WAI from the bus controller 5
While receiving T, it waits in the wait loop 27 of the read wait state 26.

In the dual address mode, when the use of a plurality of stages of buffer registers 10 is specified by the set value of register 14, data buffer circuits 10, 1
Therefore, when the wait signal WAIT from the bus controller 5 is negated (released) in the read wait state 26, the transition 28 is performed again to the read state 24. Control register 14
Are completed, the transition 29 to the write state 30 is performed. In a conventional DMAC having no data buffer circuits 10 and 11, a transition is made to the write state as soon as the wait signal from the bus controller is released. The feature of the read control by providing the data buffer circuit is the control of the repetitive transition 28 for the read state.

Upon transition to the write state 30, a data write instruction 31 is given to the bus controller 5. Since the number of states required for the write access is controlled by the bus controller 5, while receiving the wait signal WAIT from the bus controller 5, the controller waits in the wait loop 33 of the write wait state 32. In the dual address mode, when the use of a plurality of stages of the buffer register 10 is specified by the set value of the register 14, continuous writing is performed using the data buffer circuits 10 and 11. When the signal WAIT is negated (released), the transition 34 to the write state 30 is performed again. When the continuous writing of the number of times specified in advance in the control register 14 is completed, a transition 35 to the idle state 21 is performed. In the conventional DMAC having no data buffer circuit, the state transitions to the idle state as soon as the wait signal from the bus controller is released. The feature of the write control by providing the data buffer circuits 10 and 11 is the control of the repetitive transition 34 for the write state.

FIG. 3 shows an example of the transfer control operation timing between the page accessible memories. In the example of FIG. 3, the DRAM 8 is used as a page accessible memory.
Requires four states (r0, W0) at the time of initial access and two states (r1 to r3, w1 to w3) at the time of page access, and the control register 14 is set to use four buffer stages. Shall be. The internal data bus IDB and the external data bus EDB are both 8 bits.

In the state display of FIG. 3, Is indicates an idle state, Rs indicates a read state, Rw indicates a read wait state, Ws indicates a write state, and Ww indicates a write wait state.

In FIG. 3, the first read cycle r0
Starts with the read state (Rs), and while the wait signal WAIT output from the bus controller 5 is active (high level), the bus cycle is extended by the read wait cycle Rw to secure a 4-state read cycle. The source address is a value sa + 1, sa + 2, sa + 3 obtained by sequentially adding the counter output from the reference point sa.

Second to fourth read cycles r1 to r3
Are accessible in two states for continuous reading to the same page. Therefore, the wait signal WAIT output from the bus controller 5 becomes active only for a shorter period than in the first read cycle r0.

The counter 11 counts up in each bus cycle, and the 8-bit data (Data [7: 0]) d0 to d3 read out to the external data bus EDB are stored in the counter 11 in the data buffer circuit 10 respectively. The data is temporarily stored in the buffers BUF0 to BUF3 at the indicated positions.

When the number of readings corresponding to the number of used buffer stages specified by the control register 14 has been completed, writing is performed next. Generally, a source address (sa) and
Since the transfer destination address (da) is not the same page, the first write cycle (w0) is an initial access, and
State required. Also, in this write cycle,
The value of the counter 11 is reset, and is counted up from 0 every time writing occurs. The destination address is a value da + 1, da + 2, da + 3 obtained by sequentially adding up the counter output from da as a base point.

Data to be written is sequentially read from the buffers BUF0 to BUF3 indicated by the counter 11, and output to the data bus EDB.

As can be seen from the operation timing of FIG. 3, the DMAC 3 can perform page access between the data read cycle indicated by r1, r2, and r3 and the data write cycle indicated by w1, w2, and w3. Has improved throughput. When a conventional data transfer controller having only one data buffer is used, reading from the source address and writing to the destination address are performed by r0, w0, r1, w1, r2, and w.
Since the access occurs alternately as in r2, r3, and w3, all accesses are initial accesses, and the page access function of the DRAM 8 cannot be utilized.

FIG. 4 shows a case where the bus width of the internal data bus IDB is 16 bits (the data size of the buffers BUF0 to BUF7 is also 16 bits) and the bus width of the external data bus EDB is 8 bits. 2 indicates the operation timing in the case of performing transfer between page accessible memories.

DMAC 3 to bus controller 5 16
A bit data read cycle r0 is required. D
The source address output from the MAC 3 to the internal address bus IAB is sa. At this time, the external data bus EDB
Since the bus width is 8 bits, the bus controller 5 asserts the wait signal WAIT to the DMAC 3 and, in the meantime, performs an external bus access of 8 bits in the cycle r.
This is executed twice by 0a and r0b to determine 16-bit data on the internal data bus IDB (iData [7: 0]). In this operation, the source address output from the bus controller 5 to the external address bus EAB is sa, sa
+1. Note that the second read cycle r1 is also the first read cycle r1.
In the same manner as in the read cycle, the bus controller 5 performs 8-bit access to the source address sa + 2 output from the DMAC 3 using the source addresses sa + 2 and sa + 3.

In the first write cycle w0, the DMAC
3 to the bus controller 3 with 16-bit data (d
0, d1). The destination address output from the DMAC 3 to the internal address bus IAB is da. At this time, the external data bus ED
Since the bus width of B is 8 bits, the bus controller 5
Asserts a wait signal WAIT to DMAC3, during which an 8-bit external bus access is performed in cycle w
0a, w0b, and the internal data bus I
The 16-bit data output by the DMAC 3 is written to the external memory in the DB. In this operation, the destination addresses output from the bus controller 5 to the external address bus EAB are da and da + 1. The second write cycle w1 is the same as the first write cycle w0,
Destination address da + 2 output by C3
Bus controller 5 performs 8-bit access using da + 2 and da + 3 as destination addresses.

As is apparent from the operation timing of FIG. 4, when the bit width of the external data bus EDB is smaller than the number of bits of data requested by the DMAC 3, the bus controller 5 executes data transfer a plurality of times. , DMAC
DMA when data of the number of bits required by
Data can be passed to C3.

In the case of the operation of FIG. 4, the data access (r0b, r0b,
1b, w0b, w1b) are page accessible even when using a conventional data transfer controller having only one stage of data buffer. However, when the conventional data transfer controller is used, reading from the source address and writing to the destination address are performed by r0a, r0b, w0a, w0b, r1a, r1
1b, w1a, and w1b alternately occur, so that the first access (r0a, w0a, r1a,
w1a) is an initial access, and the page access function of the memory cannot be utilized. In contrast, DMA
In C3, access after the second access (r1a, w1
a) is page accessible and can improve the data transfer rate.

FIG. 5 shows another data processor 1A assuming use of SDRAM 8A having a pipeline burst mode.

The SDRAM 8A includes a bus controller 5A
The operation is instructed by a command applied to the external control bus ECB, and the memory operation is performed in synchronization with the operation reference clock signal CLK of the data processor 1A.

The bus controller 5A of FIG. 5 is an SDRAM
A counter 40 and an address generator 41 are provided corresponding to the 8A pipeline burst operation. Address generator 41 receives an address signal supplied from internal address bus IAB at the time of pipeline burst operation, adds the output of counter 40, and adds external address bus EAB.
Output to AB is possible. DMAC3A is SDRAM8
When A performs a pipeline burst operation to perform data transfer control, the bus controller 5A outputs a continuous access instruction signal CONS as a second control signal indicating continuous access. As a result, the counter 40 performs a counting operation for each operation cycle during a continuous access instruction by the continuous access instruction signal CONS.
1 adds the count value to an access address supplied from the DMAC 3A via the internal address bus IAB to generate a continuous access address. The bus controller 5A further continuously outputs an access instruction command in synchronization with the generation of the continuous access address. Thus, the bus controller 5A can perform continuous access to the SDRAM 8A in response to the access instruction from the DMAC 3A. The wait signal WAIT is asserted at a high level until data is read out to the external data bus EDB.

As described above, when the memory 8A to be transferred by the DMAC 3A can perform a pipeline burst operation, the bus controller 5A having a memory interface therefor can easily bear the address generation and command output of the pipeline burst operation. it can. At this time, the number of bursts, which is the number of continuous accesses in the pipeline burst operation, and the number of data buffer circuits 10 and 11 are determined by the continuous access instruction signal CONS.
Can be matched with the number of stages in which the buffer is used.

FIG. 6 illustrates a state transition diagram of the data transfer control in the dual address mode by the control logic circuit 13A corresponding to the pipeline burst operation.

The DMAC 3A waits for a transfer request in the waiting loop 52 of the idle state 51. Transfer request 53
, A transition is made to the initial read state 54 to instruct the bus controller 5A to perform a data read operation. Since the number of states required for read access is controlled by the bus controller 5A, it waits in the initial read state wait loop 55 while receiving the wait signal WAIT from the bus controller 5A.

When the wait signal WAIT from the bus controller 5A becomes inactive, a transition is made to the read state 56 for continuously reading data, and continuous reading 57 is performed by the number of data buffer stages specified by the control register 14. .

When the data reading is completed, the state transits to a write state 58 for continuously writing data.
Continuous writing is performed 59 by the number indicated by the number of data buffer stages in the control register 14. When all the data read into the data buffer 10 has been written, a transition 60 is made to the idle state 52 to wait for the next transfer request.

FIG. 7 shows an example of operation timing when data transfer is performed by operating the SDRAM in a pipeline burst operation.

Here, it is assumed that the number of used buffer stages of the buffer register 10 is set to four. SD via external address bus EAB and external command bus ECB
When an access address and a command are supplied to the RAM 8A, the SDRAM 8A takes in the address and the command at the rise of the synchronous clock signal CLK of the SDRAM 8A, and the SDRAM 8A outputs data to the external data bus EDB two clock cycles later. The time difference from the address and command input to the data output is called a latency. Here, the latency of the SDRAM 8A is 2
Becomes If the latency is 3 or 4, it may be dealt with by changing the length of the wait signal WAIT from the bus controller 5A. The symbols R, W, and Nop shown as commands in FIG. 7 represent commands to the SDRAM 8A that are read, write, and no operation, respectively.

The SDRAM 8A operates in the read cycle (r
0 to r3), the external address bus EAB has sa,
Addresses that are successively incremented, such as sa + 1, sa + 2, and sa + 3, must be output. During this time, the source address A on the internal address bus IAB output from the DMAC 3A to the bus controller 5A is:
The bus controller 5A outputs the sum of the source address on the internal address bus IAB and the output of the counter 40 to the SDRAM via the external address bus EAB.
Output to 8A.

The counter 40 counts up in response to the high level of the continuous address transfer signal CONS from the DMAC 3A.

The bus controller 5A outputs a wait signal WA to the DMAC 3A from the first output of the address (sa) to the external address bus EAB until the corresponding data d0 is obtained on the external data bus EDB.
The IT is activated to wait for the DMAC 3A to start operating. When the wait signal WAIT becomes inactive, the state of the DMAC 3A transitions to the read state Rs, and at the same time, the counter 11 starts counting. In the read state Rs, the read data is temporarily stored in the data buffers BUF <b> 0 to BUF <b> 3 sequentially indicated by the counter 11.

When the data reading of the number of times corresponding to the number of used buffer stages indicated by the control register 14 is completed, the DMA
The status of C3A transits to the write state Ws.
At the time of data writing, the SDRAM 8A simultaneously takes in an address on the external address bus EAB, a command on the external command bus, and write data on the external data bus EDB to perform a write operation. Like the read operation, the write operation is performed by the DMAC 3A from the internal address bus IA.
The transfer destination address output to B is a fixed value da,
The outputs of the counter 40B counted up by the continuous address transfer signal CONS are sequentially added, and da,
It is supplied to the external address bus EAB as a continuous write address such as da + 1, da + 2, da + 3.

The counter 11 in the DMAC 3A is reset to 0 once in the write state Ws, starts counting up again, and writes data d0, d1, d2 from the data buffers BUF0 to BUF3 selected by the output of the counter 11. , D3 are output.

FIG. 8 shows still another data processor 1B assuming use of an SDRAM 8A having a pipeline burst mode. The data processor 1B shown in the figure has the functions of the counter 40 and the address generator 41 incorporated in the DMAC 3B.
The function of the address generator 41 is transfer control channel 1
2B. Considering that the bus interface generally has a memory interface function such as a command output to the SDRAM 8A, the configuration of FIG. 5 is provided to the bus controller 5A having the memory interface for the pipeline burst operation as described above. Although the address generation and the command output for the operation can be easily burdened, in the case of FIG. 8, the DMAC must have the address generation for the pipeline burst operation separated from the command generation.
The other configuration is the same as that of FIG. 5, and a detailed description thereof will be omitted.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the above description does not describe a case where a continuous address is generated by a memory device built-in address counter as a memory device that supports the page mode or the pipeline burst mode. It is needless to say that the present invention is also applicable to a case where such a memory device is a data transfer target. For example, in a synchronous DRAM, a start address is externally received, a continuous address is generated by a built-in column address counter, and when the number of continuous data accesses is designated by the number of bursts, when performing data transfer by burst access, The number of used buffer stages of the register 14 may be set in consideration of the number of bursts set in the SDRAM. In a more specific mode, when the number of bursts is 4, when the number of stages of use of the buffer is set to 4 in the register 14, when the source address is output once, data of an address continuous from the source address as a base point for 4 memory cycles. The read data is output from the SDRAM, and read data is sequentially accumulated in a total of four buffers. When writing read data, the destination address is output once,
If the data output operation is sequentially performed four times in synchronization with the memory cycle from the buffer in synchronization with this, the data is sequentially written into four consecutive addresses starting from the destination address.

The built-in module of the data processor is not limited to the above description, and may include a floating point unit, a timer, and other input / output circuits.

The data processor is not limited to a single semiconductor integrated circuit, but may be a semiconductor integrated circuit mixed with a large capacity DRAM or the like.

[0067]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the data buffer circuit has a plurality of buffers, in the dual address mode, data is continuously read from the transfer source address and stored in the data buffer circuit, and the stored data is continuously stored, with the number of buffer stages as an upper limit. Can be written to the transfer destination address. In the dual address mode, reading and writing do not have to be performed alternately. Therefore, high-speed dual address transfer using a page mode can be realized for a page accessible memory. The performance of the memory having the pipeline burst mode can be fully utilized. As a result, it is possible to contribute to the improvement of the data transfer speed and the efficiency of data processing.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a data processor according to the present invention.

FIG. 2 is a state transition diagram of data transfer control in a dual address mode in a control logic circuit included in the data processor of FIG. 1;

FIG. 3 is a timing chart illustrating an example of a transfer control operation between page-accessible memories.

FIG. 4 illustrates a case where the number of used buffer stages is set to 2 and transfer between page-accessible memories is performed when the bus width of the internal data bus is 16 bits and the bus width of the external data bus is 8 bits. 6 is a timing chart illustrating an operation.

FIG. 5 SDRA with pipeline burst mode
FIG. 10 is a block diagram of another data processor assuming use of M.

FIG. 6 is a state transition diagram of data transfer control in a dual address mode by a control logic circuit included in the data processor of FIG. 5;

FIG. 7 is a timing chart illustrating an operation when performing data transfer by performing an SDRAM in a pipeline burst operation.

FIG. 8: SDRA with pipeline burst mode
FIG. 10 is a block diagram showing still another data processor assuming use of M.

[Explanation of symbols]

 1, 1A, 1B Data processor 2 CPU 3, 3A, 3B DMAC 5, 5A Bus controller 6 Internal bus 7 External bus 8 DRAM 8A SDRAM 11 Counter 12, 12A, 12B Transfer control channel 13, 13A, 13B Control logic circuit 14 Control Register WAIT Wait signal CONS Continuous access instruction signal 40 Counter 41 Address generator

Continuing from the front page (72) Inventor Tatsuro Nishino 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B061 DD06 DD09 DD12 GG05 RR03 RR05

Claims (5)

[Claims] 1. A data processor comprising: a data transfer controller having a dual address mode for reading data from a transfer source address via a data bus and writing the read data from the data bus to a transfer destination address; The transfer controller includes a data buffer circuit having a plurality of stages of buffers and a counter and capable of inputting and outputting data in a first-in first-out manner to a data bus in response to the counting operation of the counter. A transfer control circuit capable of performing an address control in which data read from the original address is repeated a plurality of times and stored in the data buffer circuit, and the data stored in the data buffer circuit is sequentially and repeatedly written to the transfer destination address a plurality of times; Data characterized by comprising Processor. 2. The data transfer controller further includes a control register for programmably specifying the number of buffers used in the data buffer circuit, and the counter counts the number specified by the control register as a count-up value. The transfer control circuit repeats a data read address output operation and a data write address output operation continuously for a number of times corresponding to the number specified by the control register. Data processor as described. 3. An internal bus to which the data transfer controller is coupled is connected to a central processing unit capable of setting transfer control conditions by the data transfer controller, and a bus controller for performing bus control on the outside of the data processor. The controller is responsive to the data transfer control by the data transfer controller, and outputs a first control signal to the data transfer controller to notify the data transfer controller of the determination on the internal bus of the data to be read from the outside. 3. The data processor according to claim 2, wherein: 4. The data transfer controller outputs a second control signal indicating continuous access to a bus controller, and the bus controller transmits an access address from the data transfer controller during a continuous access instruction of the second control signal. 4. The data processor according to claim 3, wherein the access instruction command is continuously output while sequentially incrementing, and the external access is continued. 5. A data processor according to claim 3 or 4, an external bus connected to a bus controller of said data processor, and connected to said external bus and operated in synchronization with a synchronous clock signal of said data processor. A data processing system comprising: a synchronous memory; wherein the synchronous memory is capable of performing a pipeline burst access operation in response to a command given from a data processor.