JP2001154975A - Dma transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify an operation for setting timing data and data length data for DMA transfer by a CPU. SOLUTION: Ports 1 and 2 are assumed to exist. Before a data is DMA- transferred at a first time between the port 1 and the data buffer RAM3, information to designate the port 1 and the values of timing data and data length data for DAM transfer to the port 1 are transmitted from the CPU 1 to a DMA control part 4a as a DMA control signal. The DMA control part 4a selects a port 1 setting register 71 via a setting register selecting part 6a based on the DMA control signal and sets and holds timing data and data length data in it. When data is DMA-transferred between the port 1 and a data buffer RAM 3, set timing data and data length data are read from the register 71 and used for DAM transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer control device for controlling a DMA transfer.

[0002]

2. Description of the Related Art In recent years, CPUs incorporating a direct memory access controller (DMAC) have been manufactured and sold. The DMA transfer control device uses DACK (DM
A data transfer between an external device with an A transfer end notification), an external memory, a memory-mapped external device, and a built-in peripheral module is performed at high speed in place of the CPU, thereby reducing the load on the CPU and increasing the operation efficiency of the CPU. is there. To start a DMA transfer, the CPU
The timing and data length in the A transfer are set.

[0003]

SUMMARY OF THE INVENTION However, DMA
In a DMA transfer control system having two or more ports for performing a transfer, a set value such as timing data and data length data required for performing a DMA transfer is set to D.
The setting must be made every time the MA transfer is performed. Even when the DMA transfer of different ports is performed alternately, the timing data and the data length data must be set each time, so that the setting becomes redundant. Also, DMA
Even if there is only one transfer port, if there are a plurality of data transfer timings and data lengths, it is necessary to set timing data and data length data each time.

[0004] An object of the present invention is to solve such a problem, and to provide the same timing and the same data length for the same port.
An object of the present invention is to provide a DMA transfer control device which can omit setting of timing data and data length data when performing MA transfer.

[0005]

In order to achieve the above object, the present invention provides a holding means for holding a set value for each set value of timing data and data length data related to DMA transfer, and performs a DMA transfer. When performing, a desired one of these holding units is designated, and the DMA transfer is controlled using the set value held in the designated holding unit.

With this configuration, once the above-mentioned set value is held in the holding means, as long as the set value is held, D
This set value can be used at the time of MA transfer, and external setting is not required.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of a DMA transfer control device according to the present invention, wherein 1 is a CPU having a built-in DMAC, 2 is a DMA transfer control device of the first embodiment, and 3 is a DMA transfer. Data buffer RAM, 4a DMA controller, 5a control signal generator, 6a setting register selector, 71 ₁ port 1 setting register, 72 ₂ port 2 setting register, 8a
Is a data selection unit.

In FIG. 1, the D in the first embodiment forms a DMA control system together with the CPU 1.
MA transfer control device 2, DMA transfers data buffer RAM 3, DMA control unit 4a, setting register selection unit 6a, the port 1 setting register _71, which is configured by a Port 2 setting register 7 ₂ and the data selecting section 8a, D
The control signal generator 5a is built in the MA control unit 4a. This DMA control system has two ports, port 1 and port 2,
Port 1 setting register 7 ₁ the value of the timing data 1 and data length data 1 for port 1, port 2 setting register 7 ₂ the value of the timing data 2 and data length data 2 for the port 2 respectively held.

Next, the function of each block in FIG. 1 will be described.

(1) DMA transfer data buffer RAM3
Function: Stores transfer data in DMA transfer, DM
The transfer data is transmitted / received to / from the DMA control unit 4a in response to a request from the A control unit 4a.

(2) Function of DMA control section 4a: The transfer data is extracted from the DMA control signal sent from the CPU 1 and sent to the DMA transfer data buffer RAM3. DMA from the DMA control signal sent from CPU 1
Information of a port to be transferred, and timing data 1 and data length data 1 when a DMA transfer is performed at port 1
Alternatively, a setting signal including the timing data 2 and the data length data 2 for performing the DMA transfer at the port 2 is generated and sent to the setting register selecting unit 6a. A port 1 address signal and a port 2 address signal are generated based on the DMA control signal sent from the CPU 1,
Send to ports 1 and 2. Transfer data for DMA transfer is fetched from the DMA transfer data buffer RAM 3 and sent to ports 1 and 2 as a port 1 data signal and a port 2 data signal, respectively. A port 1 selection signal and a port 2 selection signal are generated based on the DMA control signal sent from the CPU 1 and sent to the data selection unit 8a. A setting signal relating to the DMA transfer is set to a setting register selecting section 6
a and sends it to the control signal generator 5a. A port 1 control signal and a port 2 control signal, which are output signals of the control signal generator 5a, are sent to ports 1 and 2, respectively. The data signal sent from the data selector 8a is stored in the temporary DMA transfer data buffer RAM3,
Of the DMA transfer data buffer RAM 3 in response to the request of
Send to U1.

(3) Function of control signal generator 5a: A port 1 control signal and a port 2 control signal are generated based on a setting signal taken into the DMA controller 4a from the setting register selector 6a. , 2.

(4) Function of setting register selecting section 6a: receives the above setting signal sent from DMA control section 4a, generates a port 1 setting signal including timing data 1 and data length data 1, and sets port 1 Register 7
Send to ₁ . Upon receiving the setting signal sent from the DMA control unit 4a, a port 2 setting signal including timing data 2 and data length data 2 is generated, and the port 2 setting register 7
Send to ₂ . Port receive port 1 setting signal including the timing data 1 and data length data 1 from 1 setting register 7 _1. Receive port 2 setting signal including the timing data 2 and data length data 2 from the port 2 setting register 7 _2. A setting signal including timing data 1 and data length data 1 or timing data 2 and data length data 2 is generated, and a control signal generator 5a in the DMA control unit 4a is generated.
Send to

[0014] (5) Port 1 setting register 7 ₁ features:
The timing data 1 and the data length data 1 are extracted and held from the port 1 setting signal sent from the setting register selecting unit 6a, and the timing data 1 and the data length data 1 are converted according to a request from the setting register selecting unit 6a. It is sent to the setting register selector 6a.

[0015] (6) Port 2 setting register 7 ₂ features:
Be the same as the port 1 setting register _71, and held from the port 2 setting signal sent from the setting register selection unit 6a fetches the timing data 2 and data length data 2, also request setting register selection unit 6a Sends the timing data 2 and the data length data 2 to the setting register selecting section 6a.

(7) Function of data selector 8a: port 1 select signal and port 2 transmitted from DMA controller 4a
Using the selection signal, one of the port 1 data signal received from the port 1 and the port 2 data signal received from the port 2 is selected, and the selected data signal is transmitted to the DMA controller 4.
Output to a.

Next, the operation of the first embodiment will be described.

First, the CPU 1 sends selection information indicating whether to perform the DMA transfer at the port 1 or the DMA transfer at the port 2 to the D in the DMA transfer control device 2.
Send to MA control unit 4a. As these ports 1 and 2,
For example, PCMCIA or IDE is used.

When the first DMA transfer is performed at the port 1 after the power is turned on, the CPU 1 sends a DMA control signal including timing data 1 and data length data 1 to the port 1 to the DMA control unit 4a in the DMA transfer control device 2. The DMA control unit 4a generates a setting signal including information indicating a port for performing a DMA transfer, timing data 1 and data length data 1 based on the DMA control signal, and sends the generated setting signal to the setting register selecting unit 6a. Setting register selection unit 6a sends the setting signal as a port 1 set signal to the port 1 setting register 7 _1, the port 1 setting register _71, the timing data 1 and the data length data 1 included in the port 1 setting signal And hold.

When the first DMA transfer is performed at port 2 after the power is turned on, the same as the case of port 1 described above,
Port 2 setting register 7 timing data 2 to the port 2 to ₂ and data length data 2 is held.

[0021] Next, the case of transferring data from CPU1 in on port 1 setting register 7 ₁ set of timing data 1 and data length data 1 as described above is performed to port 1.

The CPU 1 outputs information (port selection information) for selecting a port for performing the DMA transfer, information indicating the data transfer direction, and a signal for instructing the start of the DMA transfer.
The data is sent to the DMA control unit 4a in the MA transfer control device 2, and the transfer data is sequentially sent to the DMA control unit 4a. This transfer data is temporarily stored in the DMA transfer data buffer RAM 3 as a port 1 data signal. Next, the DMA control unit 4a sends to the setting register selection unit 6a information on port selection for performing DMA transfer, which is included in the DMA control signal sent from the CPU 1. Setting register selection unit 6a selects the port 1 Configuration Register 7 ₁ using port 1 setting signal based on this information, the timing data 1 is held in the port 1 Configuration Register 7 ₁ according to the above procedure and data length data 1 Capture
It is sent to the control signal generator 5a in the DMA control unit 4a. Therefore, the control signal generator 5a generates a port 1 control signal based on the timing data 1 and the data length data 1 sent from the setting register selector 6a, and stores the port 1 control signal in the DMA transfer data buffer RAM 3 as a port 1 data signal. The data is transferred to port 1 together with the stored transfer data and the port 1 address signal generated by the DMA controller 4a.

Next, the case of transferring data from the port 1 on the port 1 setting register 7 ₁ set of timing data 1 and data length data 1 as described above is performed to CPU 1.

The CPU 1 sends the port selection information of the DMA transfer, the information indicating the data transfer direction, and the signal instructing the start of the DMA transfer to the D
Send to MA control unit 4a. The DMA control unit 4 a
The information of the port performing the A transfer is set in the setting register selecting section 6a.
Send to Setting register selecting unit 6a, the timing data 1 and data length data 1 is held in the port 1 setting register 7 ₁ using port 1 setting signal based on this information capturing, the control signal generation of the DMA control unit 4a To the vessel 5a. Therefore, the control signal generator 5a generates a port 1 control signal based on the timing data 1 and the data length data 1 sent from the setting register selector 6a,
This port 1 control signal is transferred to port 1 together with the port 1 address signal generated by the DMA controller 4a. Thereafter, the transfer data is transferred from the port 1 to the data selection unit 8a of the DMA transfer control device 2 as a port 1 data signal. The data selection unit 8a
Using the port 1 selection signal sent from the MA control unit 4a, the transfer source port of the transfer data (in this case, port 1)
And the port 1 data signal is transmitted to the DMA controller 4a.
Send to Therefore, the DMA control unit 4a sets the data selection unit 8
a is temporarily stored in the DMA transfer data buffer RAM3, and when the CPU 1 receives a transfer data read request, the DMA transfer data buffer RA3.
This transfer data is read from M3 and transferred to CPU1.

The above description relates to port 1,
Regard port 2, when performing CPU1 DMA transfer from the port 2 on the port 2 setting register 7 ₂ setting timing data 2 and data length data 2 as described above has been performed, from the above CPU1 D to port 1
As in the case of performing the MA transfer, the transfer data from the CPU 1 is temporarily stored in the DMA transfer data buffer RAM 3 as a port 2 data signal, and the setting register selection unit 6a in the DMA transfer control device 2 sets the port 2 setting register 7 _The timing data 2 and the data length data 2 held in ₂ are taken in as a port 2 setting signal and sent to a control signal generator 5a in the DMA control unit 4a. Therefore, the control signal generator 5a generates a port 2 control signal based on the setting signal sent from the setting register selector 6a, and outputs the port 2 address signal and the port 2 data signal read from the DMA transfer data buffer RAM3. And to port 2.

Further, in the case of DMA transfer from the port 2 to the CPU1 in on port 2 setting register 7 ₂ setting timing data 2 and data length data 2 as described above has been performed, the above port 1 To CPU1 DM
In the same manner as in the case of the A transfer setting register selection unit 6a of the DMA transfer control device 2 captures timing data 2 and data length data 2 Port 2 setting register 7 in ₂ as ports 2 setting signal, DMA controller 4a to the control signal generator 5a. Therefore, the control signal generator 5a generates a port 2 control signal based on the setting signal sent from the setting register selecting unit 6a, and transfers it to the port 2 together with the port 2 address signal. Thereafter, the transfer data is transferred from the port 2 to the data selection unit 8a as a port 2 data signal. The data selection unit 8a is connected to the port 2 transmitted from the DMA control unit 4a.
The port of the transfer data source is identified using the selection signal (in this case, port 2), and this data signal is transmitted to the DMA control unit 4a.
Send to The DMA controller 4a converts the data signal sent from the data selector 8a into a DMA transfer data buffer RA.
The data is temporarily stored in M3, and when a transfer data read request is issued from the CPU 1 through the DMA control signal, the DMA
The transfer data is read from the transfer data buffer RAM 3 and transferred to the CPU 1.

As described above, in the first embodiment,
A register for holding timing data and data length data for each port for performing the DMA transfer; for each port, at the time of the first DMA transfer after power-on, the timing data of the port for performing the first DMA transfer; Since the data and data length data are set in the register corresponding to this port, the timing data and data length data once set are valid in the second and subsequent DMA transfers, and have the same timing and the same data length as the first DMA transfer. When the DMA transfer is performed, the setting of the timing data and the data length data can be omitted.

When the timing data and the data length data are made different during the DMA transfer with the same port, new timing data and data length data for the DMA transfer are required prior to the DMA transfer. Is set again in the port setting register by the CPU 1. However, in the first embodiment, the timing data and the data length data already set in the port setting register can be used as long as there is no request for changing the timing data and the data length data. Therefore, the setting of the timing data and the data length data by the CPU 1 can be omitted.

FIG. 2 is a block diagram showing a second embodiment of the DMA transfer control device according to the present invention.
b is a DMA control unit, 5b is a control signal generator, 6b is a setting register selection unit, _7n is a port n setting register, 8b is a data selection unit, and the parts corresponding to those in FIG. The description of the operation will be omitted.

In the second embodiment, the number of ports for DMA transfer is n (where n is an integer of 3 or more).

In FIG. 2, the DMA control unit 4b
Performs the same operation as that of the DMA control unit 4a,
DMA extracted from the DMA control signal sent from 1
The point that information, timing data and data length data of a port to be transferred are supported for n ports, the address signal and the data signal to be output to each of n ports are provided for n ports, and output to the data selection unit 8b The difference from the DMA control unit 4a in FIG. 1 is that a selection signal for n ports is provided and that a control signal is transmitted from the control signal generator 5b in the DMA control unit 4b to n ports.

The setting register selecting section 6b operates in the same manner as the setting register selecting section 6a in FIG. 1 except that the registers to be selected are the port 1 setting register 7 ₁ , the port 2 setting register 7 ₂ ,. n setting registers 7 _n and n registers from the port 1 setting signal
It differs from the setting register selection unit 6a in FIG. 1 in that it has n signals up to the setting signal.

The port n setting register 7 _i (where i =
1, 2,..., N) are the same as the port 1 setting register 7 ₁ and the port 2 setting register 7 ₂ in FIG. 1, and extract the timing data i and the data length data i from the port i setting signal for the port i. The data is taken out and held, and the data is read and sent to the setting register selecting section 6b.

The control signal generator 5b operates similarly to the control signal generator 5a in FIG.
.., A port 1 control signal, a port 2 control signal for each n,.
.., Is different from the control signal generator 5a shown in FIG. 1 in that n control signals of port n control signals are generated and output.

The data selector 8b operates in the same manner as the data selector 8a in FIG.
..,..., Port n selection signals sent from the DMA control unit 4b, and transmitted to the DMA control unit 4b using the n selection signals of the port n selection signals. The difference from the data selection unit 8a in FIG. 1 is that a signal is selected.

In the second embodiment, the number of ports for performing DMA transfer is set to two of ports 1 and 2 in the first embodiment.
What was pieces, expanded to n ports 1 to n, the timing data relating to DMA transfers with it, a register for holding the data length data, the port 1 setting register 7 ₁ and the port in the first embodiment what was 2 two setting register 7 ₂ are those extended to n, and as described above, DMA controller 4b, setting register selector 6
b, the control signal generator 5b and the data selector 8b also differ from the first embodiment in accordance with the expansion of the number of ports.
The functions related to the MA transfer are the same as in the first embodiment.

After the power is turned on, as with the first embodiment, the timing data and the data length data set at the time of the first DMA transfer are equal to 2 for any of the ports.
The DMA transfer is effective for the second and subsequent DMA transfers, and when DMA transfer with the same timing and the same data length as the first DMA transfer is performed, the setting of timing data and data length data can be omitted.

Also, in the second embodiment, as in the first embodiment, the DM between the same port is set.
When the timing data and the data length data are made different at the time of the A transfer, it is not possible to reset new timing data and data length data for the DMA transfer in the port setting register by the CPU 1 prior to the DMA transfer. Needless to say. However, also in the second embodiment, the timing data and the data length data already set in the port setting register can be used unless there is a request for changing the timing data and the data length data. Therefore, the setting of the timing data and the data length data by the CPU 1 can be omitted.

FIG. 3 is a block diagram showing a third embodiment of the DMA transfer control device according to the present invention.
c is DMA controller, 5c control signal generator, 6c is set register selection _{unit, 7 11, 7 12, ......} , 7 1m port 1
The same reference numerals are given to portions corresponding to those shown in FIG. 1 and description thereof is omitted.

In the third embodiment, at least one port has m pieces of timing data and data length data. Here, it is assumed that there is one port, and this is port 1.

Referring to FIG. 3, the third embodiment operates in the same manner as the first embodiment shown in FIG. 1, except that the port for performing the DMA transfer is different from the first embodiment. One point, that is, a point having only port 1.

The DMA control unit 4c operates in the same manner as the DMA control unit 4a in FIG. 1, except that the timing data and the data length data for DMA transfer extracted from the DMA control signal sent from the CPU 1 are of m types. The point of support, the point of having an address signal and a data signal to be output to one port 1, and the point of only sending the control signal which is the output signal of the control signal generator 5c to one port 1, This is different from the DMA control unit 4a in FIG.

The setting register selecting section 6c operates in the same manner as the setting register selecting section 6a in FIG. 1, except that the number of registers to be selected is m and the number of port 1 setting signals is m in FIG. Is different from the setting register selecting section 6a.

The control signal generator 5c operates in the same manner as the control signal generator 5a in FIG. 1 except that a control signal of only the port 1 control signal is generated and output to the port 1 in FIG. It is different from the control signal generator 5a.

Next, the operation of the third embodiment different from that of the first embodiment shown in FIG. 1 will be described.

In the third embodiment, the number of ports for performing DMA transfer is changed from two ports of port 1 and port 2 in the first embodiment to one port of only port 1.
A register for holding the timing data and data length data regarding DMA transfer to port 1, what was one of the ports 1 setting register 7 ₁ in the first embodiment, the port 1 setting register 7 _11, 7 _12, ... ..., 7 _1m of m
And holds m types of timing data and data length data. In addition, the data selection unit 8a used in the first embodiment is eliminated.
The control section 4c, the setting register selection section 6c, and the control signal generator 5c also differ from the first embodiment shown in FIG. 1 according to the difference in the number of ports.

In the first embodiment shown in FIG.
Although the CPU 1 supplies the port selection information for the DMA transfer to the DMA control unit 4a, in the third embodiment, information indicating the value of the timing data for performing the DMA transfer and the type of the data length data is sent to the DMA control unit 4c. Things,
According to this information, the port 1 setting registers 7 ₁₁ , 7 ₁₂ ,.
, _71m holds or reads out the timing data and data length data. D other than the above
Functions related to MA transfer are the same as in the first embodiment.

When a plurality of ports are provided in the third embodiment, a plurality of port setting registers are provided for each port, and different types of timing data and data length data are stored for each port. And a data selection unit 8b shown in FIG. 2 is provided.

In the third embodiment, the timing data and the data length data set in the first DMA transfer after the power is turned on are also effective in the second and subsequent DMA transfers. When DMA transfer with the same timing and the same data length is performed, the setting of the timing data and the data length data can be omitted as in the previous embodiments. But it is the same.

FIG. 4 is a block diagram showing a fourth embodiment of the DMA transfer control device according to the present invention.
d is DMA controller, 5d control signal generator, 6d setting register selection unit, 7 _11, 7 ₁₂ a port 1 setting register, a redundant description with the same reference numerals corresponding to FIG. 3 Omitted.

In the fourth embodiment, at least one port setting register stores predetermined timing data and data length data values. In this embodiment, one port 1 is provided. as shown in FIG. 4, the port 1 to the two ports 1 setting register 7 _11, 7 ₁₂ is provided, in which different values of the timing data and data length data respectively are set in advance. The overall schematic configuration is the same as that of the third embodiment shown in FIG. 3 when m = 2.

In FIG. 4, the DMA control unit 4d
Performs the same operation as the DMA control unit 4c in
3 does not include the timing data and the data length data in the DMA transfer in the DMA control signal sent from the CPU 1, and therefore, the timing data and the data length data are not set by the CPU 1 prior to the DMA transfer in FIG. Unlike the DMA control unit 4c, the signals for selecting the timing data 1 and the data length data 1 or the timing data 2 and the data length data 2
By outputting removed from the control signal to the setting register selection unit 6d, it is from port 1 setting register 7 _11, 7 ₁₂ only reads the timing data 1 and data length data 1 or timing data 2 and data length data 2,.

The setting register selecting section 6d operates in the same manner as the setting register selecting section 6c in FIG. 3 except that the number of registers to be selected is two, and the port 1 setting registers 7 ₁₁ ,
7 without setting the timing data and data length data with respect to _12, the timing data 1 and data length data 1 from the port 1 Configuration Register 7 ₁₁ or port 1,
That from the setting register 7 ₁₂ only retrieve the timing data 2 and data length data 2 is different from the setting register selection unit 6c in FIG.

[0054] Port 1 setting register 7 ₁₁ is set hold timing data 1 and data length data 1 predetermined, new that it does not re-set the timing data 1 and data length data 1 in FIG. 3 port 1 setting register 7 ₁₁ different.

The port 1 setting register 7 ₁₂ is similar to the port 1 setting register 7 _11, and sets and holds predetermined timing data 2 and data length data 2. that it does not reset the data length data 2 is different from the port setting register 7 ₁₁ in FIG.

In the fourth embodiment, the port 1 setting registers 7 ₁₁ and 7 ₁₂ are used as the port 1 setting registers 7 ₁₁ and 7 ₁₂ to hold the timing data and the data length data relating to the DMA transfer for the port 1. As in the third embodiment shown in FIG. 3, when different types of timing data and data length data are used for one port (where m is an integer of 3 or more), FIG. In the case of having a plurality of ports as in the embodiment shown in FIG. 2, further, as in the embodiment shown in FIG. 1 and FIG. When different types of timing data and data length data are used by providing port setting registers for each port, timing data and data length data are set in advance in each port setting register, and C The setting of the timing data and the data length data by the PU1 can be omitted.

[0057]

As described above, according to the present invention,
D of the same data length at the same timing for the same port
When performing MA transfer, at least the second and subsequent DMA
In the transfer, the setting of the timing data and the data length data can be omitted, and the unnecessary operation in the related art of repeating the data setting for each DMA transfer can be eliminated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a DMA transfer control device according to the present invention.

FIG. 2 is a block diagram showing a second embodiment of the DMA transfer control device according to the present invention.

FIG. 3 is a block diagram showing a third embodiment of the DMA transfer control device according to the present invention.

FIG. 4 is a block diagram showing a fourth embodiment of the DMA transfer control device according to the present invention.

[Explanation of symbols]

1 CPU 2 DMA transfer control unit 3 DMA transfer data buffer RAM 4 a to 4 d DMA controller 5a~5d control signal generator 6a~6d setting register selection unit _{7 1 ~7 n, 7 11 ~7} 1m port configuration register 8a~8d Data selection section

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasushi Toki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Digital Media Development Division, Hitachi, Ltd. (72) Inventor Akira Kanehira Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Media, Ltd. Digital Media Development Division F-term (reference) 5B061 DD06 DD11 RR07

Claims (4)

[Claims] 1. A DMA transfer control device for controlling a DMA transfer to a plurality of ports, wherein a set value relating to the DMA transfer can be set from the outside and one holding means for each port is provided for holding the setting value again. And a selection means for selecting one of the holding means based on selection information from the outside, and when the selection information for designating a port for performing the DMA transfer is input, the DMA transfer is performed by the selection means. A DMA transfer control device which selects the holding means corresponding to the port, reads a set value set in the selected holding means, and uses the set value for DMA transfer with the port. 2. The DMA transfer control device according to claim 1, wherein the number of the ports is two. 3. DMA for at least one port
In a DMA transfer control device for controlling the transfer, a plurality of holding means are provided for each port, wherein a set value relating to the DMA transfer can be set from the outside and held until the setting is performed again. Selection means for selecting any one of the holding means based on the selection information, the selection means designating a set value relating to the DMA transfer of the port performing the DMA transfer, and the selection means responding to the selection information A DMA transfer control device for selecting the holding unit, reading a set value set in the selected holding unit, and using the read value for DMA transfer with the port. 4. A DMA transfer control device for controlling a DMA transfer to n (where n is an integer of 1 or more) ports, wherein a means in which a set value relating to the DMA transfer is set and held in advance is set to the n number of said ports. M (where m is an integer equal to or greater than 1) is provided for each, and a selecting means for selecting any one of the holding means based on selection information from the outside is provided, and the DMA transfer of the port performing the DMA transfer is provided. The selection means selects the holding means corresponding to the selection information by inputting the selection information for specifying the setting value related to, and reads the setting value set in the selected holding means to read the port and the port. A DMA transfer control device for use in DMA transfer during the transfer.