JP2001154633A - Plasma display device and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an erase characteristic of a plasma display and to stably operate it. SOLUTION: The number of turn-on cells in a just previous sub-field is detected from a video signal inputted to a display control unit, and this information is sent to an erase pulse storage part. In the erase pulse storage part, the information of plural erase pulse waveforms (voltage, width) are stored beforehand in a storage element, and an optimum erase pulse waveform (voltage, width) is selected based on the number of turn-on cells sent from a number of turn-on cells detection part in succeeding an erase pulse selection part. A prescribed erase pulse is generated in an erase pulse generation part of a display drive pulse generation part based on the erase pulse information to be sent to a drive circuit of a display drive unit, and a display panel is driven by an optimum erase pulse condition.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an AC-driven plasma display device and a control method thereof.

[0002]

2. Description of the Related Art FIG. 5 shows a structural example of an AC-driven plasma display panel (hereinafter, AC-PDP). In the figure, 20 is a front substrate, 21 is an X electrode, 22 is a Y electrode, 23
Is a dielectric layer, 24 is a protective film, 25 is a rear substrate, 26 is a writing electrode (W electrode), 27 is a rib, 28 is a phosphor, and 29 is a discharge space.

When a display discharge is performed in an AC-PDP, a voltage pulse is alternately applied between the sustain electrodes of the X electrode 21 and the Y electrode 22 to generate a discharge in which the polarity is inverted every half cycle, and the display cell is switched. Flash. X electrode 21 and Y electrode 22
Are covered with a dielectric layer 23, and once a discharge occurs between the electrodes of each cell, electrons and ions called wall charges are accumulated on the dielectric layer 23.

When an electric field whose polarity is inverted to that of the previous discharge is applied after the discharge is extinguished, the applied electric field overlaps with the electric field formed by the wall charges. Discharge becomes possible. Thereafter, the discharge can be maintained by inverting the low voltage every half cycle. This is called a memory function. Discharge sustained at a low applied voltage using this memory function is called sustain discharge,
The voltage pulse applied to the X electrode 21 and the Y electrode 22 every half cycle is called a sustain discharge pulse. Eliminating the wall charges is called erasing, and forming the wall charges on the dielectric layer 23 first is called writing.

In an AC-PDP, the display discharge is O
As described above, the presence or absence of wall charges accumulated on the dielectric layer 23 is used to turn off N and OFF. A subfield which is a minimum unit that repeats ON and OFF is divided into three periods. First, a reset period for uniformly aligning wall charges on the dielectric in all cells (such a reset is called all-cell reset), and then writing for accumulating wall charges in a cell to be displayed. And a sustain discharge period in which display discharge is finally performed using wall charges.

After the end of the sustain discharge period and before the start of the reset period, the cells that have undergone the sustain discharge have wall charges, but the cells that have not undergone the sustain discharge have no wall charges, and the display of the immediately preceding subfield is performed. The presence or absence of wall charges differs depending on the non-display cell. The purpose of the reset period is to erase the wall charges remaining in the immediately preceding subfield by discharging and set the wall charges on all the cells to zero.

Here, the type and operation of the wall charge erasing method will be described. FIG. 6 shows the erasable region and the non-erasable region of the wall charge when the pulse width and the voltage value of the erasing pulse shown in Japanese Patent Application Laid-Open No. 10-3281 are changed. Area 1 is an area that can be erased regardless of the discharge history of the previous subfield, area 2 is an area that can be erased according to the discharge history of the previous subfield, and area 3 is only the cells that have been discharged in the previous subfield. Although the discharge is performed using the electric charge, the wall charge is accumulated again by its own discharge. Therefore, in the non-erasable region, the region 4, even when the wall charge of the cell discharged in the previous subfield is used, the discharge is not generated. It is an area that does not occur and cannot be erased.

When the pulse width and the voltage value of the region 1 are applied,
Regardless of the presence or absence of the sustain discharge in the previous subfield, all the cells are forcibly discharged at the rising edge of the pulse. It is possible to eliminate wall charges. The discharge at the falling edge of this pulse is called self-erasing discharge. This erasing method has a priming effect in addition to the effect of erasing wall charges. After the erasing discharge is completed, a small amount of charged particles and excited particles generated in the discharge remain in the discharge space, so that the probability of the next writing discharge is increased, and the discharge is facilitated. In other words, it acts as a pilot for writing discharge. Therefore, this pulse may be called a priming pulse.

In the area 2, only the cells sustained in the immediately preceding subfield can be discharged and erased. In FIG. 6, when the pulse width is the same, for example, the erase pulse width is 0.6 μsec, 120 V to 200 V and 240 V
There are two voltage ranges of ~ 300V. According to the "plasma display" (Kenichi Owaki et al .: Kyoritsu Shuppan, 1983), a method of erasing a low voltage region is called a narrow erase method, and a pulse is called a narrow erase pulse. When a pulse having a voltage and a pulse width in this region is applied, the pulse is interrupted during the progress of the discharge, that is, before the wall charge of the opposite polarity is formed, so that the wall charge is erased.

A method for erasing a high voltage region is disclosed in
3281, when a pulse having a voltage and a pulse width in this region is applied, the cell that has accumulated the wall charge in the immediately preceding subfield at the rise of the pulse is discharged, and the self-charge is generated at the fall of the pulse. Causing an erasing discharge,
Wall charges are erased. This erasing method is called a medium voltage narrow erase method, and the pulse is called a medium voltage narrow erase pulse.

[0011] Several such erasing methods are selected and used taking advantage of their respective merits.

[0012]

When driving is performed using the above-described narrow erase pulse or medium-voltage narrow pulse, the voltage range and width of the erase pulse can be increased as the size of the panel increases. There is a problem that the range (hereinafter, erase voltage margin) is narrow or disappears.

This is because when the cell discharges and current flows,
This is because a voltage drop occurs due to the circuit resistance of the panel and the resistance of the bus electrode, and the effective pulse voltage and pulse width change. When the number of selectively lit cells is large (high area display rate), the discharge current is large, so that the voltage drop is large, and the voltage is applied from the outside. Voltage needs to be increased. Therefore, the erasable area in FIG. 6 shifts to the high voltage side. As described above, since the erasable area depends on the area display ratio, the erase voltage margin covering the entire area display ratio is extremely reduced as compared with the case where the area display ratio is constant.

At a high area display ratio, the voltage drop is large, the discharge delay time of each cell varies, the discharge current waveform becomes wide, and the erase pulse width optimized at a low area display ratio is reduced. However, there is a problem that all the cells to be erased cannot be completely erased.

The present invention has been made in order to solve the above-mentioned problems, and is intended for a large-screen AC-PDP.
It is possible to prevent a reduction in the erase voltage margin due to the influence of the voltage drop and the variation of the discharge delay time, and to achieve stable driving.
An object is to obtain a C-PDP device and a control method thereof.

[0016]

According to the present invention, there is provided a method for controlling an AC-driven plasma display device, which comprises a reset period for erasing a discharge history, an address period for selecting a cell to be displayed, and a luminance. Drive control using a subfield having a discharge sustaining period, the shape of the erase pulse used in this reset period is based on the number of lighting cells detected in the subfield immediately before this reset period, This is selected from the shape data of a plurality of erase pulses.

In the method for controlling an AC-driven plasma display device according to the present invention, the AC-driven plasma display device is formed in the same plane with a plurality of scanning electrodes arranged in parallel and forming pairs with the scanning electrodes. A plurality of sustain electrodes, a plurality of data electrodes opposed to each other so as to intersect with the scan electrodes and the sustain electrodes, and an intersection area between the scan electrodes and the sustain electrodes and the data electrodes. A configuration including a plurality of display cells may be used.

In the method for controlling an AC-driven plasma display device according to the present invention, the shape data of the plurality of erase pulses may be constituted by data having at least one of a voltage value and a pulse width different from each other.

An AC-driven plasma display device according to the present invention includes a reset period for erasing a discharge history,
An AC-driven plasma display device configured to perform drive control using a subfield having an address period for selecting a cell to be displayed and a discharge sustain period for obtaining luminance stores an input video signal. A frame memory, a lighting cell number detection unit for detecting and storing the number of lighting cells in a subfield based on data of the frame memory, and an erasing pulse storage for storing a plurality of shape data of an erasing pulse used in a reset period. And an erasing pulse selecting unit that selects the shape of the erasing pulse in the next subfield from a plurality of shape data of the erasing pulse storage unit based on the number of lit cells detected and stored by the lit cell number detecting unit. And an erase pulse generator for generating an erase pulse based on the output of the erase pulse selector.

An AC-driven plasma display device according to the present invention includes a plurality of scan electrodes arranged in parallel, a plurality of discharge sustaining electrodes paired with the scan electrodes and formed in the same plane, A configuration including a plurality of data electrodes opposed to each other so as to intersect the discharge sustaining electrodes, and a plurality of display cells provided in an intersection area between the scan electrodes and the sustaining electrodes and the data electrodes may be employed. Absent.

In the AC-driven plasma display device according to the present invention, data of a plurality of erase pulses may be different from each other in at least one of a voltage value and a pulse width.

[0022]

Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The panel structure of the plasma display device according to this embodiment is the same as that of the conventional example described with reference to FIG.

FIG. 1 is a block diagram schematically showing an example of the configuration of an AC-PDP according to the present invention.
PDP, 2 is a display control unit, 3 is a display drive unit, 4 is a display panel, 5 is a frame memory, 6 is a display data processing unit, 7 is a lighting cell number detection unit, and 8 is an erase pulse storage including erase pulse data. , 9 is an erase pulse selection unit, 10 is a display drive pulse generation unit including an erase pulse generation unit, 11 and 12 are W drive circuits, 13 is a Y drive circuit, 14
Is an X drive circuit.

In the AC-PDP 1, display data, a video signal such as a vertical synchronizing signal, a horizontal synchronizing signal, and a dot clock are input to the frame memory 5 of the display control unit 2. For example, signal processing unique to the display panel is performed. The data that has been subjected to the signal processing is temporarily stored in the memory in the display data processing unit 6 for each field, divided and read for each subfield in order to perform multi-gradation display, and subjected to predetermined processing. X and Y of the display drive unit 3
W is sent to each drive circuit, and each step of reset, address, and maintenance is executed. At this time, the data for W drive and the data for Y drive are stored in the display data processing unit 6.
After the pulse shape is determined, the pulse is sent to the display drive pulse generator 10 to generate predetermined pulses for W drive and Y drive. The generated W drive pulse and Y drive pulse are sent to the W drive circuits 11, 12 and the Y drive circuit 13 of the display drive unit 3, and are subjected to reset, address, and maintenance processes. On the other hand, the pulse shape of the data for X driving is not determined at the stage when the signal processing is performed in the display data processing unit 6. The pulse shape for X drive is determined according to the following procedure. The data for the X drive, which has been subjected to the signal processing in the display data processing unit 6, is sent to the number-of-lighted-cells detection unit 7, and the data of the number of lighted cells in the immediately preceding subfield is added. Next, the data for the X drive is sent to the erase pulse storage unit 8 including the erase pulse data, and the erase pulse data is added according to the number of cells lit in the immediately preceding subfield. At 9, the pulse shape for X drive is determined. The determined X drive data is sent to the display drive pulse generator 10 including the erase pulse generator, and an X drive pulse including the erase pulse is generated. The X drive pulse thus generated is sent to the X drive circuit 14 of the display drive unit 3, and drives the display panel 4 together with the W drive pulse and the Y drive pulse. The information of the lit cell in this subfield is sent to the lit cell number detection unit 7,
It is used to determine the pulse shape of the X drive data in the subsequent subfield. The above processing is performed for each subfield, and an image is displayed.

FIG. 2 is a timing chart showing voltage waveforms in subfields of the driving sequence. One subfield includes a reset period for erasing a discharge history, an address period for selecting a cell to be displayed, and a sustain discharge period for obtaining luminance. Here, the subfield using the priming pulse described in the conventional example is used as the subfield using the all-cell reset, and the subfield using the narrow erase pulse or the medium-voltage narrow pulse is used as the selected cell. This is shown as a subfield using reset. By repeating several subfields using the all-cell reset and some subfields using the selected cell reset, one field is formed and one image is formed. The voltage waveforms shown in FIG. 2 are sequentially applied from the top to the W electrode 26, the Y electrode 22 (two applied voltage waveforms for the first row and the n-th row are shown in the figure), and the applied voltage of the X electrode 21. It is a waveform. The X electrodes 21 are commonly connected, and the same voltage is applied to all the X electrodes 21. On the other hand, the Y electrode 22 and the W electrode 26 can apply an individual voltage for each line. (See Fig. 5)

In the reset period of the subfield using the all-cell reset, the priming pulse P is applied to the X electrode 21.
When xp is applied, as described in the conventional example, at the rise of the pulse, discharge occurs between the XY electrodes of all cells, and the wall charges are erased.

In the reset period of the subfield using the selected cell reset, when a narrow erase pulse or a medium voltage narrow pulse Pxe is applied to the X electrode 21, a discharge occurs in the previous subfield as described in the conventional example. Then, only the cells in which the wall charges are stored are discharged, and the wall charges are erased.

In the address period, the Y electrodes 22 on the first row to the Y electrodes 2 on the Nth row
2, negative scan pulses Pya are applied in order. On the other hand, a positive address pulse Pwa is applied to the W electrode 26 according to the content of the image data. An arbitrary cell on the screen can be matrix-selected by the scan pulse Pya applied to the Y electrode 22 and the address pulse Pwa applied to the W electrode 26. Since the total voltage value of the scan pulse Pya and the address pulse Pwa is set to be equal to or higher than the discharge start voltage between the Y and W electrodes of the cell, the scan pulse Py
a and the cell to which the address pulse Pwa is simultaneously applied is Y
Discharge occurs between the -W electrodes.

During the address period, the common X electrode 21
Is maintained at a positive voltage value. Although this voltage value does not discharge between the X and Y electrodes even if it is summed with the voltage value of the scan pulse Pya, when a discharge occurs between the Y and W electrodes, this discharge is used as a trigger and at the same time, between the X and Y electrodes. However, the voltage value is set so that discharge occurs. The discharge between the X and Y electrodes that is triggered by the discharge between the Y and W electrodes may be referred to as a write sustain discharge. By this write sustain discharge, wall charges are accumulated in the sustain electrode pair.

After the scanning of the entire screen is completed, the sustain discharge pulses Pys and Pxs are applied to the entire screen all at once, and the sustain discharge is performed only in the cells selected during the address period and accumulating the wall charges. The light emission due to the sustain discharge is used for display, and the cells that emit light by the sustain discharge within one field are illuminated brighter. Thus, reset, write,
An image can be displayed by repeating the sustain discharge.

Next, the characteristics of the erase pulse with respect to the area display ratio and the method of selecting the optimum erase pulse voltage will be described. The optimum voltage value of the erasing pulse for the area display ratio varies depending on the resistance of the panel, the size of the screen, and the discharge current, and is determined in advance by experiment or calculation. For example, FIG. 3 shows the relationship between the display ratio and the voltage drop obtained experimentally for the PDP having the structure shown in FIG. The size of the screen is 40 inches diagonally, the total resistance of the panel including the resistance of the bus electrode and the resistance of the circuit is 100Ω per sustain electrode line, and the width of the sustain electrode is 300 μm. Thus, the area display ratio and the voltage drop value are in a proportional relationship.

A part of FIG. 2 is a schematic diagram of a voltage waveform at the time of erasing discharge of Pxe of a narrow erase pulse or a medium voltage narrow pulse. FIG. 2A shows a case of a low area display rate, and the effective voltage value is almost the same as the applied voltage value because the voltage drop due to the resistance is small. FIG.
(B) shows the case of a high display ratio, in which the voltage drop due to the resistance is large and the effective voltage value is greatly reduced. FIG. 2C illustrates a case where the applied voltage is supplemented from the outside so that the effective voltage value becomes the effective voltage value in the case of the low display rate in the case of the high display rate in FIG. Is shown.

As shown in FIG. 3, the complement of the voltage utilizes the fact that the area display ratio is proportional to the voltage drop value. However, it is not always necessary to make the voltage level analogously variable. There is a sufficient effect even if it is made variable to three types of levels. For example, in the case of a narrow erase pulse, the area display rate is set to the same value as the sustain voltage when the area display rate is 0% to 49%, and the area display rate is 7 when the area display rate is 50% to 100%.
It is set to a value obtained by adding 10 V which is a voltage drop at 5%. The same applies to the case of the selected cell self-erasing pulse.

In this way, referring to the data of FIG. 3, it is determined how much the voltage is to be complemented, and the erase pulse storage unit 8 stores erase pulse data having a plurality of voltage values.

As described above, the AC-PDP control method according to the present invention detects the number of lit cells in a subfield and automatically adjusts the voltage of an erase pulse used in the subsequent subfield based on the number of lit cells. Then, the wall charges are reset. Therefore, it is possible to select an optimal erase pulse voltage value with respect to a voltage drop that increases in proportion to the number of lighting cells, and it is possible to prevent a decrease in an erase voltage margin due to the influence of the voltage drop, thereby realizing stable driving. .

Further, the AC-PDP according to the present invention detects the number of lit cells in a subfield, and automatically adjusts the voltage of an erase pulse used in the subsequent subfield based on the number of lit cells, thereby detecting wall charge. For resetting, it is possible to select the optimal erase pulse voltage value for the voltage drop that increases in proportion to the number of lighting cells,
The drive is stably performed without reducing the erase voltage margin due to the influence of the voltage drop.

Embodiment 2 In Embodiment 2 according to the present invention, Embodiment 1
Similarly to the above, information on some erase pulses is stored in the erase pulse storage unit 8. The erase pulse selector 9 can select an optimum erase pulse width for the number of lighted cells (area display ratio) with respect to the total number of cells in the subfield detected by the lighted cell number detector 7. . FIG. 4 is a schematic diagram of a voltage waveform at the time of erasing discharge of the narrow erasing pulse according to the present invention. FIG. 4A shows a case of a low area display ratio, in which all cells to be erased are discharged. FIG.
(B) shows the case of a high area display rate, and the pulse falls before all the cells to be erased discharge because of a large variation in the discharge delay time among the individual cells. In FIG. 4C, the pulse width is widened so that all the cells to be erased are discharged in the case of a high area display ratio as shown in FIG. In this way, how much the pulse width is complemented with respect to the area display ratio is determined, and the erase pulse having a plurality of widths is stored in the erase pulse storage unit 8.

In the first and second embodiments, the frame memory 5, the display data processing unit 6, and the display drive pulse generating unit 10 are included in the display control unit 2. However, these components are not included in the plasma display device. It is needless to say that the same action is included no matter where it is included.

In the embodiment of the present invention, the description has been made of the three-electrode surface discharge type AC-PDP. However, the present invention is a discharge utilizing wall charges, and includes a reset period for erasing a discharge history, a display period, and a display period. The present invention can be applied to any type of device that performs drive control using a subfield having an address period for selecting a cell to be operated and a sustain period for obtaining luminance, and has two electrodes. However, the present invention is not limited to the three-electrode surface discharge type AC-PDP.

As described above, according to the control methods shown in the first and second embodiments, a wide erasing margin can be secured even in a large-screen panel having a large voltage drop and a large variation in discharge delay time.

[0041]

As described above, by using the AC-PDP control method according to the present invention, the number of lit cells in a subfield is detected, and based on the number of lit cells, the voltage of an erase pulse used in the next subfield is detected.・ Automatically adjusts pulse width and resets wall charges.Erase pulse with optimal conditions can be selected for voltage drop that increases in proportion to the number of lighting cells. A reduction in the erase voltage margin is prevented, and stable driving is possible.

Also, the AC-PDP device according to the present invention
The number of lit cells in the subfield is detected, and based on the number of lit cells, the shape of the erasing pulse used in the subsequent subfield is automatically adjusted and the wall charge is reset. An erase pulse having an optimum condition can be selected with respect to the voltage drop, and a reduction in the erase voltage margin due to the influence of the voltage drop can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of an AC-PDP control method according to the present invention.

FIG. 2 is a schematic diagram showing a relationship between a timing chart and a voltage waveform of a narrow erase pulse in an AC-PDP control method according to the present invention.

FIG. 3 is a diagram showing a relationship between a display rate and a voltage drop in the AC-PDP control method according to the present invention.

FIG. 4 is a schematic diagram showing a voltage waveform used at the time of erasing discharge of a narrow erasing pulse in the method of controlling an AC-PDP according to the present invention.

FIG. 5 is a view showing a structure of a conventional PDP.

FIG. 6 is a diagram showing an erasable area with respect to an erase pulse width and a voltage for explaining an erase characteristic in a conventional PDP.

[Explanation of symbols]

1 AC-PDP, 2 display control unit, 3 display drive unit, 4 display panel, 5 frame memory, 6
Display data processing section, 7 lighting cell number detection section, 8 erase pulse storage section, 9 erase pulse selection section, 10 display drive pulse generation section, 11 W drive circuit, 12 W drive circuit, 1
3 Y drive circuit, 14 X drive circuit, 20 front substrate,
21 X electrode, 22 Y electrode, 23 dielectric layer, 24
Protective film, 25 back substrate, 26 writing electrode (W electrode), 27 rib, 28 phosphor, 29 discharge space

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5C080 AA05 BB05 DD09 EE29 FF12 HH02 HH07 JJ02 JJ04 JJ05 JJ06 5C094 AA13 AA53 AA56 BA31 CA19 DB01 DB04 EA04 EA05 EA10 EB02 EC04 FA01 FA02 GA10

Claims (6)

[Claims] 1. A drive control method for an AC-driven plasma display device, comprising: a reset period for erasing a discharge history, an address period for selecting a cell to be displayed, and a discharge sustain period for obtaining luminance. Drive control using the subfield having, the shape of the erase pulse used in the reset period,
A method for controlling a plasma display device, comprising selecting from a plurality of erase pulse shape data based on the number of lighting cells detected in a subfield immediately before the reset period. 2. An AC-driven plasma display apparatus, comprising: a plurality of scan electrodes arranged in parallel; a plurality of discharge sustaining electrodes paired with the scan electrodes and formed on the same plane; 2. The semiconductor device according to claim 1, further comprising: a plurality of data electrodes opposed to each other so as to intersect the discharge sustaining electrodes; and a plurality of display cells provided in an intersection area between the scan electrodes and the sustaining electrodes and the data electrodes.
3. The control method for a plasma display device according to item 1. 3. The shape data of the plurality of erase pulses,
3. The method according to claim 1, wherein at least one of the voltage value and the pulse width is different from each other. 4. The driving control is performed using a subfield having a reset period for erasing a discharge history, an address period for selecting a cell to be displayed, and a discharge sustaining period for obtaining luminance. An AC-driven plasma display device, comprising: a frame memory for storing an input video signal; a lighting cell number detection unit for detecting and storing the number of lighting cells in the subfield based on data in the frame memory; An erasing pulse storage unit that stores a plurality of shape data of the erasing pulse used in the reset period; and an erasing pulse in the next subfield based on the number of lighting cells detected and stored by the number of lighting cells detector. An erase pulse selection unit for selecting the shape of the erase pulse from a plurality of shape data in the erase pulse storage unit; A plasma display device including the erase pulse generator for generating an erase pulse based on the output of. 5. An AC driven plasma display apparatus comprising: a plurality of scan electrodes arranged in parallel; a plurality of sustain electrodes formed in the same plane as a pair with the scan electrodes; 5. A semiconductor device comprising: a plurality of data electrodes disposed to face each other so as to intersect with a sustain electrode; and a plurality of display cells provided in an area where the scan electrode and the sustain electrode intersect with the data electrode. 3. The plasma display device according to 1. 6. The shape data of the plurality of erase pulses,
6. The plasma display device according to claim 4, wherein at least one of the voltage value and the pulse width is different from each other.