JP2001148686A - Digital signal transmitting and receiving system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital signal transmitting/receiving system which has a small-scale circuit constitution and can surely transmit and receive the asynchronous data. SOLUTION: In a digital signal transmitting/receiving system where the data signal WDT sent from a device 10 of the transmitting side is latched by the read clock signal of a device 20 of the receiving side, the phase of a write clock WCK that is sent from the device 10 to the device 20 is compared with the phases of 1st and 2nd read clocks RCK1 and RCK2 respectively. When the phase of the clock WCK is coincident with the phase of one of both clocks RCK1 and RCK2, a clock selection part 21 switches a read clock RCK to one of both clocks RCK1 and RCK2 that has its phase which is not coincident with the phase of the clock WCK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a case where a signal receives jitter or wander in a transmission line, or a case where two devices for transmitting and receiving data operate with clocks obtained from different oscillation sources. The present invention relates to a digital signal transmission / reception method for eliminating data transmission / reception errors.

[0002]

2. Description of the Related Art A conventional digital signal transmission / reception system will be described with reference to FIG. In FIG. 14, a description will be given with reference numeral 140 as a transmitting device and reference numeral 150 as a receiving device.
The transmission-side device 140 places the data signal A as shown in FIG.
Is sent to the receiving device 150. In the receiving device 150, the clock transfer unit 151 performs clock transfer based on the clock B generated by the oscillation source 152, and outputs a data signal B. In this case, the data signal A is latched at the rising edge of the clock B, for example.

In the above configuration, if there is a disturbance in the transmission line L and there is a phase fluctuation between the clock A of the transmitting device 140 and the clock B of the receiving device 150, as shown in FIG. At the transition point of the data signal A and the clock B
Rising edges coincide with each other, and an error occurs in the data signal B. In such a case, if the phase relationship between the data signal A and the clock B is stabilized without change, the error of the data signal B continues.

In order to solve the above problem, there is a method in which a plurality of buffer memories are provided in a receiving device, and data signals sent from a transmitting device are written into the plurality of buffer memories at different timings. In a normal state, data is read from one buffer memory, and when the phase relationship between the data signal and the read clock changes and there is a possibility that an error occurs in the data signal, the data signal is read from another buffer memory. This is a reading method.

[0005]

As described above, if a plurality of buffer memories are provided in the receiving apparatus, errors in the data signal can be avoided. However, when transmitting and receiving a large number of parallel signals, there is a problem that the number of buffer memories increases and the circuit scale increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal transmission / reception system which solves the above-mentioned drawbacks and can reliably transmit and receive asynchronous data with a small circuit.

[0007]

According to the present invention, a transmitting side transmits a data signal and a write clock synchronized with the data signal, and a receiving side transmits the data signal transmitted from the transmitting side to a receiving side. In a digital signal transmitting and receiving method in which a data signal is transmitted and received by latching with a read clock signal, the receiving side includes: clock generating means for generating a first read clock and a second read clock synchronized with each other; A first phase comparator for comparing the phases of one read clock; and a second phase comparator for comparing the phases of the write clock and the second read clock, wherein the phases of the write clock and the first read clock are provided. If the two match, the read clock is switched to the second read clock, and the write clock and the second read clock are switched. Is the case where the phase of the clock are matched, and characterized in that switches the read clock to the first read clock.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. Reference numeral 10 denotes a transmitting device, and reference numeral 20 denotes
Is a receiving side device. The receiving device 20 includes a clock selection unit 21, a data latch unit 22, and the like.

[0009] The clock selecting unit 21 includes
, And the first and second read clocks RCK1 and RCK2 generated by the receiving device 20 asynchronous with the write clock WCK.
Enter. Then, a read clock RCK is output.

The data latch unit 22 includes a read clock RCK output from the clock selection unit 21, a signal obtained by inverting the second read clock RCK 2 by the NOT circuit 23, and a data signal WD sent from the transmission side device 10.
T inputs respectively. The data signal WDT is, for example, a single or a plurality of NRZ data signal sequences, is synchronized with the write clock WCK, and has a transition point, for example, at a rising edge of the write clock WCK. Then, the data latch unit 22 outputs the data signal RDT.

The timing of each of the above-mentioned signals is shown, for example, in FIGS.

Here, the receiving apparatus 20 will be described with reference to FIG. In FIG. 3, parts corresponding to those in FIGS. 1 and 2 are denoted by the same reference numerals, and overlapping description is partially omitted.

The clock selection unit 21 includes two phase comparison circuits 2 composed of an OR circuit (hereinafter referred to as an AND circuit).
11, 212, an RS latch circuit 213, and a selection circuit 214. The selection circuit 214 includes two AND circuits a1 and a2, a NOT circuit a3 located on the input side of the AND circuit a1, and an OR circuit a4 located on the output side of the two AND circuits a1 and a2.

The data latch section 22 has two data latch circuits 221 and 222 each composed of a D flip-flop.
Are connected in parallel. Data signals WDT0 to WDTn and a read clock RCK sent from the transmission side device are input to the first-stage data latch circuit 221 respectively. The output of the first-stage data latch circuit 221 is directly input to the second-stage data latch circuit 222, and at the same time, the second read clock RCK is input.
2 is input via the NOT circuit 23.

In the above configuration, the phase comparison circuit 21
1, the write clock WCK and the first read clock RCK
1 are compared in phase, and the phase comparison circuit 212 compares the phases of the write clock WCK and the second read clock RCK2. At this time, if the clocks whose phases are compared overlap with each other, the outputs of the phase comparison circuits 211 and 212 become true. The first read clock RCK1 and the second read clock RCK2 are synchronized with each other, and as shown in FIG.
It is wider than the pulse width A of K. Therefore, the outputs of the two phase comparison circuits 211 and 212 do not become true at the same time.

The outputs of the phase comparison circuits 211 and 212 are R-
The signal is input to the S latch circuit 213 to latch the selection control signal. The selection control signal is output from the NOT circuit a3 of the selection circuit 214.
Is input to the AND circuit a1 through the
Input directly to 2. A first read clock RCK1 is input to the AND circuit a1, a second read clock RCK2 is input to the AND circuit a2, and one of the first and second read clocks RCK1 and RCK2 is selected.
Output from the OR circuit a4 as the read clock RCK. For example, when the output of phase comparison circuit 211 is true, second read clock RCK2 is selected, and when the output of phase comparison circuit 212 is true, first read clock RCK1 is selected.
Is selected.

The read clock RCK is a latch clock for the first-stage data latch circuit 221 in the data latch unit 22. In this case, since the read clock RCK does not coincide with the transition point of the data signal WDT, the data is reliably latched, and no error occurs in the data signal. The latched data is latched again by the second-stage data latch circuit 222, so that the phases of the data signals RDT0 to RDTn output from the data latch unit 22 are always constant.

According to the above configuration, latching is performed, for example, at the falling edge of the second read clock RCK2, and the data signal WDT on the transmission side is, as shown in FIG.
The data signal RDT is converted to a data signal RDT obtained by changing the clock.
In this case, even if the change point of data signal WDT and the change point of first read clock RCK1 or second read clock RCK2 continue to match, data signal WDT
Are latched by either one of the read clocks whose change points do not match, thereby avoiding an error in the data signal.

By the way, in the case of the above-described configuration, a situation where the first read clock RCK1 is switched to the second read clock RCK2, and conversely, a situation where the second read clock RCK2 is switched to the first read clock RCK1,
There are the following four switching patterns.

First, the first switching pattern will be described with reference to FIG. FIG. 4 shows a situation where the write clock WCK and the data signal WDT are fixed in the time domain with respect to each other, and both the first and second read clocks RCK1 and RCK2 move leftward as indicated by arrows. Is shown. In this case, it is assumed that the data signal WDT is latched by the first read clock RCK1 before the switching occurs. At time t, the first read clock RC
When K1 overlaps with the write clock WCK (the output of the AND circuit 211 in FIG. 3 becomes true), the read clock is immediately switched to the second read clock RCK2. And
The latch output is latched again at the falling edge of the second read clock RCK2. In this case, before and after the switching, the output data signal RDT does not have duplication or omission as shown in FIG.

It should be noted that RCK2 in FIG.
The signal whose polarity is inverted is shown below, and the signal whose polarity is inverted is shown with an underline.

Next, the second switching pattern will be described with reference to FIG. FIG. 5 shows a situation in which the write clock WCK and the data signal WDT are fixed in the time domain with respect to each other, and both the first and second read clocks RCK1 and RCK2 move leftward as indicated by arrows. Is shown. In this case, it is assumed that the data signal WDT is latched by the second read clock RCK2 before the switching occurs. At time t, the second read clock RC
When K2 overlaps with the write clock WCK (the output of the AND circuit 212 in FIG. 3 becomes true), the read clock is immediately switched to the first read clock RCK1. At this time, switching of the data latch circuit 221 of the first stage constituting the data latch unit 12 in FIG. 3 cannot be made in time, so that, for example, the data # 1 is changed to the second read clock RCK2 at the moment when the switching occurs and after the completion of the switching. First read clock R
Latched at CK1. As a result, as shown in (f) of the figure, the output data signal RDT has data # 1 redundantly output.

Next, the third switching pattern will be described with reference to FIG. FIG. 6 shows a situation in which these are fixed in the time domain with reference to the write clock WCK and the data signal WDT, and both the first and second read clocks RCK1 and RCK2 move rightward as indicated by arrows. Is shown. In this case, it is assumed that the data signal WDT is latched by the second read clock RCK2 before the switching occurs. At time t, the second read clock RC
K2 and the data signal WCK overlap (AND circuit 2 in FIG. 3)
12 becomes true), the read clock is switched to the first read clock RCK1. Then, the latch output is latched again at the falling edge of the second read clock RCK2. In this case, before and after the switching, the output data signal RDT does not have any duplication or omission as shown in FIG.

Next, the fourth switching pattern 4 shown in FIG.
Will be described. FIG. 7 shows that these are fixed in the time domain on the basis of the write clock WCK and the data signal WDT,
This shows a situation where both the first and second read clocks RCK1 and RCK2 move rightward as indicated by arrows. In this case, it is assumed that the data signal WDT is latched by the first read clock RCK1 before the switching occurs. At time t, the first read clock RC
K1 overlaps the data signal WCK (AND circuit 2 in FIG. 3)
11 becomes true), the read clock is immediately switched to the second read clock RCK2. Further, the latch output is latched again at the falling edge of the second read clock RCK2. In this case, at the time of switching, the output data signal RDT lacks data # 1 for one time slot, as shown in FIG.

As described above, in the second switching pattern and the fourth switching pattern, duplication or omission of data occurs when the read clock is switched. Such a problem is difficult to avoid under certain circumstances, and an appropriate measure is required depending on the circuit when data discontinuity occurs.

Here, as another embodiment of the present invention, FIG. 8 shows an example in which a function for notifying whether duplication or omission of data has occurred or not occurred when a read clock is switched is provided. I will explain. FIG. 12 shows the timing of each signal in FIG.

Reference numeral 81 denotes a timing generator, to which a first read clock RCK1 and a clock RC synchronized with the first read clock RCK1 and having, for example, an eight-fold frequency are input. And the second
Read clock RCK2, negative clear signal NC
L, and outputs an enable signal EN.

Reference numeral 82 denotes a clock selection unit. The clock selection unit 82 has a write clock WCK and a read clock RC sent from a transmission side device (not shown).
K1 and the clock RC are input, and further, the second read clock RCK2 output from the timing generation unit 81, the negative clear signal NCL, and the enable signal EN are input. Then, the read clock RCK, NORM (a state where there is no error in the latch of the data signal), LOST (a state where data is missing in the data signal), and DUPL (a state where data duplication occurs in the data signal) are performed. Output.

Reference numeral 83 denotes a data latch unit. The data latch unit 83 has a data signal WDT and read clocks RCK and NOT sent from a transmission side device (not shown).
The second read clock RCK2 is input via the circuit. Then, it outputs a data signal RDT.

Here, the timing generator 81 will be described with reference to FIG. Timing generator 81
Generates a timing signal such as the second read clock RCK2. Reference characters IN1 and IN2 denote input terminals, and three data latch circuits D1, D2 and D3 each composed of a D flip-flop are cascade-connected to the input terminals IN1 and IN2. A data latch circuit D4 composed of a D flip-flop is connected to the third-stage data latch circuit D3. Data latch circuit D1 and data latch circuit D
4, the RS latch circuit R1 is connected, and the RS latch circuit R1 is connected to the output terminal OUT1. Note that the data latch circuit D3 is connected to the output terminal OUT2. The data latch circuit D4 is connected to the input terminal IN2 via the NOT circuit N1, and is connected to the data latch circuit D5. The data latch circuit D5 has N
It is connected to the input terminal IN2 via the OT circuit N1 and to the output terminal OUT3.

In the above configuration, the first read clock RCK1 is input from the input terminal IN1, and the input terminal IN1
2, a clock RC is input. And the output terminal 0U
From T1 to 0UT3, an enable signal EN, a read clock RCK2 having a different timing in synchronization with the first read clock RCK1, and a negative clear signal NCL, respectively.
Output.

Next, FIG.
This will be described with reference to FIG.

Reference numerals IN3 to IN8 denote input terminals. The input terminals IN3 and IN5 are connected to a data latch circuit D6 composed of D flip-flops.
6 is connected to a data latch circuit D7 composed of a D flip-flop. Note that a NOT circuit N2 is connected between the input terminal IN3 and the data latch circuit. The data latch circuits D6 and D7 are connected to AND circuits A1 and A2, and the AND circuits A1 and A2 are connected to an output terminal 0UT4 via an OR circuit O1. Input terminals IN4, IN
5, an AND circuit A3 is connected to input terminals IN4 and IN4.
6 is connected to an AND circuit A4. AND circuit A
3, A4 is connected to the RS latch circuit R2. Data latch circuits D8 and D9 each composed of a D flip-flop are connected to the input terminal IN7, and one terminal of the data latch circuits D8 and D9 is connected to the input terminal IN8. Further, the RS latch circuit R2 includes a NOT circuit N
3 and N4, are connected to the AND circuit A1 and the data latch circuit D8, respectively, and are directly connected to the AND circuit A2 and the data latch circuit D9. The data latch circuit D8 is connected to the output terminal 0UT5, the data latch circuit D9 is connected to the output terminal 0UT6, and the data latch circuits D8 and D9 are connected to the output terminal 0UT via the exclusive OR circuit E1.
7 is connected.

In the above configuration, the input terminals IN3 to IN3
From IN8, a clock RC, a write clock WCK, a first read clock RCK1, a second read clock RCK
2. Enable signal EN, negative clear signal NCL
Enter. Then, read clocks RCK, DUPL (a state where data duplication occurs in the data signal), LOST (a state where data loss occurs in the data signal), and NORM (there is no error in the latch of the data signal) from the output terminals 0UT4 to OUT7. State).

As described above, the clock selecting unit 82 switches the latch clock, and determines which of the above switching patterns 1 to 4 is exclusively true by NORM, LOST, Notification is made with each signal of DUPL. Note that NORM indicates that there is no error when data is latched, and LOST indicates that DU has been lost when data is lost.
PL becomes true when data is duplicated.

Next, the data latch unit 83 will be described with reference to FIG.
This will be described with reference to FIG.

Reference characters IN9 to IN12 denote input terminals. Two data latch circuits D11 and D12 each composed of a D flip-flop are connected in cascade to the input terminals IN10 to IN11n and the input terminal IN9. The output terminals OUT8 to OUT8 are connected to the second data latch circuit D12.
9n are connected.

In the above configuration, the input terminal IN10
ＩＮIN11n to the first stage data latch circuit D11. At this time, 1
The stage of the data latch circuit D11 is clock RCK2 obtained by inverting the polarity of the input terminal IN9 second read clock RCK2 also enter. Second stage data latch circuit D1
2, the read clock RCK is input from the input terminal IN12. And, to the output terminals OUT8 to OUT9n,
Data signals RDT0 to RDTn are output.

According to the above configuration, the time t1 in FIG.
And the second read clock RCK2 and the write clock WC
When K overlaps and the read clock is switched, duplication of data # 2 occurs as shown in FIG. In this case, the signal DUPL becomes true as shown in FIG.

At time t2, the first read clock R
When CK1 overlaps the write clock WCK and the read clock is switched, as shown in FIG.
Is missing. In this case, as shown in FIG.
ST becomes true.

If there is no duplication or omission of data,
The signal NORM becomes true as shown in FIG.

As described above, in the data latch unit 83,
DUPL, LOS at the timing of latching the output signal
Either T or NORM signal becomes true. For this reason,
For example, if signal DUPL is true, data signal RDT
For example, processing such as accepting the output of (ALLO) can be performed.

In the clock selector 82 shown in FIG.
A data latch circuit D6 is connected to the input terminals IN3 and IN5, and a data latch circuit D7 is connected to the input terminals IN3 and IN6.
Are connected, and a NOT circuit N2 is connected between the input terminal IN3 and the data latch circuit D7. Here, the operation of the data latch circuits D6 and D7 will be described with reference to FIG. In FIG. 13, portions corresponding to those in FIG. 12 are denoted by the same reference numerals, and redundant description will be omitted.

For example, at time t, the write clock WCK and the second read clock RCK2 coincide, and switching occurs. At this time, if there is no data latch circuit D6 or data latch circuit D7, a glitch G occurs in the read clock RCK as shown in FIG. 7F, and depending on the width of the glitch G, the subsequent latch unit may malfunction. is there.
In such a case, if the data latch circuit D6 or the data latch circuit D7 is provided, generation of glitch G can be prevented.

In the embodiment shown in FIG. 8, FIG.
As shown in the figure, a clock RC having a frequency, for example, eight times the frequency of the first read clock RCK1 is used. By using such a clock RC, the second read clock RCK2 delayed from the first read clock RCK1 can be generated, and a DUP for notifying data duplication or loss is provided.
Each signal such as L, LOST, NORM, etc. can be generated, and the occurrence of glitch can be prevented.

According to the above configuration, when a signal receives jitter or wander in a transmission line connecting between two devices or circuits for transmitting and receiving data, or when two devices or circuits for transmitting and receiving data have different oscillations. When operating with the clock obtained from the source, a digital signal transmission / reception system can be obtained which has a simple circuit configuration, has no error in data transmission / reception, and can smoothly transmit / receive data.

[0047]

According to the present invention, it is possible to realize a digital signal transmission / reception system capable of reliably transmitting and receiving asynchronous data with a small-scale circuit.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram illustrating an embodiment of the present invention.

FIG. 2 is a diagram showing signal timings for explaining an embodiment of the present invention.

FIG. 3 is a circuit configuration diagram illustrating an embodiment of the present invention.

FIG. 4 is a diagram illustrating a first switching pattern according to the embodiment of the present invention.

FIG. 5 is a diagram for explaining a second switching pattern in the embodiment of the present invention.

FIG. 6 is a diagram illustrating a third switching pattern according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating a fourth switching pattern according to the embodiment of the present invention.

FIG. 8 is a circuit configuration diagram illustrating another embodiment of the present invention.

FIG. 9 is a circuit configuration diagram of a timing generation unit according to another embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of a clock selection unit according to another embodiment of the present invention.

FIG. 11 is a circuit configuration diagram of a data latch unit according to another embodiment of the present invention.

FIG. 12 is a diagram showing signal timings for explaining another embodiment of the present invention.

FIG. 13 is a diagram showing signal timings for explaining a glitch prevention operation in another embodiment of the present invention.

FIG. 14 is a diagram illustrating a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Transmission side apparatus 20 ... Reception side apparatus 21 ... Clock selection part 22 ... Data latch part 23 ... NOT circuit

Claims (4)

[Claims] 1. A transmitting side transmits a data signal and a write clock synchronized with the data signal, and a receiving side latches the data signal sent from the transmitting side with a reading clock signal of the receiving side to transmit the data signal. In the digital signal transmission / reception method for transmitting / receiving a signal, the receiving side compares a phase of the write clock and a phase of the first read clock with clock generation means for generating a first read clock and a second read clock synchronized with each other. First phase comparing means; and second phase comparing means for comparing the phases of the write clock and the second read clock. When the phases of the write clock and the first read clock match, the read operation is performed. The clock is switched to the second read clock, and the phases of the write clock and the second read clock match. Wherein the read clock is switched to the first read clock. 2. The method according to claim 1, wherein an interval between the first read clock and the second read clock is larger than a width of the write clock.
Digital signal transmission / reception system described in the above. 3. The digital signal transmission / reception system according to claim 1, wherein at least one of said first phase comparison means and said second phase comparison means comprises an OR circuit. 4. A method according to claim 1, wherein the read clock is switched from the first read clock to the second read clock, or at least data duplication and data loss occurring when the read clock is switched from the second read clock to the first read clock. 2. The digital signal transmission / reception system according to claim 1, further comprising a signal generation unit that generates a signal indicating one of the two.