JP2001144246A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount a noise eliminating filter circuit element at high density. SOLUTION: A chip layer mounting a semiconductor chip 12, a ground layer 14 and a power supply layer 16 are housed in a package 10 so as to pinch an insulation substance mutually, and inductor element mounting terminals 22, 24, and capacitor element mounting terminals 26, 28 are disposed in a chip, corresponding region 18 facing the semiconductor chip 12 out of a reverse face of the package 10, and an external connecting signal wiring terminal 30 is disposed in the region 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a filter circuit element mounting terminal for suppressing power supply noise or the like generated in a semiconductor chip in a package body.

[0002]

2. Description of the Related Art Some semiconductor devices, for example, LSIs, are provided with a power supply unit which performs high-speed switching operation. In this type of LSI, a filter circuit is usually configured with an inductor element and a capacitor element in order to reduce power supply noise generated by high-speed switching operation, and these filter circuit elements are mounted on a power supply unit. Have been.

[0003] When a filter circuit is formed on a printed circuit board, for example, Japanese Patent Application Laid-Open Nos. Hei 9-139573 and Hei 9
As described in JP-A-326451, instead of directly mounting an inductor element on a printed circuit board, one that obtains inductance by forming a spiral or serpentine pattern on a power supply layer of the printed circuit board is known. is there.

Further, when a filter circuit is formed in a package, a method of obtaining an inductance by a pattern in the package, as described in Japanese Patent Application Laid-Open No. 9-326451, an inductor element or a direct There has been proposed a configuration employing a configuration in which capacitor elements are mounted.

[0005]

According to the prior art, when a filter circuit is formed in a printed circuit board or a package, the inductor element is formed in a pattern in the printed circuit board or the package. An extra space must be secured for forming a pattern for the element, and it is difficult to mount the filter circuit element at high density. Furthermore, if there is a conductor layer close to the formed inductor pattern, it is difficult to obtain a large inductance as the inductor pattern due to the influence of the mutual inductance between the inductor pattern and the conductor layer, which reduces power supply noise. It is difficult to sufficiently reduce it.

On the other hand, when an inductor element or a capacitor element is directly mounted in a package, an inductor element or a capacitor element must be mounted on each of a plurality of power supply pins, resulting in a BGA (Ball Grid Array).
In a PGA (Pin Grid Array) package, the size is on the order of several centimeters, and it is difficult to secure a space for mounting a plurality of inductor elements and capacitor elements. In addition, when a semiconductor chip is provided with a plurality of power supply units, an inductor element and a capacitor element are mounted on power supply pins (a power supply line pin and a ground line pin) of each power supply unit. Manufacturing costs increase. Further, since the inductor element and the capacitor element are completely molded in the package with an insulating resin or the like, the element cannot be replaced later.

An object of the present invention is to provide a semiconductor device capable of mounting a noise removing filter circuit element at a high density.

[0008]

In order to achieve the above object, the present invention provides a chip layer on which a semiconductor chip is mounted,
A ground layer connected to a ground line in a power supply unit of the semiconductor chip, and a power supply connected to a power supply line having a different potential from the ground line in the power supply unit of the semiconductor chip to supply current to the semiconductor chip Wherein the semiconductor chip, the ground layer, and the power supply layer are housed in a package with an insulating material interposed therebetween, and are connected to the power supply layer in a chip-corresponding region of the package mounting surface facing the semiconductor chip. And a filter circuit element mounting terminal connected to the ground layer are arranged, and an external connection terminal connected to the semiconductor chip is arranged in a region different from the chip corresponding region. This constitutes a semiconductor device.

In configuring the semiconductor device, a first capacitor element mounting terminal and a plurality of inductor element mounting terminals are arranged as filter circuit element mounting terminals connected to a power supply layer, and a filter connected to a ground layer is provided. A second capacitor element mounting terminal can be disposed as a circuit element mounting terminal.

In constructing each of the semiconductor devices,
The following elements can be added:

(1) The power supply layer is divided into a plurality of regions, one of the plurality of inductor element mounting terminals is connected to one of the regions of the power supply layer, and the other of the power supply layers is connected to one of the plurality of inductor element mounting terminals. The other one of the plurality of inductor element mounting terminals and the first capacitor element mounting terminal are connected to the region.

(2) The first capacitor element mounting terminal and the second capacitor element mounting terminal have a terminal structure capable of mounting a plurality of capacitor elements in parallel.

According to the above-described means, the filter circuit element mounting terminal connected to the power supply layer and the filter circuit element mounting terminal connected to the ground layer are arranged in the chip corresponding area facing the semiconductor chip on the mounting surface of the package. Then, an external connection terminal connected to the semiconductor chip is arranged in a region different from the chip corresponding region, and the chip corresponding region excluding the region where the external connection terminal is arranged is used as an arrangement region of the filter circuit element mounting terminal. Therefore, by connecting a filter circuit element, for example, a capacitor element or an inductor element, to the filter circuit element mounting terminal, the filter circuit element can be mounted, and the noise removal filter circuit element can be mounted at a high density. Can be.

Further, since the capacitor element and the inductor element can be mounted on the filter circuit element mounting terminal exposed on the package mounting surface (back surface), the filter circuit element such as the capacitor element and the inductor element can be mounted as necessary. Can be exchanged.

Further, even when a plurality of power supply sections are provided on the semiconductor chip, the number of inductor elements and capacitor elements as filter circuit elements can be reduced by sharing the power supply line and the ground line of each power supply section. It is possible to reduce the number of parts and the manufacturing cost.

Further, by mounting a plurality of capacitor elements in parallel on the capacitor element mounting terminal, the parasitic inductance of the capacitor can be reduced, and the noise reduction effect can be further enhanced.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention as viewed from the back side, and FIG. 2 is an exploded perspective view of the semiconductor device. 1 and 2, the semiconductor device includes a grid array package 10. The grid array package 10 is formed in a substantially rectangular parallelepiped shape using a mold resin that is an insulating material.
In this grid array package 10, a semiconductor chip 12, a ground layer 14, and a power supply layer 16 are housed with an insulating material therebetween, and the mounting surface (rear surface) of the grid array package 10 with a printed circuit board is a semiconductor chip. 12 corresponding to chip 12 and other area 20
And are separated into The chip-corresponding region 18 is formed in a substantially square shape. In this chip-corresponding region 18, inductor element mounting terminals 22 and 24 and capacitor element mounting terminals 26 and 28 are arranged as filter circuit element mounting terminals. The area 20 includes an external connection signal wiring terminal 30 serving as a connection terminal with the printed circuit board, external connection ground terminals 30a and 30d, and an external connection power supply terminal 30.
b and 30c are arranged in a matrix as a plurality of grids.

The semiconductor chip 12 is mounted on a chip layer (not shown) together with the signal wiring 32 and the like. The semiconductor chip 12 includes a plurality of power supply units. Of the power supply units, power supply lines 34 and 36 indicating a positive potential with respect to the ground layer 14 are provided with holes H1 in the ground layer 14,
It passes through H2 and is connected to the region 16a inside the power supply layer 16. The ground lines 38 and 40 of the power supply section are connected to the ground layer 14. Further, each signal wiring 3
2 is connected to the external connection signal wiring terminal 30 through the signal wiring hole H0 of the ground layer 14 and the signal wiring hole h0 of the power supply layer 16.

The ground layer 14 is disposed between the chip layer and the power supply layer 16 with an insulating material interposed therebetween. The ground layer 14 is connected to the wiring through the holes h1 and h2 of the power supply layer 16 for external connection. It is connected to ground terminals 30a and 30d. The power supply layer 16 has a substantially rectangular notch 4
The area 2 is separated into an inner area 16a and an outer area 16b, and the outer area 16b is connected to external connection power terminals 30b and 30c. Outer area 16b
The inductor element mounting terminal 22 is fixed on the back side of
An inductor element mounting terminal 24 and a capacitor element mounting terminal (first capacitor element mounting terminal) 26 are fixed to the inner region 16a. In the outer region 16b, a plurality of holes hi for inserting signal wires are formed, and a hole h3 for inserting terminals of the capacitor element is formed. That is, the capacitor element mounting terminal (second capacitor element mounting terminal) 28 is fixed to the back side of the ground layer 14,
One terminal of the capacitor element is connected to the capacitor element mounting terminal 28 via the hole h3.

In the above configuration, when an inductor element is mounted on the inductor element mounting terminals 22 and 24, one terminal of the inductor element 44 is soldered to the inductor element mounting terminal 22, as shown in FIG. Is soldered to the inductor element mounting terminal 24. When mounting the capacitor element as the filter circuit element on the capacitor element mounting terminals 26 and 28, one terminal of the capacitor element is soldered to the capacitor element mounting terminal 26, and the other terminal of the capacitor element is connected via the hole h3. Solder to the capacitor element mounting terminal 28. Thus, the filter circuit element can be connected to the semiconductor chip 12.

More specifically, as shown in FIG. 4, a capacitor element 46 as a filter circuit element is connected to capacitor element mounting terminals 26 and 28, and an inductor element 44 is connected to inductor element mounting terminals 22 and 24, respectively. In addition, noise generated from the power supply unit of the semiconductor chip 12 can be removed by the filter circuit element.

The semiconductor chip 12 is connected to the power line 3
4, 36, ground lines 38 and 40, and signal wiring 32 are connected by wire bonding. And power terminal 3
When the power supply terminals 0b, 30c and the ground terminals 30a, 30d are respectively connected to the power supply, the current from the power supply terminals 30b, 30c flows to the region 16b outside the power supply layer 16, and the current flows from the outside region 16b through the inductor element 44 Region 1 of
A current flows through 6a. Thereafter, a current flows from the power supply lines 34 and 36 to the semiconductor chip 12 through the holes H1 and H2 of the ground layer 14. And the semiconductor chip 12
Is supplied to the ground layer 14 via the ground lines 38 and 40, and further passes from the ground layer 14 through the holes h1 and h2 to the ground terminals 30a,
It flows to 30d.

According to the present embodiment, the chip corresponding area 18
, The inductor element mounting terminals 22 and 24 and the capacitor element mounting terminals 26 and 28 are arranged, the inductor element mounting terminals 22 and 24 are connected to the inductor element 44, and the capacitor element terminals 26 and 28 are connected to the capacitor element 26. Therefore, the filter circuit element for noise removal can be mounted at a high density.

Further, after the package 10 is completed, the filter circuit element can be mounted by soldering, so that the inductor element 44 and the capacitor element 46 optimal for the printed circuit board on which the package 10 is mounted can be mounted. The cost can be reduced, and the inductor element 44 and the capacitor element 46
Can be replaced.

The power supply lines 48 and 50 connected to the power supply lines 34 and 36 are connected to the region 16 inside the power supply layer 16.
a, and all the currents from the power supply terminals 30b and 30c are supplied via the inductor element 44, so that the number of inductor elements can be reduced to one. Further, since the structure is such that the region 16a inside the power supply layer and the ground layer 14 are connected by the capacitor element 46, the number of the capacitor elements is smaller than that of the structure in which the capacitors are mounted on the power supply lines 48 and 50, respectively. It is possible to reduce the number of parts and cost.

Next, another embodiment of the present invention will be described with reference to FIGS.

In this embodiment, the capacitor element mounting terminal 2
6a, 28a are replaced with a plurality of capacitor elements 46a, 46
b and 46c are terminal structures that can be mounted in parallel.

In this embodiment, the capacitor elements 46a, 46b,
6c in parallel with the capacitor element mounting terminals 26a, 28
6A, the apparent parasitic inductance of the capacitor element is reduced to 3 by mounting three capacitor elements 46a, 46b, 46c in parallel as shown in FIG.
It can be reduced by a factor of one.

Therefore, according to the present embodiment, three capacitor elements 4 are connected to the capacitor mounting terminals 26a and 28a.
By mounting 6a, 46b, and 46c in parallel, high-frequency current can easily pass, and high-frequency current that causes noise can be confined in the package 10 as compared with the case where one capacitor element is mounted. Propagation to the printed circuit board can be suppressed, and the noise reduction effect can be enhanced.

[0030]

As described above, according to the present invention,
A filter circuit element mounting terminal connected to the power supply layer and a filter circuit element mounting terminal connected to the ground layer are arranged in a chip-corresponding area of the package mounting surface facing the semiconductor chip. Since the external connection terminals connected to the semiconductor chip are arranged and the chip-corresponding area is used as the arrangement area for the filter circuit element mounting terminals, the filter circuit elements are connected to the filter circuit element mounting terminals, so that the filter circuit elements are connected. Can be mounted, and the noise removing filter circuit element can be mounted at a high density.

[Brief description of the drawings]

FIG. 1 is a perspective view of a semiconductor device according to an embodiment of the present invention, as viewed from the back surface side.

FIG. 2 is an exploded perspective view of a semiconductor device showing one embodiment of the present invention.

FIG. 3 is a perspective view showing a mounted state of the inductor element.

FIG. 4 is a diagram showing an equivalent circuit when a filter circuit element is mounted on a semiconductor device.

FIG. 5 is a perspective view when three capacitor elements are mounted in parallel.

FIG. 6 is a diagram showing an equivalent circuit when three capacitor elements are mounted in parallel.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Grid array package 12 Semiconductor chip 14 Ground layer 16 Power supply layer 18 Chip corresponding area 20 Area 22, 24 Inductor element mounting terminal 26, 28 Capacitor element mounting terminal 30 External connection signal wiring terminal 32 Signal wiring 34, 36 Power supply line 38, 40 ground line 42 notch 44 inductor element 46 capacitor element 48, 50 power supply lead-in

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Atsushi Nakamura 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Within the Semiconductor Group, Hitachi, Ltd. Hitachi, Ltd. Semiconductor Group, Ltd. (72) Inventor Toru Hayashi 5-2-1, Kamimizu Honcho, Kodaira-shi, Tokyo In the Semiconductor Group, Hitachi, Ltd.

Claims (4)

[Claims] A chip layer on which a semiconductor chip is mounted;
A ground layer connected to a ground line in a power supply unit of the semiconductor chip, and a power supply connected to a power supply line having a different potential from the ground line in the power supply unit of the semiconductor chip to supply current to the semiconductor chip Wherein the semiconductor chip, the ground layer, and the power supply layer are housed in a package with an insulating material interposed therebetween, and are connected to the power supply layer in a chip-corresponding region of the package mounting surface facing the semiconductor chip. And a filter circuit element mounting terminal connected to the ground layer are arranged, and an external connection terminal connected to the semiconductor chip is arranged in a region different from the chip corresponding region. Semiconductor device. 2. A chip layer on which a semiconductor chip is mounted;
A ground layer connected to a ground line in a power supply unit of the semiconductor chip, and a power supply connected to a power supply line having a different potential from the ground line in the power supply unit of the semiconductor chip to supply current to the semiconductor chip Wherein the semiconductor chip, the ground layer, and the power supply layer are housed in a package with an insulating material interposed therebetween, and are connected to the power supply layer in a chip-corresponding region of the package mounting surface facing the semiconductor chip. The first capacitor element mounting terminal and the plurality of inductor element mounting terminals, and the second capacitor element mounting terminal connected to the ground layer are arranged on the semiconductor chip in a region different from the chip corresponding region. A semiconductor device in which connected external connection terminals are arranged. 3. The power supply layer is separated into a plurality of regions, and one of the plurality of inductor element mounting terminals is connected to one region of the power supply layer,
The other of the plurality of inductor element mounting terminals and the first inductor element mounting terminal in the other region of the power supply layer;
3. The semiconductor device according to claim 2, wherein said capacitor element mounting terminals are connected. 4. The terminal according to claim 2, wherein the first capacitor element mounting terminal and the second capacitor element mounting terminal have a terminal structure capable of mounting a plurality of capacitor elements in parallel. Semiconductor device.