JP2001142436A5

JP2001142436A5 -

Info

Publication number: JP2001142436A5
Application number: JP1999324794A
Authority: JP
Filing date: 1999-11-16
Publication date: 2005-06-30
Anticipated expiration: 2019-11-16

Description

【００１２】
【課題を解決するための手段】
本発明に係わる液晶駆動装置は、駆動すべき液晶パネルの各データ線に対応して１水平期間ごとに、アナログデータがコンデンサにサンプル・ホールドされボルテージホロワ接続の演算増幅器に入出力されるサンプル・ホールド動作と、コンデンサにサンプル・ホールドされ演算増幅器に入出力されたアナログデータが出力端子に出力される出力動作とを２系統で交互に行うサンプル・ホールド回路と、各演算増幅器にバイアス電流を供給するバイアス回路部とを備えた液晶駆動装置において、バイアス回路部は、第１のトランジスタを含むバイアス電流源と、第１のトランジスタに流れる電流をミラー比を切替え可能にミラーして各演算増幅器の一方の演算増幅器にバイアス電流を取り出す第２のトランジスタを含む第１バイアス電流取出し回路と、第１のトランジスタに流れる電流をミラー比を切替え可能にミラーして各演算増幅器の他方の演算増幅器にバイアス電流を取り出す第３のトランジスタを含む第２バイアス電流取出し回路とを有し、各ミラー比を切替えて、各演算増幅器に供給するサンプル・ホールド動作中のバイアス電流を、出力動作中のバイアス電流より少なく、かつ、サンプル・ホールド動作中に演算増幅器の出力端に安定した波形でアナログデータを出力するのに十分な電流値としたことを特徴とする。
上記手段によれば、バイアス回路部内のトランジスタのミラー比を切替えて、各演算増幅器に供給するサンプル・ホールド動作中のバイアス電流を、出力動作中のバイアス電流より少なく、かつ、サンプル・ホールド動作中に演算増幅器の出力端に安定した波形でアナログデータを出力するのに十分な電流値としているので、演算増幅器の出力端に安定した波形を出力するようにしたうえで、サンプル・ホールド動作中の系統の演算増幅器に供給するバイアス電流を低減できる。 0012
[Means for solving problems]
In the liquid crystal drive device according to the present invention, analog data is sample-held in a capacitor and input / output to / from a voltage hollower-connected arithmetic amplifier for each horizontal period corresponding to each data line of the liquid crystal panel to be driven. -A sample hold circuit that alternately performs the hold operation and the output operation in which the analog data sample-held by the capacitor and input / output to the arithmetic amplifier is output to the output terminal, and the bias current is applied to each arithmetic amplifier. In the liquid crystal drive device provided with the bias circuit unit for supplying, the bias circuit unit mirrors the bias current source including the first transistor and the current flowing through the first transistor so that the mirror ratio can be switched, and each arithmetic amplifier. The first bias current take-out circuit including the second transistor that takes out the bias current to one arithmetic amplifier, and the current flowing through the first transistor are mirrored so that the mirror ratio can be switched to the other arithmetic amplifier of each arithmetic amplifier. It has a second bias current take-out circuit including a third transistor that takes out the bias current, switches each mirror ratio, and supplies the bias current during sample hold operation to each arithmetic amplifier as the bias current during output operation. It is characterized by having a current value that is less and sufficient to output analog data with a stable waveform at the output end of the arithmetic amplifier during the sample hold operation.
According to the above means, the bias current during the sample hold operation supplied to each operational amplifier by switching the mirror ratio of the transistor in the bias circuit section is smaller than the bias current during the output operation, and during the sample hold operation. Since the current value is sufficient to output analog data with a stable waveform at the output end of the operational amplifier, the stable waveform is output to the output end of the operational amplifier, and the sample hold operation is in progress. The bias current supplied to the operational amplifier of the system can be reduced.

以上説明したように、サンプル・ホールド回路２０の１水平期間ごとにサンプル・ホールド動作と出力動作を交互に行う２系統のうち第１系統３０（第２系統４０）が出力動作のとき、第１バイアス電流取出し回路６１（第２バイアス電流取出し回路６２）は、電流源５１に流れる電流をトランジスタＱ１３ａとＱ１３ｂ（Ｑ２３ａとＱ２３ｂ）とでミラーして第１系統３０（第２系統４０）の演算増幅器３３（４３）に供給し、第２バイアス電流取出し回路６２（第１バイアス電流取出し回路６１）は、電流源５１に流れる電流をトランジスタＱ２３ｂ（Ｑ１３ｂ）のみでミラーしてサンプル・ホールド動作中の第２系統４０（第１系統３０）の演算増幅器４３（３３）に供給するので、サンプル・ホールド動作中の第２系統４０（第１系統３０）の演算増幅器４３（３３）には、第２系統４０（第１系統３０）が出力動作中のときに演算増幅器４３（３３）に流れるバイアス電流に対してトランジスタＱ２３ａとＱ２３ｂ（Ｑ１３ａとＱ１３ｂ）との合計サイズに対するトランジスタＱ２３ｂ（Ｑ１３ｂ）のサイズの比のバイアス電流が流れ、バイアス電流により演算増幅器４３（３３）で消費される消費電流を低減することができる。 As described above, when the first system 30 (second system 40) of the two systems that alternately perform the sample hold operation and the output operation for each horizontal period of the sample hold circuit 20 is the output operation, the first system The bias current extraction circuit 61 (second bias current extraction circuit 62) mirrors the current flowing through the current source 51 with the transistors Q13a and Q13b (Q23a and Q23b), and is an operational amplifier of the first system 30 (second system 40). The second bias current extraction circuit 62 (first bias current extraction circuit 61) supplied to 33 (43) mirrors the current flowing through the current source 51 only with the transistor Q23b (Q13b), and the second bias current extraction circuit 62 (first bias current extraction circuit 61) is in the sample hold operation. Since the supply is supplied to the operational amplifier 43 (33) of the two systems 40 (first system 30), the operational amplifier 43 (33) of the second system 40 (first system 30) during the sample hold operation is supplied with the second system. The ratio of the size of the transistors Q23b (Q13b) to the total size of the transistors Q23a and Q23b (Q13a and Q13b) with respect to the bias current flowing through the operational amplifier 43 (33) when the 40 (first system 30) is in output operation. The bias current of the above flows, and the current consumption consumed by the operational amplifier 43 (33) due to the bias current can be reduced.

上記構成のバイアス回路部８０は、動作において、第１系統３０が出力動作のとき、入力端子２に"Ｌ"レベルの信号が供給され、第１バイアス電流取出し回路８１のトランスファゲートＳ１ａがオフ制御され、第２バイアス電流取出し回路８２のトランスファゲートＳ２ａがオン制御される。このとき、第１バイアス電流取出し回路８１は、バイアス電流源５１に流れる電流をＭＯＳトランジスタＱ１３でミラーして、ＭＯＳトランジスタＱ１４ｂのみに流し、さらにＭＯＳトランジスタＱ１４ｂに流れる電流をＭＯＳトランジスタＱ１５でミラーしてＭＯＳトランジスタＱ１６に流して、ＭＯＳトランジスタＱ１４ｂに流れる電流を出力端子８５からバイアス端子３５を介してＭＯＳトランジスタＱ１４ｂにミラー接続された演算増幅器３３のＮチャネル型ＭＯＳトランジスタでミラーするとともに、ＭＯＳトランジスタＱ１６に流れる電流を出力端子８６からバイアス端子３６を介してＭＯＳトランジスタＱ１６にミラー接続された演算増幅器３３のＰチャネル型ＭＯＳトランジスタにミラーして演算増幅器３３にバイアス電流を供給する。このとき、第２バイアス電流取出し回路８２は、バイアス電流源５１に流れる電流をＭＯＳトランジスタＱ２３でミラーして、ＭＯＳトランジスタＱ２４ａ，Ｑ２４ｂに流し、さらにＭＯＳトランジスタＱ２４ａ，Ｑ２４ｂに流れる電流をＭＯＳトランジスタＱ２５でミラーしてＭＯＳトランジスタＱ２６に流して、ＭＯＳトランジスタＱ２４ａ，Ｑ２４ｂに流れる電流を出力端子８７からバイアス端子４５を介してＭＯＳトランジスタＱ２４ａ，Ｑ２４ｂにミラー接続された演算増幅器４３のＮチャネル型ＭＯＳトランジスタでミラーするとともに、ＭＯＳトランジスタＱ２６に流れる電流を出力端子８８からバイアス端子４６を介してＭＯＳトランジスタＱ２６にミラー接続された演算増幅器４３のＰチャネル型ＭＯＳトランジスタにミラーして演算増幅器４３にバイアス電流を供給する。このとき演算増幅器４３に流れるバイアス電流は、ＭＯＳトランジスタＱ２４ａとＱ２４ｂとを同一サイズに設計した場合の例では、第２系統４０が出力動作のときに演算増幅器４３に流れるバイアス電流の半分のバイアス電流が流れることになる。第２系統４０が出力動作のときは、上記とは第１系統３０と第２系統４０との動作が反対となる。 In the operation of the bias circuit unit 80 having the above configuration, when the first system 30 is in the output operation, an "L" level signal is supplied to the input terminal 2, and the transfer gate S1a of the first bias current extraction circuit 81 is turned off. Then, the transfer gate S2a of the second bias current extraction circuit 82 is turned on and controlled. At this time, the first bias current extraction circuit 81 mirrors the current flowing through the bias current source 51 with the MOS transistor Q13, allows it to flow only through the MOS transistor Q14b, and further mirrors the current flowing through the MOS transistor Q14b with the MOS transistor Q15. The current flowing through the MOS transistor Q16 is mirrored by the N-channel type MOS transistor of the arithmetic amplifier 33 mirror-connected from the output terminal 85 to the MOS transistor Q14b via the bias terminal 35, and the current flows through the MOS transistor Q16. The flowing current is mirrored from the output terminal 86 to the P-channel type MOS transistor of the arithmetic amplifier 33 mirror-connected to the MOS transistor Q16 via the bias terminal 36, and the bias current is supplied to the arithmetic amplifier 33. At this time, the second bias current extraction circuit 82 mirrors the current flowing through the bias current source 51 with the MOS transistor Q23, causes the current flowing through the MOS transistors Q24a and Q24b, and further causes the current flowing through the MOS transistors Q24a and Q24b with the MOS transistor Q25. It is mirrored and passed through the MOS transistors Q26, and the current flowing through the MOS transistors Q24a and Q24b is mirrored by the N-channel MOS transistor of the arithmetic amplifier 43 mirror-connected from the output terminal 87 to the MOS transistors Q24a and Q24b via the bias terminal 45. At the same time, the current flowing through the MOS transistor Q26 is mirrored from the output terminal 88 to the P-channel type MOS transistor of the arithmetic amplifier 43 mirror-connected to the MOS transistor Q26 via the bias terminal 46 to supply the bias current to the arithmetic amplifier 43. .. At this time, the bias current flowing through the operational amplifier 43 is half the bias current flowing through the operational amplifier 43 when the second system 40 is in output operation in the example in which the MOS transistors Q24a and Q24b are designed to have the same size. Will flow. When the second system 40 is in the output operation, the operations of the first system 30 and the second system 40 are opposite to the above.

【図６】図５の水平ドライバＩＣに使用されるバイアス回路部。 FIG. 6 Figure 5Bias circuit section used for horizontal driver ICs.

Claims

For each horizontal period corresponding to each data line of the liquid crystal panel to be driven, analog data is sample-held in the capacitor and input / output to the voltage hollower-connected arithmetic amplifier, and sample-hold operation is performed in the capacitor. It is provided with a sample hold circuit that alternately performs an output operation in which analog data that is held and input / output to the arithmetic amplifier is output to the output terminal in two systems, and a bias circuit unit that supplies a bias current to each arithmetic amplifier. In the liquid crystal drive device
The bias circuit unit mirrors the bias current source including the first transistor and the current flowing through the first transistor so that the mirror ratio can be switched, and extracts the bias current to one of the arithmetic amplifiers. A first bias current extraction circuit including two transistors and a third transistor that mirrors the current flowing through the first transistor so that the mirror ratio can be switched and extracts the bias current to the other arithmetic amplifier of each arithmetic amplifier. Has a second bias current take-out circuit, including
The bias current during the sample hold operation supplied to each operational amplifier by switching the mirror ratio is smaller than the bias current during the output operation, and
A liquid crystal driving device characterized in that the current value is sufficient to output analog data with a stable waveform to the output terminal of the operational amplifier during the sample hold operation.