JP2001135781A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor

Info

Publication number
JP2001135781A
JP2001135781A JP31924299A JP31924299A JP2001135781A JP 2001135781 A JP2001135781 A JP 2001135781A JP 31924299 A JP31924299 A JP 31924299A JP 31924299 A JP31924299 A JP 31924299A JP 2001135781 A JP2001135781 A JP 2001135781A
Authority
JP
Japan
Prior art keywords
semiconductor element
support member
electrode
semiconductor device
inner lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP31924299A
Other languages
Japanese (ja)
Other versions
JP3649064B2 (en
Inventor
Masaji Funakoshi
正司 舩越
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP31924299A priority Critical patent/JP3649064B2/en
Publication of JP2001135781A publication Critical patent/JP2001135781A/en
Application granted granted Critical
Publication of JP3649064B2 publication Critical patent/JP3649064B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve a problem such that a high frequency, multi-pin semiconductor element can not be effectively laminated and mounted and an ultra-thin, miniaturized semiconductor device of high density can not be achieved in conventional QFP, QFN type semiconductor devices. SOLUTION: The device has a structure where a first semiconductor element 12 is mounted by a bump electrode 13 on a support member 11 with an outer terminal 21 with an insulation sheet interposed, a second semiconductor element 15 is laminated and mounted in the backside of the first semiconductor element 12 and is connected to an inner lead 17 by a metallic fine line 18, and one-sided sealing is carried out by sealing resin 19 for exposing the bottom surface of the support member 11 and the bottom surface and the outer side surface of the inner lead 17. AN area-like external terminal is arranged in a package bottom surface by an outer terminal 20, in the bottom surface of the inner lead and the outer terminal 21 of the support member 11. Thereby, an ultra-thin and compact semiconductor device of high density can be realized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の外囲
を封止し、特に周辺外部端子下面を露出させる片面封止
を行った半導体装置およびその製造方法に関するもので
あり、特に半導体素子の高周波化および積層による高集
積化対応を具現化した半導体装置および製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which the outer periphery of a semiconductor element is sealed, and in particular, a single-sided sealing for exposing the lower surface of peripheral external terminals, and a method of manufacturing the same. The present invention relates to a semiconductor device and a manufacturing method which realize high integration by high frequency and lamination.

【0002】[0002]

【従来の技術】近年、電子機器は携帯化が加速し、それ
に従い半導体パッケージに対する薄型化、小型化の要望
はもとより、高周波化および高集積化に対応したパッケ
ージ構造を求める動きが顕著になってきた。
2. Description of the Related Art In recent years, electronic equipment has been increasingly portable, and accordingly, there has been a remarkable movement to demand a package structure that is compatible with higher frequencies and higher integration, as well as demands for thinner and smaller semiconductor packages. Was.

【0003】従来の半導体装置は、薄型化および小型化
に注力する傾向が強く、その中でQFP(Quad F
lat Package)と呼ばれるパッケージが広く
用いられた。以下、そのQFPを例として従来の半導体
装置について説明する。
Conventional semiconductor devices tend to focus on thinning and miniaturization, and among them, QFPs (Quad F
A package called “lat Package” has been widely used. Hereinafter, a conventional semiconductor device will be described using the QFP as an example.

【0004】QFPは、外観四角のパッケージであり、
各側面に一定ピッチでガルウィング状のリード端子が配
置された構造である。従来のQFPの断面図を図12に
示す。
[0004] The QFP is a package having a square appearance.
It has a structure in which gull-wing-shaped lead terminals are arranged at a constant pitch on each side surface. FIG. 12 is a sectional view of a conventional QFP.

【0005】図12に示すようにQFPは、リードフレ
ームのダイパッド1上に半導体素子2が熱硬化する導電
性接着剤3を用いて搭載され、その半導体素子2の電極
とリードフレームの外部端子であるアウターリード4と
繋がっているインナーリード5とが金属細線6により電
気的に接続されている。そして、ダイパッド1、半導体
素子2、金属細線6およびインナーリード5を含む外囲
領域を封止樹脂7によりフルモールドされ、外部端子を
構成するアウターリード4は成形されて封止樹脂7から
突出した構成となっている。
[0005] As shown in FIG. 12, a QFP is mounted on a die pad 1 of a lead frame by using a conductive adhesive 3 by which a semiconductor element 2 is thermally cured, and is connected to electrodes of the semiconductor element 2 and external terminals of the lead frame. An outer lead 4 and an inner lead 5 connected thereto are electrically connected by a thin metal wire 6. The surrounding area including the die pad 1, the semiconductor element 2, the fine metal wires 6, and the inner leads 5 is fully molded with the sealing resin 7, and the outer leads 4 constituting the external terminals are formed and protrude from the sealing resin 7. It has a configuration.

【0006】またQFPの製造方法は図12を参照して
説明すると、リードフレームのダイパッド1上に半導体
素子2を搭載する工程と、外部端子を構成するアウター
リード4に繋がっているインナーリード5と半導体素子
1の電極とを金属細線6により電気的に接続する工程
と、ダイパッド1とその外囲領域を封止樹脂7によりフ
ルモールドする工程と、封止樹脂7から突出したアウタ
ーリード4をガルウィング状に成形し、リードフレーム
から分離する工程とから構成されるものである。そして
実装面積の縮小化を図るため外部端子の狭ピッチ化、外
部端子の細線化を行っている。
A method of manufacturing a QFP will be described with reference to FIG. 12. A step of mounting a semiconductor element 2 on a die pad 1 of a lead frame, and a step of mounting an inner lead 5 connected to an outer lead 4 constituting an external terminal. A step of electrically connecting the electrodes of the semiconductor element 1 with the thin metal wires 6, a step of fully molding the die pad 1 and its surrounding area with a sealing resin 7, and a step of gull-wing the outer leads 4 protruding from the sealing resin 7. And separating from the lead frame. In order to reduce the mounting area, the pitch of the external terminals is reduced and the external terminals are thinned.

【0007】しかしながら、外部端子ピッチが0.3
[mm]以下になると半田ペーストがマスクに残留する
などの問題があり、現行の実装技術では量産が困難であ
ることが判明している。そこで更なる実装面積の縮小お
よび薄型化を実現したのがQFN(Quad Flat
Non−Leaded Package)である。以
下、そのQFNについて説明する。
However, the external terminal pitch is 0.3
If the thickness is less than [mm], there is a problem that the solder paste remains on the mask, and it has been found that mass production is difficult with the current mounting technology. Therefore, the QFN (Quad Flat) has further reduced the mounting area and thickness.
Non-Leaded Package). Hereinafter, the QFN will be described.

【0008】QFNは片面封止技術を実現させることに
より、超薄型化および小面積化を図ることが可能となっ
た。図13はQFNを示す図であり、図13(a)は断
面図であり、図13(b)は1/2領域の底面図を示し
ている。なお、図13(a)は図13(b)のA−A1
箇所の断面を示している。
[0008] By realizing the single-sided sealing technology, the QFN can be made ultra-thin and small in area. FIG. 13 is a diagram showing a QFN, FIG. 13A is a cross-sectional view, and FIG. 13B is a bottom view of a half region. FIG. 13A shows A-A1 in FIG.
The cross section of the location is shown.

【0009】図13に示すようにQFNは、リードフレ
ームのPSD(Point Suport Diepa
d)構造を有するダイパッド8上に熱硬化性の導電性接
着剤3を介して半導体素子2が搭載されている。なお、
PSD構造とは半導体素子を数点で支持し、封止樹脂と
半導体素子の密着性を良好とし、実装時の耐パッケージ
クラック性を向上させ、出荷からセット基板への実装期
間を長期化することを目的とするものである。そして半
導体素子2の電極とリードフレームのインナーリード9
の上面とが金属細線6により電気的に接続され、ダイパ
ッド8とその外囲を封止樹脂7により片面モールドさ
れ、パッケージ底面にはインナーリード9の底面および
外方側面が露出して外部端子10を構成しているもので
ある。
As shown in FIG. 13, QFN is a lead frame PSD (Point Support Diego).
d) The semiconductor element 2 is mounted on the die pad 8 having a structure via the thermosetting conductive adhesive 3. In addition,
The PSD structure is to support the semiconductor element at several points, improve the adhesion between the sealing resin and the semiconductor element, improve the package crack resistance during mounting, and prolong the mounting period from shipment to the set board. It is intended for. The electrodes of the semiconductor element 2 and the inner leads 9 of the lead frame
Are electrically connected to each other by a thin metal wire 6, the die pad 8 and its outer periphery are molded on one side by a sealing resin 7, and the bottom surface and the outer side surface of the inner lead 9 are exposed on the bottom surface of the package to form an external terminal 10. It is what constitutes.

【0010】そしてQFNの製造方法は、リードフレー
ムのPSD構造を有するダイパッド8上に半導体素子2
を搭載する工程と、その半導体素子2の電極とインナー
リード9とを金属細線6により電気的に接続する工程
と、ダイパッド8、半導体素子2、金属細線6を含む領
域を封止樹脂7により片面モールドする工程と、インナ
ーリード9を切断し、パッケージ単体にする工程とから
構成されるものである。
The method of manufacturing the QFN is such that the semiconductor element 2 is formed on the die pad 8 having the PSD structure of the lead frame.
Mounting, electrically connecting the electrode of the semiconductor element 2 to the inner lead 9 with the thin metal wire 6, and sealing the area including the die pad 8, the semiconductor element 2 and the thin metal wire 6 with the sealing resin 7. It comprises a molding step and a step of cutting the inner leads 9 to make a single package.

【0011】このようにQFNは、QFPでは封止樹脂
7から突出する外部端子10をパッケージ裏面と略同一
面上に露出させ、封止樹脂7の厚み(パッケージ厚)を
薄くしたことが大きな特徴であり、パッケージ厚0.8
[mm]以下という超薄型かつ小型化を実現したパッケ
ージである。
As described above, the QFN is characterized in that the external terminals 10 protruding from the sealing resin 7 in the QFP are exposed on substantially the same surface as the back surface of the package, and the thickness (package thickness) of the sealing resin 7 is reduced. And the package thickness is 0.8
It is an ultra-thin and miniaturized package of [mm] or less.

【0012】[0012]

【発明が解決しようとする課題】しかしながら前記従来
のQFN型の半導体装置では、高周波半導体素子を搭載
すると、半導体素子の電極と外部端子とはワイヤーボン
ド(金属細線)により接続するため、金属細線長が長い
もので4[mm]となり、配線遅延が顕著化し、外部端
子間は狭ピッチとなり端子間容量の影響も大きく、高周
波半導体素子の特性が十分に発揮できないという課題が
ある。また、外部端子が周囲に配列されているため、外
部端子数の限界が小面積化を考慮すると少ピンとなり、
半導体素子個別での搭載となるため、高集積化対応への
課題が挙げられる。
However, in the conventional QFN type semiconductor device, when a high-frequency semiconductor element is mounted, the electrodes of the semiconductor element and the external terminals are connected by wire bonds (fine metal wires). Is long and 4 [mm], the wiring delay becomes remarkable, the pitch between the external terminals becomes narrow, the effect of the capacitance between the terminals is large, and there is a problem that the characteristics of the high-frequency semiconductor element cannot be sufficiently exhibited. Also, since the external terminals are arranged around, the limit of the number of external terminals is reduced when considering the area reduction,
Since the semiconductor elements are individually mounted, there is a problem of high integration.

【0013】本発明は、前記従来の課題を解決するもの
で、高周波半導体素子への対応、および高集積化を実現
し、従来設備の併用を可能にした半導体装置およびその
製造方法を提供することを目的とする。
An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device capable of coping with high-frequency semiconductor elements, achieving high integration, and using conventional facilities, and a method of manufacturing the same. With the goal.

【0014】[0014]

【課題を解決するための手段】前記従来の課題を解決す
るために本発明の半導体装置は、以下のような構成を有
している。すなわち、フェースダウンで搭載される半導
体素子の電極パットと対応した接続電極を有し、前記接
続電極と引き回し配線により接続され、その平面内でエ
リア配置された電極を有し、その前記電極は内部ビアで
底面に導通されて外部端子を構成している支持部材と、
前記支持部材上にその表面に設けたバンプ電極により、
絶縁材を介して前記接続電極にフェースダウンで搭載さ
れた第1の半導体素子と、前記第1の半導体素子の裏面
に積層搭載された第2の半導体素子と、前記第2の半導
体素子の表面の電極パッドとインナーリードとを接続し
た金属細線と、前記支持部材の底面、インナーリードの
底面と外方側面を露出させて外囲を封止した封止樹脂と
よりなり、前記インナーリードの前記封止樹脂から露出
した部分と前記支持部材の底面に配列した外部端子とで
エリア状の外部端子を構成している半導体装置である。
In order to solve the above-mentioned conventional problems, a semiconductor device according to the present invention has the following configuration. That is, it has a connection electrode corresponding to an electrode pad of a semiconductor element mounted face-down, is connected to the connection electrode by a lead-out wiring, and has an electrode arranged in an area in the plane, and the electrode has an internal shape. A support member that is electrically connected to the bottom surface with a via to form an external terminal,
By the bump electrode provided on the surface of the support member,
A first semiconductor element mounted face-down on the connection electrode via an insulating material, a second semiconductor element stacked and mounted on a back surface of the first semiconductor element, and a front surface of the second semiconductor element A metal thin wire connecting the electrode pad and the inner lead, and a bottom surface of the support member, a sealing resin that exposes the bottom surface and the outer side surface of the inner lead and seals the outer periphery, and A semiconductor device in which an area-shaped external terminal is constituted by a portion exposed from a sealing resin and external terminals arranged on a bottom surface of the support member.

【0015】具体的には、支持部材はシリコンにより形
成されている半導体装置である。
Specifically, the supporting member is a semiconductor device formed of silicon.

【0016】また、支持部材の断面形状において上部に
薄肉部を有している半導体装置である。
Further, the semiconductor device has a thin portion on an upper part in a sectional shape of the support member.

【0017】本発明の半導体装置の製造方法は、第1の
半導体素子の電極パッド上に突起電極を形成する工程
と、フェースダウンで搭載される半導体素子の電極パッ
ドと対応した接続電極を有し、前記接続電極と引き回し
配線により接続され、その平面内に配置された電極を有
し、前記電極は底面に導通されて外部端子を構成してい
る支持部材を用意する工程と、前記支持部材の上面に対
して絶縁シートを載置した後、前記支持部材に突起電極
を形成した第1の半導体素子をフェースダウンで搭載
し、前記支持部材の接続電極と第1の半導体素子の突起
電極とを接続する工程と、前記第1の半導体素子の裏面
に接着剤を塗布する工程と、前記接着剤を介して第1の
半導体素子上に第2の半導体素子をその底面側で接着し
て搭載する工程と、インナーリードを有し、前記支持部
材を配置できる開口領域を有したフレーム部材を用意
し、前記フレーム部材の開口領域に前記第1の半導体素
子,第2の半導体素子が搭載された支持部材を配置し、
前記第2の半導体素子の電極パッドと前記フレーム部材
のインナーリードとを金属細線により電気的に接続する
工程と、前記支持部材の底面、インナーリードの底面と
外方側面を露出させ、前記支持部材、第1の半導体素
子,第2の半導体素子および金属細線領域、インナーリ
ードの外囲を封止樹脂により封止する工程とよりなる半
導体装置の製造方法である。
A method of manufacturing a semiconductor device according to the present invention includes a step of forming a protruding electrode on an electrode pad of a first semiconductor element and a connection electrode corresponding to the electrode pad of the semiconductor element mounted face down. A step of preparing a supporting member that is connected to the connection electrode by a lead-out wiring and disposed in the plane of the supporting member, the electrode being electrically connected to the bottom surface to form an external terminal; and After placing the insulating sheet on the upper surface, the first semiconductor element having the protruding electrode formed on the supporting member is mounted face down, and the connection electrode of the supporting member and the protruding electrode of the first semiconductor element are connected. Connecting, applying an adhesive to the back surface of the first semiconductor element, and mounting the second semiconductor element on the first semiconductor element via the adhesive by bonding the second semiconductor element on the bottom side. Process and A frame member having a knurled lead and having an opening region in which the support member can be arranged is prepared, and a support member on which the first semiconductor element and the second semiconductor element are mounted is arranged in the opening region of the frame member. ,
Electrically connecting the electrode pad of the second semiconductor element to the inner lead of the frame member by a thin metal wire, exposing a bottom surface of the support member, a bottom surface and an outer side surface of the inner lead, And a step of sealing the first semiconductor element, the second semiconductor element, the thin metal wire region, and the outer periphery of the inner lead with a sealing resin.

【0018】具体的には、支持部材の上面に対して絶縁
シートを載置した後、前記支持部材に突起電極を形成し
た第1の半導体素子をフェースダウンで搭載し、前記支
持部材の接続電極と第1の半導体素子の突起電極とを接
続する工程では、突起電極により前記絶縁シートを貫通
させ、前記支持部材の接続電極と接続させ、突起電極間
に前記絶縁シートを入り込ませる半導体装置の製造方法
である。
Specifically, after the insulating sheet is placed on the upper surface of the support member, the first semiconductor element having the protruding electrode formed on the support member is mounted face down, and the connection electrode of the support member is mounted. Manufacturing the semiconductor device in which the insulating sheet is penetrated by the projecting electrode, connected to the connecting electrode of the support member, and the insulating sheet is inserted between the projecting electrodes in the step of connecting the projecting electrode to the projecting electrode of the first semiconductor element. Is the way.

【0019】また、インナーリードを有し、支持部材を
配置できる開口領域を有したフレーム部材を用意し、前
記フレーム部材の開口領域に第1の半導体素子,第2の
半導体素子が搭載された支持部材を配置し、前記第2の
半導体素子の電極パッドと前記フレーム部材のインナー
リードとを金属細線により電気的に接続する工程では、
前記支持部材をフレーム部材の開口領域に配置する際、
前記支持部材が載置される箇所に前記支持部材を吸着す
る真空吸着空孔と、弾性を有する耐熱性物質とが設けら
れたヒータープレートを用い、前記ヒータープレートの
前記耐熱性物質上に前記支持部材を吸着固定した状態で
配置する半導体装置の製造方法である。
A frame member having an inner lead and an opening region in which a support member can be arranged is prepared, and a supporting member in which a first semiconductor element and a second semiconductor element are mounted in the opening region of the frame member. Disposing a member, and electrically connecting the electrode pad of the second semiconductor element and the inner lead of the frame member by a thin metal wire;
When disposing the support member in the opening area of the frame member,
Using a heater plate provided with a vacuum suction hole for adsorbing the support member at a position where the support member is mounted, and a heat-resistant substance having elasticity, the support plate is provided on the heat-resistant substance of the heater plate. This is a method for manufacturing a semiconductor device in which members are arranged in a state of being fixed by suction.

【0020】前記のような構成により本発明の半導体装
置は、放熱効果はもとより、半導体素子の電極と外部端
子までの距離が最短化され配線遅延が低減されるととも
に、高周波化および多ピンを有する半導体素子の搭載で
き、多ピン半導体素子の電極間隔を実装基板の端子間隔
に拡大することが可能なパッケージ構造である。さらに
パッケージングで高集積化が可能となり、半導体素子の
電極と外部端子との接続技術も従来のワイヤーボンド技
術を用いることができ、汎用性に優れたものである。
With the above configuration, the semiconductor device of the present invention has not only a heat radiation effect, but also minimizes the distance between the electrode of the semiconductor element and the external terminal, reduces wiring delay, and has a higher frequency and more pins. A package structure in which a semiconductor element can be mounted and the electrode interval of the multi-pin semiconductor element can be expanded to the terminal interval of the mounting board. Further, high integration can be achieved by packaging, and the conventional wire bonding technology can be used for the connection technology between the electrode of the semiconductor element and the external terminal, which is excellent in versatility.

【0021】また、支持部材と半導体素子の搭載手段に
は、半導体素子の搭載時に、その半導体素子に形成され
たバンプ電極が、挟まれた絶縁シートを貫通して支持部
材の接続電極に到達するとともに、半導体素子に加えら
れる荷重で接合するといった方法を用いているので、各
突起電極高さの均一化処理が不必要になる。また突起電
極間の狭ピッチ化に関係なく、絶縁シートが各突起電極
間に入り込むため、突起電極間の電流リークを防止する
ことができる。さらに半導体装置の製造方法において
は、その製造設備であるヒータープレートに高弾性耐熱
物質を用いることにより、半導体素子の金属細線の接続
時にその半導体素子に加わる衝撃を大きく緩和し、半導
体素子ダメージによるクラック等の抑制効果がある。
In the mounting means for mounting the semiconductor element on the support member, the bump electrode formed on the semiconductor element reaches the connection electrode of the support member through the sandwiched insulating sheet when the semiconductor element is mounted. In addition, since a method of joining with a load applied to the semiconductor element is used, a process of equalizing the height of each protruding electrode is not required. Also, regardless of the narrow pitch between the protruding electrodes, the insulating sheet enters between the protruding electrodes, so that a current leak between the protruding electrodes can be prevented. Furthermore, in the method of manufacturing a semiconductor device, a high elastic heat-resistant material is used for a heater plate as a manufacturing facility, so that a shock applied to the semiconductor element when a thin metal wire of the semiconductor element is connected is greatly reduced, and a crack due to damage of the semiconductor element is generated. And so on.

【0022】[0022]

【発明の実施の形態】以下、本発明の半導体装置および
その製造方法について、その一実施形態を図面を参照し
ながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention and a method for manufacturing the same will be described below with reference to the drawings.

【0023】まず本実施形態の半導体装置について説明
する。図1は本実施形態の半導体装置を示す図であり、
図1(a)は断面図であり、図1(b)は略1/2領域
の底面図である。なお、図1(a)は図1(b)のB−
B1箇所の断面を示す。
First, the semiconductor device of this embodiment will be described. FIG. 1 is a diagram showing a semiconductor device of the present embodiment,
FIG. 1A is a cross-sectional view, and FIG. 1B is a bottom view of a substantially 1/2 region. FIG. 1A is a cross-sectional view of FIG.
The cross section at B1 is shown.

【0024】図1に示すように本実施形態の半導体装置
は、電極および配線を有した支持部材11上に第1の半
導体素子12がバンプ電極13により、絶縁樹脂または
絶縁シート14を介してフェースダウンで搭載され、そ
の第1の半導体素子12の裏面に第2の半導体素子15
が接着剤16により搭載され、チップ−オン−チップの
積層構造を有しているものである。そして第2の半導体
素子15の表面の電極とインナーリード17とが金属細
線18により電気的に接続され、支持部材11の底面、
インナーリード17の底面と外方側面を露出させて封止
樹脂19により片面封止された構造を有している。そし
て底面図に示すように、インナーリード17の封止樹脂
19から略同一面に露出した部分は外側の外部端子20
を構成し、また支持部材11の底面には内側の外部端子
21を有して、外部端子21が2列のグリッド状に配置
され、外部端子20と外部端子21とでパッケージ底面
にエリア状に外部端子を配置しているものである。
As shown in FIG. 1, in the semiconductor device of the present embodiment, a first semiconductor element 12 is provided on a support member 11 having electrodes and wirings by a bump electrode 13 and a face through an insulating resin or an insulating sheet 14. The second semiconductor element 15 is mounted on the back surface of the first semiconductor element 12.
Are mounted with an adhesive 16 and have a chip-on-chip laminated structure. Then, the electrode on the surface of the second semiconductor element 15 and the inner lead 17 are electrically connected by the thin metal wire 18, and the bottom surface of the support member 11,
It has a structure in which the bottom surface and the outer side surface of the inner lead 17 are exposed and sealed on one side by a sealing resin 19. Then, as shown in the bottom view, the portion of the inner lead 17 exposed from the sealing resin 19 on the substantially same surface is the external terminal 20 outside.
In addition, the support member 11 has an inner external terminal 21 on the bottom surface, the external terminals 21 are arranged in a two-row grid shape, and the external terminals 20 and the external terminals 21 are arranged in an area on the package bottom surface. The external terminals are arranged.

【0025】また、本実施形態の半導体装置において、
支持部材11は電極および配線を有したダイパッド機能
を有する部材であり、上面の半導体素子の電極と接続し
た電極を配線により引き回して、グリッド状に配置し、
その底面に外部端子として配置しているものである。図
2に本実施形態で用いる支持部材を示す。図2(a)は
平面図であり、図2(b)は底面図である。
Further, in the semiconductor device of this embodiment,
The support member 11 is a member having a die pad function having an electrode and a wiring, and the electrode connected to the electrode of the semiconductor element on the upper surface is routed by the wiring, and arranged in a grid.
These are arranged as external terminals on the bottom surface. FIG. 2 shows a support member used in the present embodiment. FIG. 2A is a plan view, and FIG. 2B is a bottom view.

【0026】図2に示すように本実施形態の支持部材1
1は、その表面にフェースダウンで搭載される半導体素
子の電極パッドと対応した接続電極22を有し、その電
極22と引き回し配線23により接続され、エリア配置
された電極24を有しているものである。そして表面の
電極24は支持部材内部のビアで底面に導通されて外部
端子21を構成しているものである。また支持部材11
は基板実装の信頼性のために電気的接続を有さないダミ
ー端子25を有している。
As shown in FIG. 2, the support member 1 of the present embodiment
1 has a connection electrode 22 corresponding to an electrode pad of a semiconductor element mounted face-down on the surface thereof, and has an electrode 24 connected to the electrode 22 by a lead-out wiring 23 and arranged in an area. It is. The electrode 24 on the front surface is electrically connected to the bottom surface by a via inside the support member to form the external terminal 21. The support member 11
Have dummy terminals 25 that have no electrical connection for reliability of board mounting.

【0027】支持部材11の材料としては、例えばシリ
コン、樹脂を用いる。また、支持部材11の材料にシリ
コンを用いると、ウェハー形状にすることによりバック
グラインダー設備を用い、一定厚さの支持部材を多数同
時に精度よく形成することが可能になる。さらにシリコ
ンによる支持部材11の場合、外部端子21および引き
回し配線23の形成には、従来の拡散設備を用いること
ができるため、微細配線化かつ設備有効利用に大きく貢
献することができる。またこの支持部材11には、高周
波特性、多ピンの半導体素子を搭載することが可能とな
り、その半導体素子の特性を十分に伝達できる機能を有
する。ダミー端子25は、電気的接続機能を持たず、実
装後の安定性を向上させる目的がある。しかし、支持部
材の標準化面で実際に必要な端子数以上に外部端子21
を付設し、採用範囲を拡大することも可能である。この
とき、余剰外部端子21がダミー端子25の機能を担う
ことになる。
As the material of the support member 11, for example, silicon or resin is used. Further, when silicon is used as the material of the support member 11, it becomes possible to form a large number of support members having a constant thickness at the same time and with high precision by using a back grinder facility by forming a wafer shape. Further, in the case of the support member 11 made of silicon, since the conventional diffusion equipment can be used for forming the external terminals 21 and the routing wiring 23, it is possible to greatly contribute to miniaturization of wiring and effective utilization of the equipment. The support member 11 can mount a high-frequency characteristic, multi-pin semiconductor element, and has a function of sufficiently transmitting the characteristic of the semiconductor element. The dummy terminal 25 has no electrical connection function, and has an object of improving stability after mounting. However, the number of external terminals 21 exceeds the number of terminals actually required in terms of standardization of the support member.
Can be added to expand the range of adoption. At this time, the surplus external terminal 21 performs the function of the dummy terminal 25.

【0028】また支持部材11としては、通常のリード
フレームのダイパッドに対して、その表面に電極および
引き回し配線、底面に表面の電極と導通した外部端子を
形成したものを用いてもよい。
As the support member 11, a die pad of a normal lead frame may be used in which electrodes and lead-out wiring are formed on the surface, and external terminals connected to the electrodes on the surface are formed on the bottom surface.

【0029】以上、本実施形態の半導体装置は、フェー
スダウンで搭載される半導体素子の電極パッドと対応し
た接続電極22を有し、その接続電極22と引き回し配
線23により接続され、エリア配置された電極24を有
し、その電極24は内部ビアで底面に導通されて外部端
子21を構成している支持部材11と、その支持部材1
1上に第1の半導体素子12がその表面に設けたバンプ
電極13により、絶縁材を介して接続電極22にフェー
スダウンで搭載され、第1の半導体素子12の裏面に第
2の半導体素子15が接着剤16により積層搭載され、
第2の半導体素子15の表面の電極とインナーリード1
7とが金属細線18により電気的に接続され、支持部材
11の底面、インナーリード17の底面と外方側面を露
出させて封止樹脂19により片面封止された構造を有し
ており、インナーリード17の封止樹脂19から略同一
面に露出した部分は外部端子20を構成し、また支持部
材11の底面は外部端子21を有して、外部端子21が
2列のグリッド状にエリア配置されているものである。
さらに支持部材11が露出しているため、搭載した半導
体素子から発せられた熱を効率よく放熱させることもで
きる。
As described above, the semiconductor device of this embodiment has the connection electrode 22 corresponding to the electrode pad of the semiconductor element mounted face-down, and is connected to the connection electrode 22 by the lead-out wiring 23 and arranged in an area. A support member 11 having an electrode 24, the electrode 24 being electrically connected to the bottom surface by an internal via to form an external terminal 21;
1, a first semiconductor element 12 is mounted face down on a connection electrode 22 via an insulating material by a bump electrode 13 provided on the surface thereof, and a second semiconductor element 15 is mounted on the back surface of the first semiconductor element 12. Are stacked and mounted by the adhesive 16,
Electrode on inner surface of second semiconductor element 15 and inner lead 1
7 is electrically connected by a thin metal wire 18, and has a structure in which the bottom surface of the support member 11, the bottom surface and the outer side surface of the inner lead 17 are exposed, and one side is sealed by a sealing resin 19. The portion of the lead 17 exposed to the substantially same surface from the sealing resin 19 constitutes the external terminal 20, and the bottom surface of the support member 11 has the external terminal 21, and the external terminals 21 are arranged in an area in a two-row grid. Is what is being done.
Further, since the support member 11 is exposed, the heat generated from the mounted semiconductor element can be efficiently radiated.

【0030】また本実施形態においては、半導体素子の
電極と外部端子との接続を金属端子により行うため、高
周波領域特性を有する半導体素子の性能を十分に発揮で
き、支持部材11の外部端子21を格子状に配列してい
ることから、多ピン半導体素子の搭載を可能とし、同時
に外部端子間の端子容量を低減できる。
In this embodiment, since the connection between the electrode of the semiconductor element and the external terminal is made by the metal terminal, the performance of the semiconductor element having high-frequency characteristics can be sufficiently exhibited. Since they are arranged in a lattice, a multi-pin semiconductor element can be mounted, and at the same time, terminal capacitance between external terminals can be reduced.

【0031】次に本実施形態の半導体装置の製造方法に
ついて、図面を参照しながら説明する。図3〜図10は
本実施形態の半導体装置の製造方法を示す図である。
Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to the drawings. 3 to 10 are views showing the method for manufacturing the semiconductor device of the present embodiment.

【0032】まず図3に示すように、第1の半導体素子
12の電極パッド上に突起電極としてバンプ電極13を
形成する。このバンプ形成方法としては、電解めっき、
スタッドバンプボンディング法を用いる。またバンプ電
極13の形状として先端を鋭角にすることにより、後工
程の支持部材の絶縁シートを貫通することが容易とな
る。またバンプ電極13の材料としては金(Au)を用
いる。
First, as shown in FIG. 3, a bump electrode 13 is formed on the electrode pad of the first semiconductor element 12 as a bump electrode. This bump formation method includes electrolytic plating,
A stud bump bonding method is used. In addition, by forming the tip of the bump electrode 13 at an acute angle, it becomes easy to penetrate the insulating sheet of the support member in a later step. Gold (Au) is used as the material of the bump electrode 13.

【0033】次に図4に示すように、フェースダウンで
搭載される半導体素子の電極パッドと対応した接続電極
を有し、その接続電極と引き回し配線により接続され、
その平面内でエリア配置された電極を有し、その電極は
内部ビアで底面に導通されて外部端子を構成している支
持部材11を用意し、その支持部材11の上面に対して
絶縁シート14を載置した後、電極にバンプ電極13を
形成した第1の半導体素子12をフェースダウンで搭載
し、支持部材11の接続電極と第1の半導体素子12の
バンプ電極13とを接続する。この時、バンプ電極13
により絶縁シート14を貫通して、支持部材11の接続
電極と接続させるものである。
Next, as shown in FIG. 4, the semiconductor device has connection electrodes corresponding to the electrode pads of the semiconductor element mounted face-down, and is connected to the connection electrodes by leading wiring.
An electrode is provided in an area within the plane, and the electrode is electrically connected to the bottom surface by an internal via to prepare a support member 11 constituting an external terminal, and an insulating sheet 14 is provided on the upper surface of the support member 11. After mounting, the first semiconductor element 12 having the bump electrode 13 formed on the electrode is mounted face down, and the connection electrode of the support member 11 and the bump electrode 13 of the first semiconductor element 12 are connected. At this time, the bump electrode 13
Thereby, it penetrates the insulating sheet 14 and is connected to the connection electrode of the support member 11.

【0034】次に図5に示すように、前工程で搭載した
第1の半導体素子12の回路面の反対面(裏面)に接着
剤16を塗布する。この接着剤16は例えば熱硬化特性
を有するものを用い、搭載する半導体素子に応じて導電
性、非導電性のいずれかを用いる。
Next, as shown in FIG. 5, an adhesive 16 is applied to the surface (back surface) opposite to the circuit surface of the first semiconductor element 12 mounted in the previous step. The adhesive 16 has a thermosetting property, for example, and is either conductive or non-conductive depending on the semiconductor element to be mounted.

【0035】次に図6に示すように、塗布した接着剤1
6を介して第1の半導体素子12上に第2の半導体素子
15をその底面側で搭載する。すなわち、第2の半導体
素子15の電極パッド面を上にして搭載する。また、第
2の半導体素子15の搭載には従来設備、工法を取り入
れられコストアップ抑制に効果がある。
Next, as shown in FIG. 6, the applied adhesive 1
6, the second semiconductor element 15 is mounted on the first semiconductor element 12 on the bottom surface side. That is, the second semiconductor element 15 is mounted with the electrode pad surface facing upward. In addition, the installation of the second semiconductor element 15 employs conventional equipment and construction methods, and is effective in suppressing an increase in cost.

【0036】次に図7に示すように、第2の半導体素子
15の電極パッドとフレーム部材のインナーリード17
とを金属細線18により電気的に接続する。この工程で
は、図8に示すようなインナーリード17を有し、支持
部材を配置できる開口領域を有したフレーム部材26を
用いる。図8はフレーム部材26の略1/2領域の平面
図である。そして、フレーム部材26の開口領域に半導
体素子を搭載した支持部材を設置し、金(Au)線等の
金属細線で接続するものである。すなわち、インナーリ
ード17を有し、支持部材11を配置できる開口領域を
有したフレーム部材26を用意し、そのフレーム部材2
6の開口領域に第1の半導体素子,第2の半導体素子が
搭載された支持部材11を配置し、第2の半導体素子の
電極パッドとフレーム部材26のインナーリード17と
を金属細線18により電気的に接続するものである。
Next, as shown in FIG. 7, the electrode pads of the second semiconductor element 15 and the inner leads 17 of the frame member are formed.
Are electrically connected by a thin metal wire 18. In this step, a frame member 26 having an inner lead 17 as shown in FIG. 8 and having an opening region in which a support member can be arranged is used. FIG. 8 is a plan view of a substantially half area of the frame member 26. Then, a support member on which the semiconductor element is mounted is installed in the opening region of the frame member 26, and is connected by a thin metal wire such as a gold (Au) wire. That is, a frame member 26 having an inner lead 17 and an opening region in which the support member 11 can be arranged is prepared.
The support member 11 on which the first semiconductor element and the second semiconductor element are mounted is arranged in the opening area of the semiconductor device 6, and the electrode pads of the second semiconductor element and the inner leads 17 of the frame member 26 are electrically connected by the thin metal wires 18. It is a thing to connect.

【0037】技術的には従来のワイヤーボンド技術を用
いることが可能である。また設備としては、ワイヤーボ
ンド設備に、半導体素子を搭載した支持部材をピックア
ップし、ワイヤーボンド領域に精度よく搬送する機能を
加える。さらに半導体素子を搭載した支持部材をヒータ
ープレート27に搭載する際、大きなダメージを与えな
いようにするために、図9に示すような支持部材の搭載
箇所に耐熱性ゴム等の衝撃を吸収する弾力性に優れた耐
熱性物質28を埋め込む。図9において29は支持部材
を真空で吸着するための真空吸着空孔である。なお図9
はフレーム部材と半導体素子を搭載した支持部材との金
属細線接続で用いるヒータープレートを示す図であり、
図9(a)は平面図であり、図9(b)は図9(a)の
C−C1箇所の断面図である。
Technically, a conventional wire bonding technique can be used. In addition, as a facility, a function of picking up a supporting member on which a semiconductor element is mounted and accurately transporting the supporting member to a wire bond area is added to the wire bond facility. Further, when mounting the support member on which the semiconductor element is mounted on the heater plate 27, in order to prevent large damage, the elasticity of absorbing the impact of heat-resistant rubber or the like at the mounting position of the support member as shown in FIG. A heat resistant material 28 having excellent heat resistance is embedded. In FIG. 9, reference numeral 29 denotes a vacuum suction hole for sucking the support member in vacuum. FIG. 9
Is a diagram showing a heater plate used for thin metal wire connection between the frame member and the support member on which the semiconductor element is mounted,
9A is a plan view, and FIG. 9B is a cross-sectional view taken along a line CC of FIG. 9A.

【0038】本実施形態の複数の半導体素子が搭載され
た支持部材11とフレーム部材26とを位置合わせし
て、配置し、金属細線で接続する工程では、支持部材1
1をフレーム部材26の開口領域に配置する際、支持部
材11が載置される箇所に支持部材11の底面を吸着す
る真空吸着空孔29と、弾性を有する耐熱性物質28と
が設けられたヒータープレート27を用い、そのヒータ
ープレート27の耐熱性物質28上に支持部材11を吸
着固定した状態で配置、接続するものである。これによ
り、金属細線で接続する際の支持部材11の上の半導体
素子に印加されるダメージを低減できるものである。
In the step of positioning and arranging the support member 11 on which a plurality of semiconductor elements are mounted and the frame member 26 according to the present embodiment and connecting them with the thin metal wire, the support member 1
When arranging 1 in the opening region of the frame member 26, a vacuum suction hole 29 for sucking the bottom surface of the support member 11 and a heat-resistant substance 28 having elasticity were provided at a place where the support member 11 was placed. The heater plate 27 is used, and the support member 11 is arranged and connected to the heat-resistant substance 28 of the heater plate 27 in a state where the support member 11 is fixed by suction. This can reduce damage applied to the semiconductor element on the support member 11 when connecting with a thin metal wire.

【0039】次に図10に示すように、支持部材11、
第1の半導体素子12,第2の半導体素子15および金
属細線18領域、インナーリード17の外囲を封止樹脂
19により封止する。この場合、支持部材11の底面、
インナーリード17の底面と外方側面を露出させた片面
封止を行う。また一般的に封止プロセスは、トランスフ
ァーモールドで行われるが、本実施形態では製造コス
ト、歩留り等を考慮した封止プロセスを選択する。
Next, as shown in FIG.
The first semiconductor element 12, the second semiconductor element 15, the region of the thin metal wire 18, and the outer periphery of the inner lead 17 are sealed with a sealing resin 19. In this case, the bottom surface of the support member 11,
One-sided sealing is performed so that the bottom surface and the outer side surface of the inner lead 17 are exposed. Generally, the sealing process is performed by transfer molding. In the present embodiment, the sealing process is selected in consideration of the manufacturing cost, the yield, and the like.

【0040】以上のような工程により、フェースダウン
で搭載される半導体素子の電極パッドと対応した接続電
極を有し、その接続電極と引き回し配線により接続さ
れ、その平面内でエリア配置された電極を有し、その電
極は内部ビアで底面に導通されて外部端子を構成してい
る支持部材と、その支持部材11上にその表面に設けた
バンプ電極13により、絶縁シート14を介して接続電
極にフェースダウンで搭載された第1の半導体素子12
と、第1の半導体素子12の裏面に積層搭載された第2
の半導体素子15と、第2の半導体素子15の表面の電
極パッドとインナーリード17とを接続した金属細線1
8と、支持部材11の底面、インナーリード17の底面
と外方側面を露出させて外囲を封止した封止樹脂19と
よりなり、インナーリード17の封止樹脂19から露出
した部分と支持部材11の底面に配列した外部端子とで
エリア状の外部端子を構成している半導体装置を得るも
のである。
According to the above steps, the connection electrodes corresponding to the electrode pads of the semiconductor element mounted face down are connected, and the connection electrodes are connected to the connection electrodes by the lead-out wiring, and the electrodes arranged in the area within the plane are connected. The electrode is connected to a connection electrode via an insulating sheet 14 by a supporting member that is electrically connected to the bottom surface by an internal via to form an external terminal, and a bump electrode 13 provided on the surface of the supporting member 11. First semiconductor element 12 mounted face down
And a second stacked and mounted on the back surface of the first semiconductor element 12.
And a metal thin wire 1 in which an electrode pad on the surface of the second semiconductor element 15 and the inner lead 17 are connected.
8 and a sealing resin 19 in which the bottom surface of the support member 11, the bottom surface and the outer side surface of the inner lead 17 are exposed, and the outer periphery is sealed, and the portion of the inner lead 17 exposed from the sealing resin 19 is supported. An external terminal arranged on the bottom surface of the member 11 and an external terminal in an area form are obtained.

【0041】次に本発明の半導体装置の別の実施形態に
ついて図面を参照しながら説明する。図11は本実施形
態の半導体装置を示す断面図である。
Next, another embodiment of the semiconductor device of the present invention will be described with reference to the drawings. FIG. 11 is a sectional view showing the semiconductor device of the present embodiment.

【0042】図11に示すように、本実施形態の半導体
装置は、図1に示したタイプの半導体装置と基本構成は
同様であるが、支持部材の断面形状が異なるものであ
る。
As shown in FIG. 11, the semiconductor device of this embodiment has the same basic structure as the semiconductor device of the type shown in FIG. 1, but has a different cross-sectional shape of the supporting member.

【0043】本実施形態の半導体装置は、フェースダウ
ンで搭載される半導体素子の電極パッドと対応した接続
電極を有し、その接続電極と引き回し配線により接続さ
れ、その平面内でエリア配置された電極を有し、その電
極は内部ビアで底面に導通されて外部端子を構成してい
る支持部材30と、その支持部材30上にその表面に設
けたバンプ電極13により、絶縁シート14を介して接
続電極にフェースダウンで搭載された第1の半導体素子
12と、第1の半導体素子12の裏面に積層搭載された
第2の半導体素子15と、第2の半導体素子15の表面
の電極パッドとインナーリード17とを接続した金属細
線18と、支持部材30の底面、インナーリード17の
底面と外方側面を露出させて外囲を封止した封止樹脂1
9とよりなり、インナーリード17の封止樹脂19から
露出した外部端子20と、支持部材30の底面に配列し
た外部端子とでエリア状の外部端子を構成している半導
体装置である。そして支持部材30の断面形状において
上部に薄肉部31を有しており、封止樹脂19の密着性
を向上させる構造を有している。
The semiconductor device of this embodiment has a connection electrode corresponding to the electrode pad of the semiconductor element mounted face down, and is connected to the connection electrode by a lead-out wiring and arranged in an area within the plane. The electrodes are electrically connected to the bottom surface by internal vias to form external terminals, and are connected via the insulating sheet 14 by the bump electrodes 13 provided on the surface of the support member 30 on the support member 30. A first semiconductor element 12 mounted face-down on the electrode, a second semiconductor element 15 stacked and mounted on the back surface of the first semiconductor element 12, an electrode pad on the surface of the second semiconductor element 15 and an inner The sealing resin 1 in which the thin metal wire 18 connected to the lead 17, the bottom surface of the support member 30, the bottom surface and the outer side surface of the inner lead 17 are exposed, and the outer periphery is sealed.
9 is a semiconductor device in which the external terminals 20 exposed from the sealing resin 19 of the inner leads 17 and the external terminals arranged on the bottom surface of the support member 30 constitute an area-shaped external terminal. The support member 30 has a thin portion 31 at the top in the cross-sectional shape, and has a structure for improving the adhesion of the sealing resin 19.

【0044】以上のように本実施形態の半導体装置は、
ダイパッド機能を有する支持部材に外部端子、引き回し
配線および半導体素子の電極パッドと接続する接続電極
を付設することにより、高周波化半導体素子および多ピ
ンを有する半導体素子を、小実装面積を確保しながら実
現できる。さらに、半導体素子を積層できるため、実装
での高集積化を可能にする。
As described above, the semiconductor device of this embodiment is
A high frequency semiconductor device and a semiconductor device having many pins are realized while securing a small mounting area by attaching an external terminal, a lead-out wiring, and a connection electrode connected to an electrode pad of the semiconductor device to a support member having a die pad function. it can. Furthermore, since semiconductor elements can be stacked, high integration in mounting is enabled.

【0045】また本実施形態の半導体装置の製造方法に
おいては、支持部材に半導体素子を搭載するとき、半導
体素子に形成した突起電極であるバンプ電極が絶縁シー
トを貫通して接続するため、絶縁シートはバンプ電極間
に隙間なく入り込み、電流リークおよび端子容量を大き
く抑制できる。また従来のダイスボンド技術およびワイ
ヤーボンド技術を用いることが可能であり、汎用性に優
れた製造方法である。
In the method of manufacturing a semiconductor device according to the present embodiment, when the semiconductor element is mounted on the support member, the bump electrode, which is a protruding electrode formed on the semiconductor element, penetrates the insulating sheet and is connected. Penetrates between the bump electrodes without any gap, thereby greatly suppressing current leakage and terminal capacitance. Further, the conventional die bonding technology and wire bonding technology can be used, and this is a manufacturing method excellent in versatility.

【0046】[0046]

【発明の効果】本発明の半導体装置は、第1の半導体素
子を搭載する支持部材に回路配線構成を施し、その支持
部材の底面にエリア状に外部端子を配列させることがで
き、多ピン、小型化に対応できるものである。また第1
の半導体素子は支持部材の電極に対して絶縁シートを貫
通して接続されており、電流リークおよび端子容量を大
きく抑制できるものであり、最短距離で外部端子と接続
され、高速化を実現できるものである。また第1の半導
体素子上に第2の半導体素子が積層搭載され、3次元モ
ジュールを構成し、高密度実装を実現できるものであ
る。そしてパッケージ底面の外側には第2の半導体素子
の外部端子が配列され、内側には第1の半導体素子の外
部端子が配列されてエリア配置されるものであり、多ピ
ン、狭ピッチに対応できるものである。
According to the semiconductor device of the present invention, the support member on which the first semiconductor element is mounted is provided with a circuit wiring structure, and external terminals can be arranged in an area on the bottom surface of the support member. It can respond to miniaturization. Also the first
Is connected to the electrode of the support member through the insulating sheet, can greatly reduce current leakage and terminal capacity, can be connected to external terminals in the shortest distance, and can achieve high speed It is. Further, a second semiconductor element is stacked and mounted on the first semiconductor element to constitute a three-dimensional module, and high-density mounting can be realized. The external terminals of the second semiconductor element are arranged outside the package bottom surface, and the external terminals of the first semiconductor element are arranged and arranged inside the area inside the package. The multi-pin, narrow pitch can be accommodated. Things.

【0047】また半導体装置の製造方法においては、支
持部材に半導体素子を搭載するとき、半導体素子に形成
した突起電極であるバンプ電極が絶縁シートを貫通して
接続するため、絶縁シートはバンプ電極間に隙間なく入
り込み、電流リークおよび端子容量を大きく抑制でき
る。また従来のダイスボンド技術およびワイヤーボンド
技術を用いることが可能であり、汎用性に優れた製造方
法を提供できるものである。
In the method of manufacturing a semiconductor device, when the semiconductor element is mounted on the support member, the bump electrode, which is a protruding electrode formed on the semiconductor element, penetrates and connects the insulating sheet. Current leak and terminal capacitance can be largely suppressed. Further, the conventional die bonding technology and wire bonding technology can be used, and a manufacturing method excellent in versatility can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態における半導体装置を示す
FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention.

【図2】本発明の一実施形態における半導体装置の支持
部材を示す図
FIG. 2 is a view showing a support member of the semiconductor device according to the embodiment of the present invention;

【図3】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 3 is a sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention;

【図4】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

【図5】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 5 is a sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention;

【図6】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention;

【図7】本発明の一実施形態における半導体装置の製造
方法を示す断面図
FIG. 7 is a sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention;

【図8】本発明の一実施形態における半導体装置の製造
方法のフレーム部材を示す平面図
FIG. 8 is a plan view showing a frame member in a method of manufacturing a semiconductor device according to an embodiment of the present invention.

【図9】本発明の一実施形態における半導体装置の製造
方法のヒータープレートを示す図
FIG. 9 is a diagram showing a heater plate in the method for manufacturing a semiconductor device according to one embodiment of the present invention.

【図10】本発明の一実施形態における半導体装置の製
造方法を示す断面図
FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the present invention;

【図11】本発明の一実施形態における半導体装置を示
す断面図
FIG. 11 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

【図12】従来の半導体装置を示す図FIG. 12 illustrates a conventional semiconductor device.

【図13】従来の半導体装置を示す図FIG. 13 illustrates a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 ダイパッド 2 半導体素子 3 導電性接着剤 4 アウターリード 5 インナーリード 6 金属細線 7 封止樹脂 8 ダイパッド 9 インナーリード 10 外部端子 11 支持部材 12 第1の半導体素子 13 バンプ電極 14 絶縁シート 15 第2の半導体素子 16 接着剤 17 インナーリード 18 金属細線 19 封止樹脂 20 外側の外部端子 21 内側の外部端子 22 接続電極 23 引き回し配線 24 電極 25 ダミー端子 26 フレーム部材 27 ヒータープレート 28 耐熱性物質 29 真空吸着空孔 30 支持部材 31 薄肉部 REFERENCE SIGNS LIST 1 die pad 2 semiconductor element 3 conductive adhesive 4 outer lead 5 inner lead 6 thin metal wire 7 sealing resin 8 die pad 9 inner lead 10 external terminal 11 support member 12 first semiconductor element 13 bump electrode 14 insulating sheet 15 second Semiconductor element 16 Adhesive 17 Inner lead 18 Fine metal wire 19 Sealing resin 20 Outer external terminal 21 Inner external terminal 22 Connection electrode 23 Leading wiring 24 Electrode 25 Dummy terminal 26 Frame member 27 Heater plate 28 Heat resistant material 29 Vacuum suction empty Hole 30 Support member 31 Thin part

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 フェースダウンで搭載される半導体素子
の電極パットと対応した接続電極を有し、前記接続電極
と引き回し配線により接続され、その平面内でエリア配
置された電極を有し、その前記電極は内部ビアで底面に
導通されて外部端子を構成している支持部材と、前記支
持部材上にその表面に設けたバンプ電極により、絶縁材
を介して前記接続電極にフェースダウンで搭載された第
1の半導体素子と、前記第1の半導体素子の裏面に積層
搭載された第2の半導体素子と、前記第2の半導体素子
の表面の電極パッドとインナーリードとを接続した金属
細線と、前記支持部材の底面、インナーリードの底面と
外方側面を露出させて外囲を封止した封止樹脂とよりな
り、前記インナーリードの前記封止樹脂から露出した部
分と前記支持部材の底面に配列した外部端子とでエリア
状の外部端子を構成していることを特徴とする半導体装
置。
The semiconductor device includes a connection electrode corresponding to an electrode pad of a semiconductor element mounted face-down, an electrode connected to the connection electrode by a lead wiring, and arranged in an area in a plane of the connection electrode. The electrode was mounted face-down on the connection electrode via an insulating material by a support member which is electrically connected to the bottom surface by an internal via to form an external terminal, and a bump electrode provided on the surface of the support member. A first semiconductor element, a second semiconductor element stacked and mounted on the back surface of the first semiconductor element, a thin metal wire connecting an electrode pad on the surface of the second semiconductor element and an inner lead, The bottom surface of the support member, the bottom surface and the outer side surface of the inner lead are made of a sealing resin that is sealed by exposing the outer periphery, and the portion of the inner lead exposed from the sealing resin and the supporting member A semiconductor device comprising an area-shaped external terminal and external terminals arranged on a bottom surface.
【請求項2】 支持部材はシリコンにより形成されてい
ることを特徴とする請求項1に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the support member is formed of silicon.
【請求項3】 支持部材の断面形状において上部に薄肉
部を有していることを特徴とする請求項1に記載の半導
体装置。
3. The semiconductor device according to claim 1, wherein the supporting member has a thin portion at an upper part in a cross-sectional shape thereof.
【請求項4】 第1の半導体素子の電極パッド上に突起
電極を形成する工程と、フェースダウンで搭載される半
導体素子の電極パッドと対応した接続電極を有し、前記
接続電極と引き回し配線により接続され、その平面内に
配置された電極を有し、前記電極は底面に導通されて外
部端子を構成している支持部材を用意する工程と、前記
支持部材の上面に対して絶縁シートを載置した後、前記
支持部材に突起電極を形成した第1の半導体素子をフェ
ースダウンで搭載し、前記支持部材の接続電極と第1の
半導体素子の突起電極とを接続する工程と、前記第1の
半導体素子の裏面に接着剤を塗布する工程と、前記接着
剤を介して第1の半導体素子上に第2の半導体素子をそ
の底面側で接着して搭載する工程と、インナーリードを
有し、前記支持部材を配置できる開口領域を有したフレ
ーム部材を用意し、前記フレーム部材の開口領域に前記
第1の半導体素子,第2の半導体素子が搭載された支持
部材を配置し、前記第2の半導体素子の電極パッドと前
記フレーム部材のインナーリードとを金属細線により電
気的に接続する工程と、前記支持部材の底面、インナー
リードの底面と外方側面を露出させ、前記支持部材、第
1の半導体素子,第2の半導体素子および金属細線領
域、インナーリードの外囲を封止樹脂により封止する工
程とよりなることを特徴とする半導体装置の製造方法。
4. A step of forming a protruding electrode on an electrode pad of a first semiconductor element, and having a connection electrode corresponding to an electrode pad of a semiconductor element mounted face down, wherein the connection electrode and the lead-out wiring are provided. A step of preparing a support member connected to and having an electrode disposed in the plane thereof, the electrode being electrically connected to the bottom surface and forming an external terminal; and placing an insulating sheet on the upper surface of the support member. Mounting the first semiconductor element having the protruding electrode formed on the support member face-down, connecting the connection electrode of the support member to the protruding electrode of the first semiconductor element; Applying an adhesive to the back surface of the semiconductor element, mounting a second semiconductor element on the first semiconductor element via the adhesive on the bottom side thereof, and an inner lead. , The support member A frame member having an opening region in which the first semiconductor element and the second semiconductor element are mounted is arranged in the opening region of the frame member; Electrically connecting the electrode pad and the inner lead of the frame member by a thin metal wire, exposing a bottom surface of the support member, a bottom surface and an outer side surface of the inner lead, and connecting the support member, the first semiconductor element, A step of sealing the outer periphery of the second semiconductor element, the thin metal wire region, and the inner lead with a sealing resin.
【請求項5】 支持部材の上面に対して絶縁シートを載
置した後、前記支持部材に突起電極を形成した第1の半
導体素子をフェースダウンで搭載し、前記支持部材の接
続電極と第1の半導体素子の突起電極とを接続する工程
では、突起電極により前記絶縁シートを貫通させ、前記
支持部材の接続電極と接続させ、突起電極間に前記絶縁
シートを入り込ませることを特徴とする請求項4に記載
の半導体装置の製造方法。
5. After placing an insulating sheet on the upper surface of the supporting member, a first semiconductor element having a protruding electrode formed on the supporting member is mounted face-down, and a connecting electrode of the supporting member and the first semiconductor element are mounted. In the step of connecting the protruding electrode of the semiconductor element, the insulating sheet is penetrated by the protruding electrode, connected to the connection electrode of the support member, and the insulating sheet is inserted between the protruding electrodes. 5. The method for manufacturing a semiconductor device according to item 4.
【請求項6】 インナーリードを有し、支持部材を配置
できる開口領域を有したフレーム部材を用意し、前記フ
レーム部材の開口領域に第1の半導体素子,第2の半導
体素子が搭載された支持部材を配置し、前記第2の半導
体素子の電極パッドと前記フレーム部材のインナーリー
ドとを金属細線により電気的に接続する工程では、前記
支持部材をフレーム部材の開口領域に配置する際、前記
支持部材が載置される箇所に前記支持部材を吸着する真
空吸着空孔と、弾性を有する耐熱性物質とが設けられた
ヒータープレートを用い、前記ヒータープレートの前記
耐熱性物質上に前記支持部材を吸着固定した状態で配置
することを特徴とする請求項4に記載の半導体装置の製
造方法。
6. A frame member having an inner lead and having an opening region in which a support member can be disposed, and a supporting member in which a first semiconductor element and a second semiconductor element are mounted in the opening region of the frame member. In the step of disposing a member and electrically connecting the electrode pad of the second semiconductor element and the inner lead of the frame member by a thin metal wire, when disposing the support member in an opening region of the frame member, A vacuum suction hole for adsorbing the support member at a position where the member is mounted, and a heater plate provided with a heat-resistant substance having elasticity, the support member is provided on the heat-resistant substance of the heater plate. The method for manufacturing a semiconductor device according to claim 4, wherein the semiconductor device is arranged in a state of being fixed by suction.
JP31924299A 1999-11-10 1999-11-10 Manufacturing method of semiconductor device Expired - Fee Related JP3649064B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31924299A JP3649064B2 (en) 1999-11-10 1999-11-10 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31924299A JP3649064B2 (en) 1999-11-10 1999-11-10 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2001135781A true JP2001135781A (en) 2001-05-18
JP3649064B2 JP3649064B2 (en) 2005-05-18

Family

ID=18108010

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3649064B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010073893A (en) * 2008-09-18 2010-04-02 Shinko Electric Ind Co Ltd Semiconductor device and production process thereof
KR20150006227A (en) 2013-07-08 2015-01-16 삼성전기주식회사 High frequency module

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010073893A (en) * 2008-09-18 2010-04-02 Shinko Electric Ind Co Ltd Semiconductor device and production process thereof
KR20150006227A (en) 2013-07-08 2015-01-16 삼성전기주식회사 High frequency module

Also Published As

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