JP2001135721A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve electromigration resistance of a semiconductor device by suppressing the occurrence of leakage currents between wirings due to diffusion of copper into an insulating film and enhancing the characteristic of a metallic layer for capable of being embedded by embedding at least a connecting hole with a barrier layer which prevents the copper diffusion and a metallic compound layer which functions as a seed for copper plating. SOLUTION: A semiconductor device is provided with a first wiring 14 formed in a substrate 10, first and second insulating films 15 and 18 formed on the substrate 10 so as to cover the wiring 14, a groove 22 formed into the second insulating film 18. The device is also provided with a connection hole 21 formed from the bottom of the groove 22 to the wiring 14 through the first insulating film 15, a metallic compound layer 24, which is formed to embed at least part of the hole 21 and to cover the internal surface of the groove as a seed layer for plating and also as a barrier layer which prevents the diffusion of a metal, and a second wiring 27 formed in the groove 22 via the compound layer 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to reducing the aspect ratio of a groove or a connection hole formed in an insulating film and then embedding a conductive material by plating to form a wiring or wiring. The present invention relates to a semiconductor device having a plug and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, aluminum alloys have been widely used as wiring materials for LSIs. However, as the demand for finer and faster LSIs has increased, aluminum alloy wirings have had sufficient performance, especially high reliability. It has become difficult to secure low resistance. As a countermeasure for this, a copper wiring technique which has higher electromigration resistance and lower resistance than aluminum alloys has attracted attention and has been studied for practical use.

[0003] In the formation of copper wiring, a method using trench wiring is expected to be promising because dry etching of copper is generally not easy. The groove wiring is formed by forming a predetermined groove in an interlayer insulating film such as silicon oxide in advance, embedding a wiring material in the groove, and removing excess wiring material by chemical mechanical polishing or the like.

As a method of manufacturing a groove wiring, electrolytic plating, chemical vapor deposition, sputtering and reflow, high-pressure reflow, and the like have been studied. However, copper having a high ability to be embedded in fine holes and grooves has been studied. Of particular importance is the electrolytic plating method.

An example of a process for embedding copper in a groove and a connection hole by an electrolytic plating method will be described below.

An interlayer insulating film made of a silicon oxide material is formed so as to cover the lower wiring, a wiring groove is formed in the interlayer insulating film and a connection hole is formed at the bottom of the wiring groove, and then the wiring groove and the connection hole are formed by sputtering. Then, for example, a film of tantalum nitride is formed as a barrier layer on the inner surface to a thickness of 30 nm. At this time, a barrier layer is also formed on the interlayer insulating film. The barrier layer made of tantalum nitride has a function of preventing copper from diffusing into an interlayer insulating film formed of silicon oxide or the like. Next, 100 n of copper was sputtered.
A copper seed layer is formed by forming a film having a thickness of m. This copper seed layer functions as a seed layer for growing copper in a subsequent electrolytic plating step.

Next, the insides of the wiring grooves and the connection holes are buried with copper by electrolytic plating of copper. Thereafter, excess copper and the barrier layer on the interlayer insulating film are removed. as a result,
Wirings and plugs are formed inside the wiring grooves and connection holes via a barrier layer.

In the above manufacturing method, the barrier layer and the copper seed layer are covered on the inner surfaces of the wiring trenches and the connection holes in order to suppress the diffusion of copper into the silicon oxide film and to realize good embedding of copper. It is important to form well.

[0009]

However, in the process of miniaturizing the wiring and filling the groove and the connection hole at the same time, the aspect ratio of the groove and the connection hole becomes high, and the barrier layer and the copper seed are formed by sputtering. It becomes difficult to form the layer with sufficient step coverage. As described above, when the step coverage becomes insufficient, copper diffuses from an insufficient portion of the step coverage into the interlayer insulating film in the wiring process after the next process or due to aging, and the diffused copper causes A current leak occurs between the wirings and the plugs, and cannot be used.

[0010] If the step coverage of the copper seed layer is insufficient, voids and the like are generated in the trenches and the connection holes, for example, and disconnection occurs due to electromigration or the like, and the product cannot be used.

As a countermeasure for this, in sputtering, improvement of the step coverage of the barrier layer and the copper seed layer by improving the apparatus has been studied. For example, there are a long-distance sputtering method in which the distance between the target and the substrate is increased, and an ionization sputtering method in which atoms to be sputtered are ionized to increase a component traveling perpendicular to the substrate. However, in these sputtering methods, if the wiring becomes finer and the aspect ratio becomes higher, there is a limit to the attachment of sputter atoms at the bottom of the via hole. In addition, since low-melting metal materials such as copper and copper alloy have inherently poor sputter coverage compared to high-melting metal compound materials such as tantalum nitride and titanium nitride, improvement by the above method is not necessarily easy. is not.

Although a method of forming a barrier layer by a chemical vapor deposition method is also known, the use of a chemical vapor deposition method in which a film is formed in a conformal manner results in a substantial aspect of grooves and connection holes. The ratio becomes high, and it becomes difficult to embed a metal into a groove or a connection hole by electrolytic plating, and there is a possibility that an embedding defect may occur.

[0013]

SUMMARY OF THE INVENTION The present invention is directed to a semiconductor device and a method of manufacturing the same to solve the above-mentioned problems.

The semiconductor device may include a first wiring formed on the substrate, an insulating film formed on the substrate so as to cover the first wiring, a groove formed in the insulating film, A connection hole formed in the insulating film so as to reach the first wiring from the bottom, and a plating seed layer and a conductive barrier layer for preventing diffusion of metal; A conductive metal compound layer formed so as to cover the inner surface of the groove, and a wiring forming layer embedded in the groove via the metal compound layer.

In the above-described semiconductor device, since the connection holes are buried in the conductive metal compound layer, the wiring forming layers are buried in the trenches with a low aspect ratio. Therefore, the wiring forming layer is buried in the groove without generating a void. Further, since the metal compound layer serves as a plating seed layer and a conductive barrier layer for preventing metal diffusion, the insulating film can be formed of a silicon oxide based insulating film, and the wiring forming layer can be formed. It can be made of copper or a copper alloy, and it is not necessary to form two layers of a barrier layer for preventing metal diffusion and a plating seed layer as in the related art.

A first method of manufacturing a semiconductor device includes a step of forming a concave portion in an insulating film on a substrate, a step of embedding a lower portion of the concave portion with a conductive material for preventing metal diffusion, and a step of forming an upper inner surface of the concave portion. Forming a conductive barrier layer that prevents metal diffusion so as to cover, forming a seed layer serving as a seed for plating on the surface of the barrier layer, and via the seed layer and the barrier layer Embedding the upper portion of the concave portion with a metal.

In the first method of manufacturing a semiconductor device, since the lower portion of the concave portion is buried with a conductive material for preventing metal diffusion, the aspect ratio of the upper portion of the concave portion when the upper portion of the concave portion is buried with metal is reduced. . Therefore, the embedding property of the metal layer is improved. Further, since the lower portion of the concave portion is buried with a conductive material for preventing metal diffusion and a conductive barrier layer for preventing metal diffusion is formed so as to cover the upper inner surface of the concave portion, copper diffuses in the insulating film. It is also possible to form with a silicon oxide based insulating film which is easy.

In a second method of manufacturing a semiconductor device, a step of forming a concave portion in an insulating film on a substrate, a step of burying a lower portion of the concave portion and covering an upper inner surface of the concave portion to prevent diffusion of metal and A step of forming a conductive metal compound layer serving as a seed for plating; and a step of embedding a metal in an upper portion of the concave portion via the metal compound layer.

In the second method of manufacturing a semiconductor device, a metal compound layer is formed to prevent diffusion of metal and to serve as a seed for plating so as to fill a lower portion of the concave portion and cover an inner surface of the upper portion of the concave portion. After that, when the upper part of the concave portion is buried with the wiring forming layer, the aspect ratio of the upper portion of the concave portion becomes low. Therefore, the embedding property of the wiring formation layer in the concave portion is improved. Further, since the lower part of the concave portion is covered with a conductive metal compound layer that prevents diffusion of metal and serves as a seed for plating and covers the inner surface of the upper portion of the concave portion, a barrier layer that prevents metal diffusion as in the related art is provided. There is no need to form two layers with a plating seed layer.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the semiconductor device according to the present invention will be described with reference to the schematic sectional view of FIG.

As shown in FIG. 1, a semiconductor element, wiring and the like (not shown) are formed on a semiconductor substrate (not shown), and a lower insulating film 11 is formed on the semiconductor substrate so as to cover them. Is formed. Thus, the substrate 10 is configured.

A groove 12 is formed in the lower insulating film 11, and a barrier layer 13 made of tantalum nitride is formed on the inner surface of the groove 12. Further, a first wiring 14 having a groove wiring structure is formed inside the groove 12 via a barrier layer 13.

Further, the first wiring 1 is formed on the lower insulating film 11.
An insulating film (hereinafter, referred to as a first insulating film) 15 covering 4
For example, it is formed of a silicon nitride film 16 and a silicon oxide film 17. Further, an insulating film (hereinafter, referred to as a second insulating film) 18 is formed on the first insulating film 15 by, for example, a silicon nitride film 19 and a silicon oxide film 20.

The silicon nitride film 16 has a function of preventing copper from diffusing from the first wiring, for example. The silicon nitride film 19 becomes, for example, an etching mask when forming a connection hole, and also becomes an etching stopper when forming a groove.

The first wiring 14 is formed on the first insulating film 15.
A connection hole 21 reaching the second insulating film 18 is formed.
A groove 22 is formed in the bottom so that the connection hole 21 is exposed at the bottom. As described above, the concave portion 23 is constituted by the groove 22 and the connection hole 21 formed at the bottom thereof.

A conductive metal compound layer 24 serving as a plating seed layer and a barrier layer for preventing metal diffusion is formed in a state of filling the inside of the connection hole 21 and covering the inner surface of the groove 22. I have. Therefore, the metal compound layer 24 forms the plug 25 inside the connection hole 21. Further, the metal compound layer 2 is provided inside the groove 22.
4, a second wiring 27 having a trench wiring structure is formed in a wiring forming layer 26 such as copper. The metal compound layer 24 is made of, for example, cobalt phosphorus tungsten or nickel phosphorus tungsten.

The first insulating film 15 is an insulating film (ILD: Inter Level Diel) between wiring layers for maintaining insulation between the first wiring 14 serving as a lower wiring and the second wiring 26 serving as an upper wiring.
ectrics). Further, the second insulating film 18 becomes an insulating film (IMD: Inter Metal Dielectrics) between the wirings that maintain the insulating property between the second wirings 26, 26 serving as upper wirings.

In the above semiconductor device, since the connection hole 21 is buried with the metal compound layer 24, the wiring forming layer 26 is buried in a state where the recess 23 has a low aspect ratio, and the second wiring is formed inside the groove 22. 27 are formed. Therefore, the wiring formation layer 26 is formed without the voids 2
3 is embedded inside. Further, the metal compound layer 24
Becomes a seed layer for plating and a barrier layer for preventing metal diffusion, so that the first insulating film 15 and the second insulating film 1
8 can be formed of a silicon oxide-based insulating film. Further, the wiring forming layer 26 can be formed of copper or a copper alloy. Further, it is not necessary to form two layers of a barrier layer for preventing metal diffusion and a plating seed layer as in the related art.

Next, an example of an embodiment according to the first manufacturing method of the present invention will be described with reference to a manufacturing process sectional view of FIG.

As shown in FIG. 2A, a lower insulating film 11 is formed on a semiconductor substrate (not shown) to cover semiconductor elements, wirings and the like (not shown) by a known semiconductor process technique. I do. The lower insulating film 11 is formed, for example, by forming an interlayer insulating film (not shown) covering the above-mentioned semiconductor element, wiring, etc. (not shown),
A silicon nitride film 31 is formed on the above-mentioned interlayer insulating film by a VD method (hereinafter, referred to as a PE-CVD method).
A silicon oxide film 32 is formed on the silicon nitride film 31 by E-CVD.

Next, using a conventional trench wiring forming technique,
A groove 12 for forming a wiring is formed in the silicon oxide film 32. Then, a barrier layer 13 for preventing diffusion of copper is formed on the inner surface of the groove 12, and copper is buried in the groove 12 via the barrier layer 13. The layer 13 is removed, and the first wiring 14 is formed inside the groove 12.

Thereafter, the first insulating film 11 is formed on the lower insulating film 11.
A first insulating film 15 covering the wiring 14 is formed. The first insulating film 15 is formed, for example, by forming a silicon nitride film 16 to a thickness of 50 nm by PE-CVD,
A first insulating film 15 is formed by forming a silicon oxide film 17 to a thickness of 500 nm by a CVD method; This first insulating film 15 is an insulating film (ILD: Inter Level Dielectrics) between wiring layers for maintaining insulation between the first wiring 14 serving as a lower wiring and a second wiring serving as an upper wiring formed later.
Becomes Further, a silicon nitride film 19 is formed on the first insulating film 15 to a thickness of 70 nm by the PE-CVD method.

Next, an opening 41 is formed in the silicon nitride film 19 serving as a mask when forming a connection hole by using a lithography technique and an etching technique.

Next, as shown in (2) of FIG.
The silicon oxide film 20 is buried in the silicon nitride film 19 by E-CVD so as to fill the opening 41.
Is formed, and the silicon nitride film 19 and the silicon oxide film 2 are formed.
0 constitutes the second insulating film 18. The second insulating film 18 is an inter-metal insulating film (IMD: Inter Metal Dielec) for maintaining insulation between second wirings to be formed later as upper wirings.
trics).

Next, as shown in FIG. 2C, a resist mask (not shown) serving as an etching mask for forming a groove is formed by resist coating and lithography techniques, and thereafter, etching is performed using the resist mask. The groove 22 is formed by, for example, anisotropically etching the second insulating film 18 (silicon oxide film 20). Further, etching is further performed using the silicon nitride film 19 as a mask, and a connection hole 21 is formed in the silicon oxide film 17. This etching is stopped on the silicon nitride film 16.

The etching of the silicon oxide film 17 and the silicon oxide film 20 is performed using, for example, a magnetron type etching apparatus. An example of the etching conditions is that octafluorocyclobutane (C ₄ F) is used as an etching gas.
₈ ) (supply flow rate is, for example, 14 cm ³ / min), and carbon monoxide (CO) (supply flow rate is, for example, 250 cm ³ / mi).
n), argon (Ar) (supply flow rate is 100 cm, for example)
³ / min) and oxygen (O ₂ ) (supply flow rate is 2
cm ³ / min), the pressure of the etching atmosphere was set to 5.3 Pa, and the etching power was set to 1.60 kW.

Further, as shown in FIG. 2D, the silicon nitride film 19 and the silicon nitride film 16 are etched using the silicon oxide film 20 and the silicon oxide film 17 as an etching mask to form a second insulating film 18. In addition, a groove 22 that is to be the upper part of the concave portion is formed, and a connection hole 21 that communicates with the first wiring 14 that is to be the lower part of the concave portion is formed in the first insulating film 15. Thus, the recess 23 is formed by the connection hole 21 and the groove 22.

Next, as shown in FIG. 2 (5), the recesses 2 are formed with a metal compound layer 24 of a conductive material for preventing metal diffusion.
3 (the connection hole 21) is buried. That is, the metal compound layer 24 is deposited from the surface of the first wiring 14 by the electroless plating method to fill the inside of the connection hole 21 to form the plug 25. The plug 25 may be formed so as to swell toward the groove 22 from the connection hole 21 or may be formed so as to leave the upper portion of the connection hole 21. For the metal compound layer 24, cobalt phosphorus tungsten or nickel phosphorus tungsten is used.

In the electroless plating in which the metal compound layer 24 is formed of cobalt phosphorus tungsten, for example, ammonium tungstate (10 g / L), cobalt chloride (30 g / L), and ammonium hypophosphite (2
0 g / L), ammonium oxalate (80 g / L) and a surfactant, the temperature of the plating solution was adjusted to 90 ° C., and the pH of the plating solution was adjusted to 8.5 to 10.5.

Next, as shown in FIG. 2 (6), the recess 23 on the plug 25 is formed by, for example, sputtering.
A barrier layer 51 for preventing diffusion of copper is formed by depositing, for example, tantalum nitride to a thickness of 30 nm so as to cover the inner surface of the (groove 22). At this time, a barrier layer 51 is also deposited on the second insulating film 18. The sputtering conditions for the barrier layer 51 include, as an example, argon (Ar) as a process gas, a pressure of a film formation atmosphere of 0.4 Pa, a film formation temperature of 100 ° C., and a DC applied voltage to a target of 6 k.
V was set.

Further, by sputtering, a seed layer 52 serving as a seed for plating is formed on the surface of the barrier layer 51 by depositing copper to a thickness of, for example, 150 nm. that time,
A seed layer 52 is also deposited on the barrier layer 51 on the second insulating film 18. The sputtering conditions of the seed layer 52 are, for example, argon (Ar) as a process gas.
, The pressure of the film forming atmosphere is 0.2 Pa, and the film forming temperature is 1
At 00 ° C., the DC applied voltage to the target was set at 12 kV.

Next, the concave portion 23 is filled with a wiring forming layer 53 made of copper, for example, by electrolytic copper plating.
At this time, a copper plating layer 53 is also deposited on the seed layer 52 on the second insulating film 18. As an example of the electroplating conditions for forming the copper plating layer 53, a copper sulfate-based copper electroplating solution is used as a plating solution, a plating temperature is 18 ° C., a plating current value is 2.83 A, and a plating time is 4 hours. The time was set to 30 minutes and copper was deposited to a thickness of 1.0 μm. In this manner, the wiring forming layer 54 including the copper plating layer 53 and the plating seed layer 52 is embedded in the recess 23 through the barrier layer 51.

Thereafter, for example, by chemical mechanical polishing,
Excess copper plating layer 53, seed layer 52 and barrier layer 51 on second insulating film 18 are removed. As an example of the chemical mechanical polishing conditions, a polishing pad having a laminated structure of a nonwoven fabric and an independent foam is used, an alumina-containing slurry obtained by adding hydrogen peroxide to a polishing slurry is used, and the supply flow rate of the slurry is 100 cm ^3. / Min, the slurry temperature is 2
5 ° C. to 30 ° C., the polishing pressure was 98 Pa, the rotation speed of the polishing platen was 30 rpm, and the rotation speed of the polishing head was 30 rpm. As a result, as shown in FIG.
1 is formed of a metal compound layer 24, a plug 25 connected to the first wiring 14 is formed, and a groove 2 above the plug 25 is formed.
The second wiring 27 connected to the plug 25 via the barrier layer 51 is formed in the wiring forming layer 54 inside the wiring 2.

In the first method for manufacturing a semiconductor device, instead of forming the barrier layer 51 and the sheet layer 52, a one-layer film serving as a plating seed layer and a barrier layer for preventing metal diffusion is used. For example, a cobalt phosphotungsten film or a nickel phosphotungsten film may be formed in one film forming step.

In the first method of manufacturing a semiconductor device, the metal compound layer 24, which is harder to diffuse into the insulating film than copper, is formed in the lower portion (the connection hole 21) of the concave portion 23 where the adhesion of the seed layer 52 is most likely to deteriorate. When the upper portion (groove 22) of the concave portion 23 is filled with the seed layer 52 and the copper plating layer 53, the aspect ratio of the upper portion of the concave portion 23 becomes low.
Therefore, the coverage of the seed layer 52 and the copper plating layer 53 is increased, and the embedding of the copper plating layer 53 by electrolytic plating or electroless plating is improved. Therefore, generation of voids is reduced, and electromigration resistance is improved. Further, since the connection holes 21 are buried with the metal compound layer 24 of a conductive material for preventing metal diffusion and the barrier layer 52 for preventing copper diffusion is formed so as to cover the inner surface of the groove 22, the second insulating film is formed. 18 can be formed of a silicon oxide film 20 in which copper is easily diffused.

Instead of forming the barrier layer 51 and the sheet layer 52, for example, a cobalt phosphotungsten film or a nickel phosphotungsten film is used as a plating seed layer and a single layer film serving as a barrier layer for preventing metal diffusion. The film may be formed on the inner surface of the upper portion (groove 22) of the concave portion 23 in each of the film forming steps. In this case, the number of film forming steps can be reduced. Further, the above manufacturing method can be applied to a so-called borderless contact structure in which the diameter of the connection hole 21 and the width of the groove 22 are substantially the same.

Next, an example of an embodiment according to a second manufacturing method of the present invention will be described with reference to a manufacturing process sectional view of FIG.

As shown in (1) of FIG. 3, in the same manner as in the manufacturing method described with reference to (1) to (4) of FIG.
A lower insulating film 11 covering a semiconductor element, wiring, etc. (not shown) formed on a semiconductor substrate (not shown) is replaced with an interlayer insulating film (not shown) covering, for example, the semiconductor element, wiring, etc. (not shown). ), A silicon nitride film 31 and a silicon oxide film 32 are laminated thereon. After that, a groove 12 for forming a wiring is formed in the silicon oxide film 32. Next, a barrier layer 13 for preventing the diffusion of copper is formed on the inner surface of the groove 12.
Is formed, and copper is buried in the trench 12 through the barrier layer 13. Then, excess copper and the barrier layer 13 on the silicon oxide film 32 are removed, and the first wiring is formed in the trench 12. 14 is formed.

Thereafter, the first insulating film 11 is formed on the lower insulating film 11.
A first insulating film 15 is formed by laminating a silicon nitride film 16 and a silicon oxide film 17 covering the wiring 12 of FIG. Further, a silicon nitride film 19 is formed on the first insulating film 15 to a thickness of 70 nm.
Formed to a thickness of Next, an opening 41 is formed in the silicon nitride film 19 serving as a mask for forming a connection hole. Next, the opening 41 is formed on the silicon nitride film 19.
The silicon oxide film 20 is formed so as to be embedded therein, and the silicon nitride film 19 and the silicon oxide film 20 constitute the second insulating film 18.

Next, a groove 22 is formed by, for example, anisotropically etching the second insulating film 18 (silicon oxide film 20). Further, etching is further performed using the silicon nitride film 19 as a mask, and a connection hole 21 is formed in the silicon oxide film 17. Further, the silicon nitride film 19 is formed using the silicon oxide film 20 and the silicon oxide film 17 as an etching mask.
And the silicon nitride film 16 is etched to form a groove 22 in the second insulating film 18 as an upper portion of the concave portion, and a connection hole 21 in the first insulating film 15 to communicate with the first wiring 14 in the lower portion of the concave portion. To form Thus, the recess 23 is formed by the connection hole 21 and the groove 22.

Next, as shown in FIG. 3B, a catalyst activation treatment is performed by depositing a metal having a catalytic ability on the surface to be plated. Specifically, for example, the surface to be plated is coated with palladium chloride (for example, 0.1 g / L to 0.5 g).
/ L) and stannous chloride (for example, 1 g / L to 25 g / L)
And a hydrochloric acid (for example, 100 mL / L to 300 mL / L) for 2 minutes to 5 minutes by subjecting to an aqueous solution (liquid temperature of, for example, 15 ° C. to 60 ° C.). By soaking for 1 to 3 minutes, stannous chloride is removed, and palladium is deposited as a metal having catalytic ability on the surface to be plated.

Thereafter, a metal compound layer 24 is deposited on the inner surfaces of the connection holes 21 and grooves 22 to be plated by electroless plating, and the inside of the connection holes 21 is filled with the metal compound layer 24 to form plugs 25. At the same time, the inner surface of the groove 22 is covered with the metal compound layer 24. At that time, the metal compound layer 24 is also formed on the second insulating film 18. For the metal compound layer 24, cobalt phosphorus tungsten or nickel phosphorus tungsten is used.

Next, as shown in FIG. 3C, the groove 22 is filled with a wiring forming layer 26 made of copper, for example, by electrolytic plating of copper. At this time, a wiring forming layer 26 is also deposited on the metal compound layer 24 on the second insulating film 18. As an example of the electrolytic plating conditions for forming the wiring forming layer 26, a copper sulfate-based copper electrolytic plating solution is used as a plating solution, a plating temperature is 18 ° C., a plating current value is 2.83 A, and a plating time is 4 hours. Set to 30 minutes, 1.0
Copper was deposited to a thickness of μm.

Thereafter, for example, by chemical mechanical polishing,
Excess wiring formation layer 26 and metal compound layer 24 on second insulating film 18 are removed. As an example of the chemical mechanical polishing conditions, a polishing pad having a laminated structure of a nonwoven fabric and an independent foam is used, an alumina-containing slurry obtained by adding hydrogen peroxide to a polishing slurry is used, and the supply flow rate of the slurry is 100 cm ^3. / Min, the temperature of the slurry is 25 ° C.-30
° C, polishing pressure 98Pa, polishing platen rotation speed 30rpm
m, the number of revolutions of the polishing head was set to 30 rpm.

As a result, as shown in (4) of FIG.
A plug 25 connected to the wiring 14 is formed. The wiring 25 is formed of a wiring forming layer 26 through a metal compound layer 24 inside the groove 22 above the plug 25.
5 is formed.

In the second method of manufacturing a semiconductor device, the lower portion (the connection hole 21) of the concave portion 23 is buried and the concave portion 2 is formed.
Since a conductive metal compound layer 24 which prevents metal diffusion and serves as a seed for plating is formed so as to cover the inner surface of the upper portion (groove 22) of 3, the groove 22 is thereafter filled with a wiring forming layer 26. In this case, the aspect ratio of the concave portion 23 becomes low. Therefore, the embedding property of the wiring forming layer 26 into the recess 23 is improved. Therefore, generation of voids is reduced, and electromigration resistance is improved. In addition, since the connection hole 21 is buried with the metal compound layer 24 and the inner surface of the groove 22 is covered, it is necessary to form two layers of a barrier layer for preventing metal diffusion and a plating seed layer as in the related art. Disappears.

[0057]

As described above, according to the semiconductor device of the present invention, the connection holes are buried with the conductive metal compound layer which becomes the seed layer for plating and the barrier layer for preventing metal diffusion. Current leakage can be reduced. In addition, since the connection holes are buried in the metal compound layer, the aspect ratio of the groove where the connection hole is formed is in a low state, so that no void is generated in the second wiring formed in the groove. . Therefore, the second wiring has high electromigration resistance, and the reliability of the wiring can be improved.

According to the first manufacturing method of the present invention, the lower portion of the concave portion where the adhesion of the seed layer is most likely to be deteriorated is buried with a conductive material for preventing metal diffusion, so that current leakage can be reduced. As a result, the aspect ratio of the upper portion of the concave portion can be reduced. Therefore, since the upper portion of the concave portion can be buried with metal without generating a void, the electromigration resistance can be improved,
A highly reliable wiring structure can be formed. Also,
Since the lower portion of the recess is filled with the conductive material and the inner surface of the upper portion of the recess is covered with a conductive barrier layer that prevents metal diffusion, the insulating film can be formed of a silicon oxide insulating film in which copper is easily diffused. become.

According to the second manufacturing method of the present invention, the lower portion of the concave portion is buried with a conductive metal compound layer serving as a seed for plating while preventing diffusion of metal, so that current leakage can be reduced and the concave portion of the concave portion can be formed. The upper aspect ratio can be reduced. Therefore, the recess can be filled with metal without generating a void, so that electromigration resistance can be improved and a highly reliable wiring structure can be formed. Further, since the metal compound layer is formed on the lower inner portion of the concave portion and the inner surface of the upper portion of the concave portion, copper or a copper alloy can be used for the metal,
Further, a silicon oxide-based insulating film can be used as the insulating film.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a manufacturing process sectional view showing an embodiment according to a first manufacturing method of the present invention.

FIG. 3 is a sectional view showing a manufacturing process according to an embodiment of the second manufacturing method of the present invention.

[Explanation of symbols]

10: substrate, 14: first wiring, 15: first insulating film,
18 ... second insulating film, 21 ... connection hole, 22 ... groove, 24 ...
Metal compound layer, 26 ... Wiring forming layer

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 4M104 BB32 BB39 DD37 DD52 DD53 FF18 FF22 HH13 5F033 HH07 HH11 HH15 HH32 JJ01 JJ07 JJ15 KK11 MM01 MM12 MM13 NN01 PP15 PP27 PP28 PP33 QQ09 QQ10 QSQQ XXQ XX33

Claims (11)

[Claims] A first wiring formed on the substrate, an insulating film formed on the substrate so as to cover the first wiring, a groove formed in the insulating film, and a bottom of the groove. A connection hole formed in the insulating film so as to reach the first wiring, and a plating seed layer and a barrier layer for preventing metal diffusion, which cover the connection hole and cover the inner surface of the groove. A semiconductor device, comprising: a conductive metal compound layer formed in a state in which the metal compound layer is formed; and a second wiring formed in the groove via the metal compound layer. 2. The semiconductor device according to claim 1, wherein said metal compound layer is made of cobalt phosphorus tungsten or nickel phosphorus tungsten. 3. A step of forming a recess in an insulating film on a substrate, a step of embedding a lower portion of the recess with a conductive material for preventing metal diffusion, and a step of diffusing metal so as to cover an upper inner surface of the recess. A step of forming a conductive barrier layer to prevent the formation, a step of forming a seed layer serving as a seed for plating on the surface of the barrier layer, and embedding an upper portion of the recess with a metal via the seed layer and the barrier layer. And a method of manufacturing a semiconductor device. 4. The barrier layer and the sheet layer serve as a plating seed layer and a barrier layer for preventing metal diffusion.
4. The method for manufacturing a semiconductor device according to claim 3, wherein the film is formed as a layer film in a single film forming step. 5. In the step of forming a concave portion in the insulating film on the substrate, a groove is formed in the insulating film to form an upper portion of the concave portion and a wiring provided on the substrate from the bottom of the groove. Forming a lower portion of the concave portion by forming a contact hole reaching the lower portion, and embedding the lower portion of the concave portion with a conductive material that prevents diffusion of the metal, wherein the metal is diffused from a wiring surface provided on the substrate. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a conductive material to be prevented is selectively deposited to fill a lower portion of the recess. 6. The method of manufacturing a semiconductor device according to claim 3, wherein cobalt phosphotungsten or nickel phosphotungsten is used as the conductive material for preventing diffusion of the metal. 7. The method of manufacturing a semiconductor device according to claim 4, wherein a cobalt phosphotungsten film or a nickel phosphotungsten film is used as a plating seed layer and a single layer film serving as a barrier layer for preventing metal diffusion. . 8. A step of forming a concave portion in an insulating film on a substrate, comprising: a step of burying a lower portion of the concave portion and covering an upper inner surface of the concave portion; A method for manufacturing a semiconductor device, comprising: a step of forming a metal compound layer; and a step of embedding a metal in an upper portion of the recess through the metal compound layer. 9. The method according to claim 8, wherein the step of forming the concave portion in the insulating film on the substrate includes forming a groove in an upper portion of the insulating film and forming a connection hole in a bottom portion of the groove. A method for manufacturing a semiconductor device. 10. The method for manufacturing a semiconductor device according to claim 8, wherein cobalt metal or nickel metal tungsten is used for the metal compound layer. 11. The method according to claim 8, wherein the metal compound layer is formed by electroless plating.