JP2001128028A - Synchronizing signal output circuit, synchronizing signal output method, recording medium and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a precise vertical syncitonizing signal from a composite synchronizing signalto which the vertical synchronizing signal and a horizontal synchronizing signal are composed. SOLUTION: The edge of a composite sinchronizing signal (Fig. 7 (A)) is detected and a count value (Fig. 7 (C)) is increased while resetting is executed at the detection timing (Fig. 7 (B)) of the edge. When a count value is overflowed, the composite synchronizing signal is latched at overflowed timing (Fig. 7 (D)) and the latched value (drawing 7 (E)) is outputted as a vertical synchronizing signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a synchronizing signal output circuit, a synchronizing signal output method, a recording medium, and a display device, and more particularly to, for example, synchronizing a horizontal sync signal and a vertical sync signal with a composite sync signal. In addition, the present invention relates to a synchronization signal output circuit, a synchronization signal output method, a recording medium, and a display device that are capable of preventing loss of synchronization and image fluctuation when displaying an image.

[0002]

2. Description of the Related Art FIG. 1 shows an example of a configuration of a conventional vertical synchronizing signal separating circuit.

This vertical synchronizing signal separating circuit is, for example, for a multi-sync display, and comprises an up-down counter 1 and a comparator 2.

The up-down counter 1 receives a composite sync signal and a clock. When the composite sync signal is at the H (High) level (1), for example, the up / down counter 1 increments the count value by one in synchronization with the clock,
When the composite sync signal is at the L (Low) level (0), for example, the count value is set to 1 in synchronization with the clock.
The count value is decremented by 1 and the resulting count value is output to the comparator 2.

The clock has a frequency sufficiently higher than any of the horizontal synchronizing signal and the vertical synchronizing signal contained in the composite sync signal and is asynchronous with the composite sync signal.

A predetermined threshold value is supplied to the comparator 2 in addition to the count value of the up / down counter 1. The comparator 2 compares the count value with a predetermined threshold, and outputs the comparison result as a vertical synchronization signal.

Next, the operation of the vertical synchronizing signal separation circuit of FIG. 1 will be described with reference to the timing chart of FIG.

For example, when a composite sync signal as shown in FIG. 2A is input to an up / down counter 1 of a vertical synchronizing signal separation circuit, the up / down counter 1 operates during a period when the composite sync signal is at H level. , The count value is incremented (counted up) by one in synchronization with the clock, and the count value is decremented (counted down) by one in synchronization with the clock during the period when the composite sync signal is at the L level. As a result, from the up / down counter 1,
A count value as shown in FIG.

When the up / down counter 1 counts up to a certain upper limit value, it does not count up to a larger value. Further, when the up / down counter 1 counts down to a certain lower limit (for example, 0), it does not count down to a smaller value.

As shown in FIG. 2B, the comparator 2 compares the count value from the up / down counter 1 with a predetermined threshold value, and when the count value is equal to or greater than (greater than) the predetermined threshold value. When the H level is less than (or less than) a predetermined threshold, the L level is output as a vertical synchronization signal. As a result, FIG.
A vertical synchronization signal as shown in FIG.

As described above, in the vertical synchronizing signal separation circuit of FIG. 1, the up-down counter 1 generates the vertical synchronizing signal by smoothing the composite sync signal equivalently.

[0012]

FIG. 2 (A)
When the composite sync signal as shown in (1) is input, the up / down counter 1 reaches the maximum value in the pulse portion of the vertical synchronization signal having a relatively large pulse width, and the falling edge of the pulse of the vertical synchronization signal After that, count down. However, immediately after the falling edge of the pulse of the vertical synchronization signal, since the count value is large, the countdown is performed, and immediately after the pulse falls below the threshold, a pulse of the horizontal synchronization signal having a relatively small pulse width appears. Therefore, when the count value is counted up, the count value may become equal to or higher than the threshold value again.

For this reason, as shown in FIG. 2C, one or more pulses corresponding to the horizontal synchronizing signal are output from the comparator 2 after the pulse of the original vertical synchronizing signal. This causes image disturbance due to loss of synchronization. Further, in the multi-sync display, the vertical synchronization frequency is measured based on the output of the vertical synchronization signal separation circuit. The above-described phenomenon has caused the frequency measurement to be erroneous.

The up / down counter 1 counts up or down in accordance with the level of the composite sync signal. Therefore, the up / down counter 1 counts down due to jitter of the composite sync signal and dull rising and falling edges thereof. There has been a problem that a section in which the count-up or count-down occurs fluctuates, and jitter occurs in the vertical synchronization signal output from the comparator 2.

That is, FIG. 3 shows an enlarged portion of the composite sync signal in the section D in the timing chart of FIG. FIG. 3A shows a composite sync signal, and FIG. 3D shows a clock counted by the up / down counter 1.

In the case where the composite sync signal has jitter and its rising edge and falling edge are dull, at the edge of the composite sync signal,
During the period in which the up / down counter 1 counts up or counts down, an error of one clock (or more) may occur.

Now, in FIG. 3, from time T ₁ , T ₂ ,
After the lapse of T _3, consider the operation of the up-down counter 1 leading to up to the time _{T 4 (T 1 <T 2} <T 3 <T 4).

First, in a case where one clock of the error is included in the count-up period, FIG.
As shown in (B), the count value is counted up by α clocks during the H level of the composite sync signal from time T ₁ to T _2, and the composite sync signal from time T ₂ to T ₃ in the period of L level, it is counted down by β-number of clocks in the period of L level of the composite sync signal from time T ₃ to T _4, and is counted up by γ number of clocks.

In this case, in the countdown period,
When one clock of the error comes to be included, FIG.
As shown in, the count value in the period of H level of the composite sync signal from the time T ₁ to T _2, is counted up by the alpha-2 clocks, T ₃ from the time T _2,
In the L level period of the composite sync signal up to
+2 clocks are counted down, and the time T
In the period of L level of the composite sync signal from ₃ to T _4, it will be incremented by gamma-1 clocks.

The error of the clock counted up or down in each period accumulates on the count value of the up / down counter 1, so that the error shown in FIG.
In the case of (B) and FIG 3 (C), and during the period from time T ₁ to T _4, the count value, 5 (= 2 + 2 + 1) clock error occurs.

Further, as described above, since the clock and the composite sync signal are not synchronized, the error of the count value varies in the range of 0 to 5 due to their phase relationship. Jitter occurs in the vertical synchronizing signal output from the second sync signal.

The jitter of the vertical synchronizing signal causes a problem such as vertical image fluctuation at the time of displaying an image.

The present invention has been made in view of such a situation, and it is an object of the present invention to prevent loss of synchronization, vertical image shaking, and the like.

[0024]

A synchronous signal output circuit according to the present invention comprises an edge detecting means for detecting an edge of a pulse in an input signal, and an edge detecting timing by the edge detecting means for repeating measurement of a predetermined time. It is characterized by comprising a measuring means to be reset, and a latch means for latching an input signal and outputting as a synchronizing signal every time a predetermined time is measured by the measuring means.

The measuring means can measure a predetermined time by repeating counting from the first value to the second value in synchronization with a predetermined clock.

Further, the measuring means can reset the count value of the clock to the first value at the edge detection timing by the edge detecting means.

The input signal may be a signal obtained by combining a horizontal synchronization signal and a vertical synchronization signal. In this case, the synchronization signal may be a vertical synchronization signal.

The predetermined time may be longer than the pulse width of the horizontal synchronizing signal.

Further, the predetermined time can be shorter than the interval from one pulse of the horizontal synchronizing signal to the next pulse.

According to the synchronous signal output method of the present invention, there is provided an edge detecting step for detecting an edge of a pulse in an input signal, and a measuring step for resetting at an edge detecting timing in the edge detecting step for repeating measurement of a predetermined time. And a latch step of latching an input signal every time a predetermined time is measured in the measurement step and outputting the input signal as a synchronization signal.

According to the recording medium of the present invention, there is provided an edge detecting step for detecting an edge of a pulse in an input signal, a measuring step for resetting at an edge detecting timing in the edge detecting step for repeating measurement of a predetermined time, And a latch step of latching an input signal every time a predetermined time is measured in the step and outputting the latched signal as a synchronization signal.

The display device of the present invention comprises: edge detecting means for detecting an edge of a pulse in an input signal; measuring means for repeating measurement of a predetermined time; resetting at an edge detection timing by the edge detecting means; Latch means for latching an input signal and outputting it as a synchronization signal every time a predetermined time is measured by the means.

In the synchronous signal output circuit, the synchronous signal output method, the recording medium, and the display device according to the present invention, the edge of the pulse in the input signal is detected, and a predetermined time is measured while resetting at the edge detection timing. Is repeated. Then, every time the predetermined time is measured, the input signal is latched and output as a synchronization signal.

[0034]

FIG. 4 shows a configuration example of an embodiment of a multi-sync display for a computer to which the present invention is applied.

The multi-sync display includes, for example, an analog RGB (Red, Green, Blue) video signal (image signal), a vertical synchronizing signal and a horizontal synchronizing signal for the video signal, or a composite sync signal obtained by synthesizing them. Is entered.

When the vertical synchronizing signal and the horizontal synchronizing signal are input separately instead of the composite sync signal, the vertical synchronizing signal is supplied to the terminal 11V and the horizontal synchronizing signal is supplied to the terminal 11H.
, Respectively. The vertical synchronizing signal is supplied to the terminal 12a of the switch 12, and the horizontal synchronizing signal is
The signal is supplied to the terminal 12 b of the switch 12, the frequency measurement circuit 14, and the peripheral device 15.

When the vertical synchronizing signal and the horizontal synchronizing signal are inputted separately, the switch 12 is connected to the terminal 12
a is selected, and therefore, the vertical synchronization signal supplied to the terminal 11V is supplied to the vertical synchronization signal separation circuit 13 via the switch 12. In the vertical synchronizing signal separation circuit 13, a process described later is performed on the vertical synchronizing signal supplied thereto, and the processed signal is supplied to the frequency measuring circuit 14 and the peripheral device 15.

On the other hand, when a composite sync signal obtained by combining a vertical synchronizing signal and a horizontal synchronizing signal is input to the multi-sync display, the composite sync signal is supplied to a terminal 11H. And
The composite sync signal is supplied to the terminal 12b of the switch 12, the frequency measurement circuit 14,
And the peripheral device 15.

When a composite sync signal is input, the switch 12 selects the terminal 12b, and therefore, the composite sync signal is
Is supplied to the vertical synchronizing signal separation circuit 13 through The vertical synchronizing signal separating circuit 13 separates (generates) the vertical synchronizing signal by performing processing described later on the composite sync signal supplied thereto, and the frequency measuring circuit 14 and the peripheral device 15 Supplied to

The frequency measuring circuit 14 measures the vertical synchronizing frequency and the horizontal synchronizing frequency based on the signals supplied thereto (the vertical synchronizing signal and the horizontal synchronizing signal, or the vertical synchronizing signal and the composite synchronizing signal). Centr
al Processing Unit) 16.

On the other hand, the peripheral device 15 includes a synchronization circuit 15A,
It comprises a deflection correction waveform generation circuit 15B, a video amplifier 15C, and an OSD (On Screen Display) circuit 15D, in which the vertical synchronization signal and the horizontal synchronization signal, or the vertical synchronization signal and the composite sync signal, as described above. In addition to being supplied, a video signal is also supplied.

A vertical synchronizing signal and a horizontal synchronizing signal or a vertical synchronizing signal and a composite sync signal are input to the synchronizing circuit 15A, and the synchronizing circuit 15A corrects the deflection in the deflection correcting waveform generating circuit 15B based on those signals. Controls waveform generation timing. The deflection correction waveform generation circuit 15B generates a deflection correction waveform based on the output of the synchronization circuit 15A, and supplies the deflection correction waveform to the deflection circuit 19. Deflection circuit 19
Drives the deflection yoke coil 20A of the CRT (Cathode Ray Tube) 20 according to the deflection correction waveform from the deflection correction waveform generation circuit 15B.

A video signal is input to the video amplifier 15C. The video amplifier 15C amplifies the video signal and
Supply to RT20. Thus, on the CRT 20, the electron beam corresponding to the video signal is scanned by the deflection yoke coil 20A in a so-called raster scan order, and a video (image) corresponding to the video signal is displayed.

The OSD circuit 15D generates, for example, OSD data for OSD display of a display state and the like in accordance with an operation of a front panel control switch 18A, which will be described later, and supplies the OSD data to the video amplifier 15C. In this case, in the video amplifier 15C, for example, OSD data is superimposed (superimposed) on the video signal.
Is supplied to the CRT 20 and displayed.

The control input / output device 18 comprises a front panel control switch 18A and a factory adjustment communication device 18B. The front panel control switch 18A is provided, for example, on the front of the display, and
It is operated when adjusting the display position of the image in the. An operation signal corresponding to the operation of the front panel control switch 18A is supplied to the CPU 16.

The factory adjustment communication device 18B functions as an interface for communicating the setting data with a computer at the factory when various settings of the display are made at the factory. The data is received from the factory computer and supplied to the CPU 16, and the data output by the CPU 16 is transmitted to the factory computer.

The CPU 16 has an EEPROM (Electricall
By executing the program stored in the Erasable Programmable Read Only Memory (17), the synchronization circuit 15A constituting the peripheral device 15 and the deflection correction waveform generation are generated based on the vertical synchronization frequency and the horizontal synchronization frequency from the frequency measurement circuit. The circuit 15B, the video amplifier 15C, and the OSD circuit 15D are controlled, so that images of various vertical synchronization frequencies and horizontal synchronization frequencies are displayed on the CRT 20. Further, the CPU 16 controls the peripheral device 15 based on a signal from the control input / output device 18.

The EEPROM 17 stores programs for the CPU 16 to perform various processes and necessary data.

FIG. 5 shows an example of the configuration of the vertical synchronizing signal separating circuit 13 shown in FIG.

In the following, the vertical synchronizing signal separating circuit 1
The description will be made assuming that the signal input to No. 3 is a composite sync signal. However, the vertical synchronization signal separation circuit 13
Does not affect the operation of the vertical synchronizing signal separation circuit 13 even if the signal inputted to the vertical synchronizing signal is a vertical synchronizing signal. That is, the vertical synchronizing signal separation circuit 13 can output a vertical synchronizing signal, which will be described later, regardless of whether the input signal is a composite sync signal or a vertical synchronizing signal.

The edge detection circuit 31 is supplied with a composite sync signal and a clock. The clock is, for example, a frequency sufficiently higher than any of the horizontal synchronizing signal and the vertical synchronizing signal included in the composite sync signal, and is asynchronous with the composite sync signal.

The edge detection circuit 31 operates in synchronization with the clock supplied thereto, and detects edges (rising edge, falling edge) of the composite sync signal. When detecting the edge of the composite sync signal, the edge detection circuit 31 outputs a reset signal to the up counter 32 at that timing.

As described above, the up counter 32 is supplied with the reset signal from the edge detection circuit 31 and also with the same clock as that supplied to the edge detection circuit 31. Then, the up-counter 32 repeatedly counts, for example, from 0 to a predetermined value MAX in synchronization with the clock, thereby measuring a predetermined time. That is, the up counter 32
Changes the count value from 0 to 1 in synchronization with the clock.
Increment by one. When the count value reaches MAX and the next clock is received, the up counter 32 overflows, outputs a latch pulse to the data latch circuit 33, and returns the count value to zero.
Accordingly, the up counter 32 basically stores the data latch circuit 33 every time the time corresponding to MAX elapses.
, A latch pulse is output.

When receiving a reset signal from the edge detection circuit 31, the up counter 32 resets its count value to 0, and repeats incrementing the count value again in synchronization with the clock. Here, the up counter 32 receives the reset signal,
When the count value is reset, no latch pulse is output.

The data latch circuit 33 is supplied with a latch pulse from the up counter 32 and also with a composite sync signal. Then, the data latch circuit 33 latches the composite sync signal at the timing when the latch pulse is supplied from the up counter 32, and outputs the latched value as a vertical synchronization signal.

Next, the operation of the vertical synchronizing signal separation circuit 13 of FIG. 5 will be described with reference to FIG.

First, the operation of the edge detection circuit 31 will be described with reference to the flowchart of FIG.

In step S1, the edge detection circuit 31 determines whether an edge (rising edge or falling edge) of the composite sync signal has been received. If it is determined in step S1 that the edge of the composite sync signal has not been received, the process returns to step S1. If it is determined in step S1 that an edge of the composite sync signal has been received, the process proceeds to step S2, where a reset signal is output to the up counter 32. Then, the process returns to step S1, and thereafter, the same processing is repeated.

Next, the operation of the up counter 32 will be described with reference to the flowchart of FIG.

In the up counter 32, step S11
, The count value C is initialized to, for example, 0, and the process proceeds to step S12 to determine whether or not a rising edge of the clock, for example, has been received. If it is determined in step S12 that the rising edge of the clock has not been received, the process returns to step S12.

If it is determined in step S12 that the rising edge of the clock has been received, the process proceeds to step S13, where the count value C is incremented by 1, and the process proceeds to step S14.

In step S14, it is determined whether or not the count value C has overflowed. Step S14
When it is determined that the count value C has not overflown, the process proceeds to step S15, and it is determined whether a reset signal has been transmitted from the edge detection circuit 31. If it is determined in step S15 that the reset signal has not been transmitted, step S12
Then, as described above, the count value C is incremented by one in synchronization with the rising edge of the clock.

If it is determined in step S15 that a reset signal has been received, the process returns to step S11, and the count value C is reset to zero. Then, the process proceeds to step S12, and thereafter, the count value C is incremented again from 0 in synchronization with the rising edge of the clock.

On the other hand, when it is determined in step S14 that the count value C has overflowed, that is, after the count value C has been reset in step S11, the edge detection circuit 31 does not output a reset signal and the predetermined time has elapsed. If the time has elapsed, the process proceeds to step S16, where the up counter 32 outputs the latch pulse to the data latch circuit 33.
Output to Then, the process returns to step S11, and thereafter, the above-described processing is repeated.

Next, the operation of the data latch circuit 33 will be described with reference to the flowchart of FIG.

In the data latch circuit 33, step S2
At 1, it is determined whether or not a latch pulse has been received from the up counter 32. If it is determined that no latch pulse has been received, the process returns to step S21. Step S2
If it is determined in step 1 that a latch pulse has been received, the process proceeds to step S22, where the data latch circuit 33
At the timing when the latch pulse is received, the composite sync signal is latched, and the latched value is output as a vertical synchronization signal. Then, the process returns to step S21, and thereafter, the same processing is repeated.

Next, with reference to the timing chart of FIG. 7, the operation of the vertical synchronizing signal separation circuit 13 of FIG.
Further explanation will be given.

Now, for example, a composite sync signal as shown in FIG. 7A similar to FIG.
Assuming that the reset signal is input to the vertical synchronizing signal separating circuit 13, the edge detecting circuit 31 outputs a reset signal which becomes H level at the rising edge and the falling edge of the composite sync signal as shown in FIG. Is output.

On the other hand, the up counter 32 repeats counting from 0 to MAX in synchronization with the clock, and the count value is reset to 0 at the timing of the reset signal output from the edge detection circuit 31. Therefore, the time change of the count value in the up counter 32 is as shown in FIG.

Further, the up counter 32 outputs a latch pulse only when an overflow occurs. Therefore, when the count value changes as shown in FIG. 7C, as shown in FIG. 7D. The latch pulse is output.

The data latch circuit 33 outputs the latch pulse at the timing when the up counter 32 outputs the latch pulse.
Since the composite sync signal shown in FIG. 7A is latched and the latched value is output as a vertical synchronization signal, the vertical synchronization signal output from the data latch circuit 33 is as shown in FIG.
As shown in FIG.

Now, when the up counter 32 changes from 0 to MA
Count up to X and determine until overflow
Time, that is, a predetermined time measured by the up counter 32
And W _max, The predetermined time W_maxIs a composite
Horizontal sync in the horizontal sync signal included in the sync signal
Pulse (part that is at H level as horizontal sync signal)
Min) pulse width W₁Longer and more horizontal sync pal
From the falling edge of the next horizontal sync pulse
Width to rising edge (hereinafter referred to as pulse interval as appropriate)
U) W_TwoIt is set to be shorter than

The pulse width of the vertical synchronizing pulse (the portion which is at the H level as the vertical synchronizing signal) is generally longer than both the pulse width W ₁ of the horizontal synchronizing pulse and the pulse interval W ₂ , so that the predetermined time W _max the longer than the pulse width W ₁ of the horizontal sync pulses, and by setting shorter than the pulse interval W _2, from the composite sync signal, it is possible to correct the vertical synchronizing signal separating (generation).

[0074] That is, the predetermined time W _{ma x} the up counter 32 is measured, since longer than the pulse width W ₁ of the horizontal sync pulses, up counter 32 which is reset by the horizontal sync pulse edges, a section of the horizontal synchronizing pulses There is no overflow and therefore no latch pulse is output.

[0075] The predetermined time W _{ma x} the up counter 32 is measured, since shorter than the pulse interval W ₂ of the horizontal sync pulse, the up-counter 32 is between from one horizontal sync pulse of the next horizontal sync pulse, always It overflows at least once, and therefore always outputs a latch pulse during that time.

[0076] Further, the predetermined time W _{ma x} the up counter 32 is measured, since shorter than the horizontal sync pulse pulse width W ₁ and the pulse interval W ₂ of one long vertical sync pulse interval than the up-counter 32 , The overflow always occurs once in the section of the vertical synchronizing pulse, and therefore, the latch pulse is always output once during that time.

As a result, the data latch circuit 33
In addition, the horizontal sync pulse in the composite sync signal is not latched. Further, the data latch circuit 33
Is a value (L) that is neither a horizontal sync pulse nor a vertical sync pulse in the composite sync signal.
Level) once or more. Third, the data latch circuit 33 outputs the composite sync signal
The value (H level) serving as the vertical synchronization pulse is latched at least once.

Therefore, the value output from the data latch circuit 33 after latching the composite sync signal is shown in FIG.
As shown in (1), the vertical synchronization pulse included in the composite sync signal is delayed by a predetermined time.

As described above, the edge of the horizontal synchronization pulse or the vertical synchronization pulse in the composite sync signal is detected, and the resetting is performed at the detection timing of the edge, and the measurement of the predetermined time is repeated. Each time the composite sync signal is latched and output as a vertical synchronization signal, an accurate vertical synchronization signal can be output.

That is, since the value output as the vertical synchronizing signal is determined when the composite sync signal is latched, the count value is changed to the vertical synchronizing pulse as described with reference to FIGS. By crossing the threshold value in the horizontal synchronization pulse immediately after, the output of the vertical synchronization signal including the horizontal synchronization pulse can be prevented. As a result, image distortion due to loss of synchronization,
Erroneous measurement of the vertical synchronization frequency can be prevented.

As described with reference to FIG. 3, when both increment and decrement of the count value are performed, errors in the count value are accumulated, but in the present embodiment, the count value is incremented. Therefore, even if an error occurs in the count value due to the jitter of the composite sync signal or the dullness of its rising edge and falling edge, the error is not accumulated.
Therefore, in the present embodiment, the jitter that can occur in the vertical synchronization signal is only one clock in principle, and the influence of the jitter of the composite sync signal on the vertical synchronization signal can be suppressed as much as possible. Further, according to the vertical synchronizing signal separation circuit 13 of FIG.
As it is clear from (C), in the data latch circuit 33, since the rising edge of the vertical synchronizing pulse in the composite sync signal, the value of the elapsed time after W _{ma x} is latched, for the vertical synchronizing pulse in the composite signal, a vertical Since the time delay of the vertical synchronizing pulse output from the synchronizing signal separation circuit 13 is always constant, it is possible to prevent a problem such as vertical image fluctuation of an image due to jitter or the like of the vertical synchronizing pulse.

In the present embodiment, the vertical synchronizing signal separating circuit 13 is provided with the up-counter 32 for incrementing the count value in synchronization with the clock. For example, instead of the up counter 32, a counter that decrements the count value in synchronization with a clock may be provided.

Also, in the present embodiment, the image is displayed on a CRT.
20, the present invention is applicable to a liquid crystal display, a projector, and the like.

Further, in the present embodiment, the up counter 32 outputs a latch pulse to the data latch circuit 33 when the count value overflows.
In 2, the count value may be compared with a predetermined threshold value, and a latch pulse may be output when the count value matches the predetermined threshold value.

In the present embodiment, the clock used in the vertical synchronizing signal separating circuit 13 is asynchronous with the composite sync signal.
The signal may be synchronized with the horizontal synchronization signal.

Further, in this embodiment, a case has been described in which the present invention is applied to a computer display. However, the present invention is also applicable to, for example, a television receiver and the like.

Next, the vertical synchronizing signal separating circuit 13 can be realized by dedicated hardware or software. Vertical synchronization signal separation circuit 13
Is realized by software, a program constituting the software is installed in a one-chip microcomputer, a general-purpose computer, or the like.

FIG. 8 shows a configuration example of an embodiment of a computer functioning as the synchronization signal separating circuit 13.

A program for causing a computer to function as the synchronization signal separating circuit 13 can be recorded in advance on a hard disk 105 or a ROM 103 as a recording medium built in the computer.

Alternatively, the program may be a floppy disk, CD-ROM (Compact Disc Read Only Memory), M
O (Magneto optical) disc, DVD (Digital Versatile)
Disc), a magnetic disk, a semiconductor memory, or another such removable storage medium 111, which can be temporarily or permanently stored (recorded). Such a removable recording medium 111 can be provided as so-called package software.

The program may be installed in the computer from the removable recording medium 111 as described above, or may be wirelessly transferred from a download site to the computer via an artificial satellite for digital satellite broadcasting, or transmitted from a LAN (Local Area). Network), the Internet, and the like, and can be transferred to a computer by wire. In the computer, the transferred program can be received by the communication unit 108 and installed on the built-in hard disk 105.

The computer has a CPU (Central Processing).
Unit) 102. The CPU 102 has a bus 1
01, an input / output interface 110 is connected. The CPU 102 receives a command via the input / output interface 110 by operating the input unit 107 including a keyboard, a mouse, and the like. Then, according to it, ROM (Read Only Memory)
The program stored in 103 is executed. Alternatively, the CPU 102 transmits the program stored in the hard disk 105, a satellite, or a network, receives the program by the communication unit 108, and
The program installed in the hard disk 105 is read from the removable recording medium 111 installed in the drive 109 and loaded into the RAM (Random Access Memory) 104 and executed. Thereby, the CPU 102 performs the processing according to the flowchart shown in FIG. 6 described above. Then, the CPU 102 transmits the processing result as necessary, for example, via the input / output interface 110.
An output is made from an output unit 106 including an LCD (Liquid CryStal Display), a speaker, or the like, or transmitted from a communication unit 108, and further recorded on the hard disk 105.

Here, in this specification, processing steps for writing a program for causing a computer to perform various processes do not necessarily have to be processed in chronological order in the order described in the flowchart, and may be performed in parallel. Alternatively, it also includes processing executed individually (for example, parallel processing or processing by an object).

The program may be processed by one computer, or may be processed in a distributed manner by a plurality of computers. Further, the program may be transferred to a remote computer and executed.

When the vertical synchronizing signal separation circuit 13 is realized by software, the up-down counter 3
The predetermined time _Wmax measured by 2 can be easily changed. Further, for example, as described above, when the up counter 32 compares the count value with a predetermined threshold value and outputs a latch pulse when the count value matches the predetermined threshold value, the value of the predetermined threshold value Changes are also easily possible.

[0096]

According to the synchronization signal output circuit, the synchronization signal output method, the recording medium, and the display device of the present invention, the edge of the pulse in the input signal is detected, and the pulse is reset at the detection timing of the edge for a predetermined time. Is repeated. Then, every time the predetermined time is measured, the input signal is latched and output as a synchronization signal. Therefore, an accurate synchronization signal can be obtained from the input signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an example of a conventional vertical synchronization signal separation circuit.

FIG. 2 is a timing chart for explaining the operation of the vertical synchronizing signal separation circuit of FIG. 1;

FIG. 3 is an enlarged timing chart of a part of FIG. 2;

FIG. 4 is a block diagram illustrating a configuration example of a computer display according to an embodiment of the present invention;

FIG. 5 is a block diagram showing a configuration example of a vertical synchronization signal separation circuit 13;

FIG. 6 is a flowchart for explaining the operation of the vertical synchronization signal separation circuit 13;

FIG. 7 is a timing chart for explaining the operation of the vertical synchronization signal separation circuit 13;

FIG. 8 is a block diagram illustrating a configuration example of a computer according to an embodiment of the present invention.

[Explanation of symbols]

11V, 11H terminals, 12 switches, 12a,
12b terminal, 13 vertical synchronization signal separation circuit, 14
Frequency measurement circuit, 15 peripheral devices, 15A synchronization circuit, 15B deflection correction waveform generation circuit, 15C video amplifier, 15D OSD circuit, 16 CPU, 1
7 EEPROM, 18 control input / output device, 18
A front panel control switch, 18B communication device for factory adjustment, 19 deflection circuit, 20 CRT, 20A
Deflection yoke coil, 31 edge detection circuit, 32
Up counter, 33 data latch circuit, 101
Bus, 102 CPU, 103 ROM, 104 RA
M, 105 hard disk, 106 output unit,
107 input unit, 108 communication unit, 109 drive, 110 input / output interface, 111 removable recording medium

Continued on the front page (72) Inventor Koji Murahashi 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo F-term (reference) in Sony Corporation 5C020 AA35 BA09 BB08 CA13

Claims (9)

[Claims] 1. A synchronization signal output circuit that processes an input signal and outputs a synchronization signal, wherein the edge detection unit detects an edge of a pulse in the input signal, and repeats measuring a predetermined time. Measuring means reset at an edge detection timing by an edge detecting means; and latch means for latching the input signal and outputting as the synchronization signal each time the predetermined time is measured by the measuring means. Characteristic synchronization signal output circuit. 2. The apparatus according to claim 1, wherein the measuring unit measures the predetermined time by repeating counting from a first value to a second value in synchronization with a predetermined clock. 2. The synchronization signal output circuit according to 1. 3. The synchronization signal output according to claim 2, wherein the measuring unit resets the count value of the clock to the first value at an edge detection timing by the edge detecting unit. circuit. 4. The synchronization signal output according to claim 1, wherein the input signal is a signal obtained by combining a horizontal synchronization signal and a vertical synchronization signal, and the synchronization signal is a vertical synchronization signal. circuit. 5. The apparatus according to claim 4, wherein the predetermined time is longer than a pulse width of the horizontal synchronization signal.
2. The synchronization signal output circuit according to 1. 6. The synchronization signal output circuit according to claim 4, wherein the predetermined time is shorter than an interval from one pulse of the horizontal synchronization signal to the next pulse. 7. A synchronization signal output method for processing an input signal and outputting a synchronization signal, the method comprising: repeating an edge detection step of detecting an edge of a pulse in the input signal; and measuring a predetermined time. A measurement step reset at an edge detection timing in the edge detection step; and a latch step of latching the input signal and outputting the input signal as the synchronization signal each time the predetermined time is measured in the measurement step. Characteristic synchronization signal output method. 8. A recording medium on which a program for causing a computer to process an input signal and output a synchronization signal is recorded, wherein an edge detecting step of detecting an edge of a pulse in the input signal. Repeating a measurement of a predetermined time, a measurement step reset at an edge detection timing in the edge detection step, and latching the input signal every time the predetermined time is measured in the measurement step; A recording medium on which a program including a latch step of outputting as a signal is recorded. 9. A display device for processing an input signal, obtaining a synchronization signal, and displaying an image in synchronization with the synchronization signal, comprising: edge detection means for detecting an edge of a pulse in the input signal; Measuring means resetting at the edge detection timing by the edge detecting means, repeating measuring a predetermined time; latching the input signal each time the predetermined time is measured by the measuring means; And a display unit for displaying the image in synchronization with the synchronization signal.