JP2001127778A - Bus analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a bus analyzer with high reliability that can prevent missing of captured data by detecting occurrence of a bus reset storm. SOLUTION: The bus analyzer that captures packet data communicated through a bus so as to measure and analyze a state of the bus, includes a counter that counts the number of bus reset signals communicated through the bus, a timer that controls a count time of this counter, and a discrimination section that discriminated the occurrence of the bus reset storm when the count of the counter reaches a prescribed value.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus analyzer, and more particularly, to a measure against a bus reset storm in a bus analyzer for IEEE 1394 or the like.

[0002]

2. Description of the Related Art IEEE 1394 is a serial communication interface standardized as an industry-wide bus standard. By using a dedicated connector, up to 63 types of personal computers, peripherals for personal computers, home appliances, musical instrument keyboards and the like can be used. Electrical devices can be connected at 33 to 400 Mbps per second (40 Mbps with on-board SCSI). It is suitable for transferring large amounts of data between a personal computer and digital video,
It has a hot swap function that can be connected / disconnected without turning the power on / off, so there is no need to set an ID for connection and no terminator is required.

[0003] In such an IEEE 1394 bus, a parent-child relationship called a 1394 tree must be established between the connected electrical devices. Therefore, each time an electrical device is connected to or removed from the bus, the parent-child relationship is re-established. A bus reset signal for construction is propagated.

Devices having a cycle master function, such as electric devices having an image transmission function, need to stand at the top of the tree, and therefore transmit a bus reset signal by software.

In addition, in the IEEE 1394 bus to which various multi-vendor electric devices are connected, for example, there is a problem of compatibility between IC chips controlling a physical layer, an IC chip receiving an invalid packet malfunctions, and A large number of bus reset signals may be transmitted due to the occurrence of a connection failure between the bus and the bus.

The bus analyzer uses the IEEE 139
It is used for analyzing the operation of individual electrical devices connected to the four buses or the IEEE 1394 bus to which a plurality of electrical devices are connected. That is, it is connected to the bus connection terminal of each electric device connected to the IEEE 1394 bus to determine whether the packet data output when a predetermined packet is received satisfies a predetermined standard in data length, timing, and the like. By confirming or connecting to an IEEE 1394 bus to which a plurality of electric devices are connected and capturing packets flowing on the bus, analysis of the fault contents of the devices and identification of connection faults are performed.

By the way, such a bus analyzer is
In the interrupt processing, in order to speed up the response to the interrupt request, as shown in the flowchart of FIG. 5, a plurality of interrupt factors are continuously processed at the start of one interrupt processing as much as possible. That is, even if all the processes of the interrupt factor at the time of reading in step STP1 are completed, the interrupt process is not terminated. Then, in step STP2, the interrupt factor is read out again. If there is no interrupt factor, the interrupt process is terminated in step STP4. , A loop is formed in which the interrupt processing of step STP3 is started again.

[0008]

In the state where the bus analyzer is connected in this way, if the above-mentioned bus reset signal is continuously generated at short intervals of, for example, several hundred μs, a bus reset storm state occurs. Is Step STP1 → Step STP2 → Step STP
3 → step STP1 →... Enters an infinite loop, so that it is impossible to escape from the interrupt processing, and at a glance, the system hangs.

When the data capture function of the bus analyzer is activated, the control is shifted from the interrupt processing having a higher execution priority to the application program even though the data capture is completed and an event is transmitted to the application program. Because of this, there is a problem that data processing cannot be started. As a result, in the worst case, the system may go down and the captured data may be lost.

The present invention focuses on such a problem, and an object of the present invention is to realize a highly reliable bus analyzer which can prevent the loss of captured data by detecting the occurrence of a bus reset storm. It is in.

[0011]

According to a first aspect of the present invention, there is provided a bus analyzer for receiving packet data flowing through a bus, measuring and analyzing the state of the bus, and determining the number of bus reset signals flowing through the bus. It is characterized by including a counter for counting, a timer for controlling the counting time of the counter, and a determining unit for determining that a bus reset storm has occurred when the count value of the counter reaches a predetermined value.

Thus, the state of the bus reset storm can be accurately detected.

According to a second aspect of the present invention, in the bus analyzer of the first aspect, the capturing of the packet data is stopped based on the bus reset storm detection signal, and the captured data is stored.

Thus, the cause of the occurrence of the bus reset storm can be efficiently analyzed based on the stored captured data.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a main part of an example of an embodiment of the present invention. In the figure, a bus reset storm detection function switch 1 turns on and off a detection function of a bus reset signal BR propagated to a IEEE 1394 bus 2 via a bus chip (not shown). Sends, but does not send when off.

The bus reset storm detection timer 3 is started in the initial state when one bus reset signal BR is input, and the bus input within a predetermined time set by the bus reset storm detection timer setting unit 4. The reset signal BR is sent to the bus reset signal counter 5.

The bus reset signal counter 5 counts the number of bus reset signals BR input via the bus reset storm detection timer setting unit 4 and outputs the count value to the bus reset storm occurrence determination unit 6. The bus reset storm occurrence judging section 6 receives a setting value from the bus reset storm occurrence judgment value register 7 for judging that a bus reset storm has occurred.

On the other hand, these bus reset signal counters 5
The bus reset storm occurrence determination unit 6 receives a time-up signal TU from the bus reset storm detection timer 3. The time-up signal TU indicates that a predetermined time set by the bus reset storm detection timer setting unit 4 has elapsed since the input of one bus reset signal BR, the bus reset signal counter 5 and the bus reset storm generation. The information is transmitted to the determination unit 6.

The bus reset storm occurrence judging section 6 judges whether or not a bus reset storm has occurred when it is recognized that a predetermined set time has elapsed based on the time-up signal TU. It outputs to the reset storm occurrence detection register 8.

The bus reset storm occurrence notifying unit 9 notifies the judgment result written in the bus reset storm occurrence detection register 8 to each unit of the bus analyzer such as a packet data capturing unit (not shown). Each unit performs a predetermined process, such as stopping capture of packet data, based on the notification of the determination result.

When a series of the bus reset storm detection process is completed, an initialization signal is output from the initialization circuit 10 to each unit, and each unit is initialized to be in a standby state for the next bus reset storm detection process.

FIG. 2 shows a bus reset storm detection timer 3
3 is a flowchart showing the flow of the processing of FIG. Step S
At TP1, based on ON / OFF of the bus reset storm detection function switch 1 of FIG. 1, the status and variables of each unit such as the bus reset storm detection timer 3, the bus reset storm detection timer setting unit 4, and the bus reset storm occurrence determination unit 6, etc. Then, it is determined whether or not the bus reset storm detection operation is enabled.

If the bus reset storm detection operation is not enabled, the processing of the bus reset storm detection timer 3 is not performed, and another normal processing shown in step STP5 is executed. When enabled, the bus reset storm detection timer 3 starts counting a clock (not shown) having a predetermined cycle (for example, 10 ms) until a predetermined time (for example, 100 ms) set by the bus reset storm detection timer setting unit 4 is reached. When the predetermined time has been reached, a time-up signal TU is output to the bus reset signal counter 5 and the bus reset storm occurrence determination section 6, and the counter of the bus reset storm detection timer 3 is reset to 0 as shown in step STP4. The other normal processing shown in step STP5 is executed.

The flow of the bus reset interrupt process will be described with reference to the flowcharts of FIGS. Step S
At TP1, it is determined whether or not the bus reset storm detection operation is enabled based on the on / off state of the bus reset storm detection function switch 1 of FIG. 1 and the variables of the bus reset storm detection timer setting unit 4.

If not, step STP1 for determining whether or not a bus reset storm has been detected
Jump to zero.

When the bus reset signal is enabled, the bus reset signal counter 5 updates the count value each time a bus reset signal is input in step STP2. Subsequently, at step STP3, the bus reset storm detection timer 3
Is stopped or not.

If not stopped, the process jumps to step STP5 where it is determined whether or not a bus reset storm has been detected. If it has stopped, the bus reset storm detection function switch 1 is turned on to initialize the bus reset storm detection timer 3 in step STP4.

In step STP5, if a bus reset storm has not been detected, the process jumps to step STP10 in which it is determined whether a bus reset storm has been detected.

If a bus reset storm has been detected,
In step STP6, the interrupt of the bus chip is prohibited, and the bus reset storm detection timer 3 is stopped.
Then, in step STP7, it is determined whether or not packet data is being captured.

If packet data is not being fetched, the process jumps to step STP9 to transmit a bus reset storm detection event. If the packet data is being captured, the capturing of the packet data is stopped in step STP8.

In step STP10, if a bus reset storm has not been detected, the bus reset process in step STP11 is executed.

If a bus reset storm has been detected,
The process jumps to step STP12 and proceeds to the next interrupt factor process.

FIG. 5 is a flowchart showing the flow of the process of the bus reset initialization by the initialization circuit 10. In step STP1, it is determined whether or not a bus reset storm has been detected.

If the bus reset storm has not been detected, the initialization processing is completed as it is.

If a bus reset storm has been detected,
As shown in step STP2, the bus reset signal counter 5 is initialized, the bus reset storm detection timer 3 is initialized, the bus reset storm detection function switch 1 is turned off, the bus reset storm output from the bus reset storm occurrence detection register 8 is output. It performs initialization processing such as clearing of a detection event, clearing of a bus reset storm detection determination result in the bus reset storm occurrence determination section 6, clearing of a transmission / reception buffer inside a bus chip (not shown), and enable of a bus chip interrupt.

By configuring the bus analyzer to execute these processes, it is possible to avoid a system down due to a bus reset storm and a temporary system hang-up state as in the prior art. Further, as a result, the captured packet data can be retained even when a bus reset storm occurs, so that accurate cause analysis can be performed. Further, it is possible to notify the user of the occurrence of the bus reset storm and to prompt the user to perform appropriate countermeasures.

The functions of the above-described units can be realized by appropriately combining hardware circuits and software.

Although the example of the IEEE1394 bus has been described, the present invention can also be applied to various network bus analyzers.

[0039]

As described above, according to the present invention,
A highly reliable bus analyzer can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an example of an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing flow of a bus reset storm detection timer 3;

FIG. 3 is a flowchart illustrating a flow of a bus reset interrupt process.

FIG. 4 is a flowchart showing a flow of a bus reset interrupt process.

FIG. 5 is a flowchart illustrating a flow of a bus reset initialization process.

FIG. 6 is a flowchart showing the flow of a conventional interrupt process.

[Explanation of symbols]

 1 Bus reset storm detection function switch 2 IEEE 1394 bus 3 Bus reset storm detection timer 4 Bus reset storm detection timer setting unit 5 Bus reset signal counter 6 Bus reset storm occurrence determination unit 7 Bus reset storm occurrence determination value register 8 Bus reset storm occurrence detection Register 9 Bus reset storm occurrence notification unit 10 Initialization circuit

Claims (4)

[Claims] A bus analyzer for taking in packet data flowing on a bus and measuring and analyzing the state of the bus, a counter for counting the number of bus reset signals flowing on the bus, a timer for controlling the counting time of the counter, A bus reset storm when the count value reaches a predetermined value. 2. The bus analyzer according to claim 1, wherein the capturing of the packet data is stopped based on the bus reset storm detection signal, and the captured data is stored. 3. The bus analyzer according to claim 1, wherein the bus is an IEEE 1394 bus. 4. The bus analyzer according to claim 1, wherein the function of each section is realized by combining a hardware circuit and software.