JP2009271569A - Semiconductor integrated circuit and electronic apparatus equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable one input terminal in a semiconductor integrated circuit to be used for a serial reception and also an external interruption. <P>SOLUTION: This semiconductor integrated circuit (10) includes: a CPU (12); an input terminal (11) which is common to a serial communication data signal and an external interruption signal; and an interruption notification part (15) for notifying the CPU (12) of serial reception interruption or external interruption. The interruption notification part (15) notifies the CPU (12) of interruption notification based on whether or not it is possible to detect a data frame from an external signal input through the input terminal (11). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit having a serial communication function and an electronic apparatus including the same.

  In recent years, semiconductor devices have been miniaturized due to improvements in semiconductor technology, leading to miniaturization of semiconductor integrated circuits and reduction of material costs. However, the shape of the external terminal cannot keep up with the miniaturization technology of the semiconductor element for the convenience of wiring processing to the package or the substrate, and the terminal interval cannot be compressed. For this reason, the terminal interval that affects the area of the element is not reduced, which is a barrier to further miniaturization and cost reduction of the semiconductor integrated circuit.

  Reducing the terminals themselves is an effective means for solving the above problems. However, if the required functions are lost due to the reduction of terminals, there is a disadvantage to the semiconductor integrated circuit and the electric equipment having the same. appear. Therefore, when reducing the number of terminals, it is necessary to consolidate them into one terminal in a state where a plurality of functions can be used together. When a plurality of functions are aggregated in a state where they can be used together, it is a problem how to identify the function as a signal to the semiconductor integrated circuit.

For example, a microcomputer often has a function for communicating with an external device such as a serial interface function or an external interrupt. Depending on the purpose of the microcomputer, there may be a shortage of hardware resources equipped with an external interrupt function. In order to compensate for the lack of such an external interrupt function, a technique for extending a serial reception terminal for external interrupt is known (for example, Patent Document 1).
JP 63-10240 A

  However, if the serial reception terminal is expanded for external interrupts, the data input / held from the serial reception terminal to the reception buffer is given meaning as an external interrupt. As a result, the serial reception terminal cannot be used as a serial reception function for receiving general-purpose data, and becomes a dedicated terminal for external interrupts.

  In view of the above problems, an object of the present invention is to make it possible to use one input terminal in a semiconductor integrated circuit for both serial reception and external interrupt. Another object is to provide an electronic device including such a semiconductor integrated circuit.

  In order to solve the above problems, the present invention has taken the following measures. That is, as a semiconductor integrated circuit, based on whether the CPU, the input terminal common to the serial communication data signal and the external interrupt signal, and the data frame can be detected from the external signal input through the input terminal, It is assumed that an interrupt notification unit that notifies a serial reception interrupt or an external interrupt is provided.

  In addition, as a semiconductor integrated circuit, a CPU, an input terminal common to serial communication data signals and external interrupt signals, a buffer for temporarily storing a data frame input via the input terminal, and data stored in the buffer A comparator that compares a frame with a predetermined bit pattern, and if both match, notifies the CPU of a serial reception interrupt when detecting the next data frame of the data frame, while if both do not match, It is assumed that an interrupt notification unit that notifies the CPU of an external interrupt is provided.

  In addition, as a semiconductor integrated circuit, a CPU, an input terminal common to serial communication data signals and external interrupt signals, a buffer for temporarily storing a data frame input via the input terminal, and data stored in the buffer It has a comparator that compares the bit pattern at a predetermined position of the frame with a predetermined bit pattern. When they match, it notifies the CPU of a serial reception interrupt, while when they do not match, it notifies the CPU of an external interrupt. It is assumed that an interrupt notification unit is provided.

  It is assumed that the above-described semiconductor integrated circuit is provided as an electronic device.

  According to the present invention, it is identified whether the external signal input to the input terminal is a serial communication data signal or an external interrupt signal, and an interrupt is notified to the CPU according to the identification result. Therefore, serial reception and external interrupt can be shared by one input terminal, and the terminals of the semiconductor integrated circuit can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 shows a configuration of a semiconductor integrated circuit according to the first embodiment. The input terminal 11 of the semiconductor integrated circuit 10 is connected to a serial communication data transmission source and an external interrupt signal transmission source (not shown), and accepts both the serial communication data signal and the external interrupt signal. The semiconductor integrated circuit 10 includes a central processing unit (CPU) 12 and an interrupt notification unit 15 that notifies the CPU 12 of a serial reception interrupt 13 or an external interrupt 14 based on an external signal input via the input terminal 11. Yes. The interrupt notification unit 15 sends a serial reception interrupt to the CPU 12 based on the detection results of the start bit detector 151 and the end bit detector 152 that can be a comparator between the input external signal and the serial reception data 1 unit length (data frame). 13 or external interrupt 14 is determined.

  In general, asynchronous serial communication data includes a data group to which a Start bit, Data bit, End bit, and possibly a Parity bit are added as one transfer data (one frame) as shown in FIG. The semiconductor integrated circuit 10 having a serial reception function has a sampling clock therein, and periodically monitors the state of an external signal input to the input terminal 11. When the Start bit is detected, the presence or absence of the End bit is monitored as an identification of whether or not the received data length is normal after a specific period. When the End bit is detected, the CPU 12 is notified of the End bit information together with the serial reception interrupt. The CPU 12 performs an interrupt process in accordance with the notified information.

  If an error occurs in the end bit detection, there is a mismatch in the communication speed with the serial data transfer source (i.e., when no step is taken), and a signal that is not serial communication data is input to the semiconductor integrated circuit. It is divided roughly when it is done. Data whose end bit cannot be detected is basically not reliable information as serial reception data. Therefore, when the End bit is not detected, as shown in FIG. 3, even if notified as a serial reception interrupt, the CPU can discard the received data obtained by the semiconductor integrated circuit and return the system to the state before the start of reception. It is common. However, in a state where the connection status and communication target are determined, that is, a system in which the signal input to the serial reception terminal of the semiconductor integrated circuit can only be serial reception data, the situation that the End bit is not detected does not occur, The processing sequence does not play an important role. That is, when the End bit is not detected, it is not necessary to notify the CPU of a serial communication interrupt.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 4, the CPU 12 is notified as a serial reception interrupt based on whether or not the end bit of serial communication is detected from an external signal input to the input terminal 11 or externally. Switching whether to notify as an interrupt. As a result, the number of terminals can be reduced by using serial reception and external interrupt as one terminal.

(Second Embodiment)
In the semiconductor integrated circuit 10 according to the first embodiment, when one frame length of serial communication is exceeded, switching is performed as an external interrupt. However, for example, a system that does not want a response to a short-time signal input, such as a power switch of a mobile phone, and that wants to react as an interrupt only when input for a long time, that is, Input (B) in FIG. A signal that exceeds the frame length of one frame of serial communication but does not satisfy the standard to handle as an external interrupt (signal input period) is excluded from the interrupts notified to the CPU, and satisfies the standard to treat as an external interrupt, such as Input (C) There may be systems that want to be notified as external interrupts only when Further, a signal to be handled as an external interrupt signal such as Input (D) is not always a constant potential, and a system that wishes to notify the CPU as an external interrupt with a plurality of Low / High level amplitudes is conceivable.

  FIG. 5 shows a configuration of a semiconductor integrated circuit according to the second embodiment. When the interrupt notification unit 15 in the semiconductor integrated circuit 10 according to the present embodiment determines that the end bit cannot be detected and the serial reception is not performed, the interrupt notification unit 15 further monitors whether or not the input external signal is really an external interrupt signal. To do. Specifically, the interrupt notification unit 15 has a configuration in which a timer 153 and a signal state monitor 154 are added to the interrupt notification unit 15 shown in FIG. The timer 153 measures a predetermined time after receiving a notification from the end bit detector 152 that the end bit cannot be detected. This time can be changed by the CPU 12. The signal state monitor 154 receives the notification that the end bit cannot be detected from the end bit detector 152 until the timer 153 finishes measuring a predetermined time, and then the external signal input to the input terminal 11 Monitor the status of The interrupt notification unit 15 notifies the CPU 12 of the external interrupt 14 when the state change of the external signal during the monitoring period satisfies a predetermined condition.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 7, if the input external signal is a signal that does not need to be processed by the CPU 12, it is excluded from the interrupt, and the monitored external signal is a condition as an external interrupt. If the signal satisfies the condition, the CPU 12 is notified. As a result, for example, when the external interrupt signal transmission source generates a waveform such as a specific serial command, or generates chattering noise that you do not want to handle as an external interrupt, such as a mechanical switch. Suitable for

(Third embodiment)
In the semiconductor integrated circuit 10 according to the second embodiment, only when data to be handled as serial communication or external interrupt is input, that is, like Input (A), Input (C), and Input (D) in FIG. It corresponds only when a signal is input, and cannot respond to a case where a signal such as Input (B) that cannot be distinguished from serial communication or external interrupt is input. At the initial stage of system construction, for example, it is conceivable that a failure may occur, for example, the control of asynchronous communication speed adjustment is mistaken. Therefore, by making it possible to detect a signal such as Input (B), it is possible to easily detect a communication abnormality and to debug.

  FIG. 8 shows a configuration of a semiconductor integrated circuit according to the third embodiment. The semiconductor integrated circuit 10 according to this embodiment is obtained by improving the semiconductor integrated circuit 10 according to the second embodiment so that a signal such as Input (B) in FIG. 6 can be detected. Specifically, the interrupt notification unit 15 notifies the CPU 12 of a communication error 155 when the state of the external signal changes during the external signal state monitoring by the signal state monitor 154.

  In the semiconductor integrated circuit 10 according to the present embodiment, as shown in FIG. 9, even when the input external signal is identified as neither a serial communication data signal nor an external interrupt signal, an abnormal signal is first detected by the CPU 12. Notify that. Thereby, it becomes possible to debug by detecting a communication abnormality.

(Fourth embodiment)
FIG. 10 shows a configuration of a semiconductor integrated circuit according to the fourth embodiment. The input terminal 11 of the semiconductor integrated circuit 10 is connected to a serial communication data transmission source and an external interrupt signal transmission source (not shown), and accepts both the serial communication data signal and the external interrupt signal. The semiconductor integrated circuit 10 includes a CPU 12 and an interrupt notification unit 15 that notifies the CPU 12 of a serial reception interrupt 13 or an external interrupt 14 based on an external signal input via the input terminal 11. The interrupt notification unit 15 should notify the CPU 12 of either the serial reception interrupt 13 or the external interrupt 14 based on the coincidence / non-coincidence of the input data frame and the drive-key which is a key for enabling the serial reception interrupt. Decide what to do.

  Specifically, the interrupt notification unit 15 temporarily stores a data frame input via the input terminal 11, the data frame stored in the buffer 156, and a predetermined bit pattern (Drive-Key). A comparator 158 for comparing with 157 is provided. As shown in FIG. 11, when the data frame stored in the buffer 156 matches the Drive-Key 157, the interrupt notification unit 15 notifies the CPU 12 of a serial reception interrupt upon detection of the next data frame, and does not match. In this case, an external interrupt is notified. As shown in FIG. 12, a serial reception sequencer originally provided in the semiconductor integrated circuit 10 can be used as the interrupt notification unit 15.

  According to the present embodiment, the semiconductor integrated circuit 10 transmits the drive-key for driving the serial interrupt circuit and the original serial data required by the CPU 12 from the serial data transmission source (not shown) to the CPU 12 in a serial manner. An interrupt request for reception is notified. On the other hand, when a signal other than Drive-Key is input to the semiconductor integrated circuit 10, an external interrupt is notified to the CPU 12.

  In the semiconductor integrated circuit 10 according to the present embodiment, a time loss corresponding to the reception of Drive-Key occurs. However, it is only necessary to notify the CPU 12 of the serial reception interrupt only when necessary data is transmitted from a serial transmission source (not shown), and in the communication between the serial transmission source and the semiconductor integrated circuit 10, the semiconductor integrated circuit is not provided. Serial data is not transmitted in succession beyond the processing of the circuit 10, and communication is performed with an appropriate waiting time. Therefore, the time loss for receiving the Drive-Key is not a problem.

(Fifth embodiment)
FIG. 13 shows a configuration of a semiconductor integrated circuit according to the fifth embodiment. The semiconductor integrated circuit 10 according to this embodiment has substantially the same configuration as the semiconductor integrated circuit 10 according to the fourth embodiment. The semiconductor integrated circuit 10 according to the present embodiment receives a data frame in which Drive-Key (Key bits) as shown in FIG. 14 is embedded, and the comparator 158 is at a predetermined position of the data frame stored in the buffer 156. By comparing the bit pattern with the Drive-Key 157, the interrupt notification unit 15 determines which of the serial reception interrupt 13 and the external interrupt 14 should be notified to the CPU 12 based on the match / mismatch.

  FIG. 15 shows a flow of a serial reception processing sequence of the semiconductor integrated circuit 10 according to the present embodiment. Basically, in serial communication, the bit length and data content of transfer data can be arbitrarily adjusted by application software. Therefore, a drive key for driving a serial reception interrupt is embedded in the contents of normal one frame of communication data, and the semiconductor integrated circuit 10 recognizes the key so that the serial reception interrupt and the external interrupt are identified and appropriate for the CPU 12. Can be interrupted. Thereby, the data buffer to the CPU 12 is not crushed.

  Note that the embedded position of the Drive-Key for driving the serial reception interrupt and its data length are arbitrary. Further, a mechanism that can be changed in consideration of the signal characteristics of an external interrupt that is desired to be shared may be provided.

(Embodiment of electronic device)
FIG. 16 shows an overview of an optical disc apparatus as an embodiment of an electronic apparatus. In general, the optical disc apparatus 100 includes a switch 101 using an external interrupt for inserting and removing the optical disc. The optical disc apparatus 100 may be serially connected to the host PC 200 via the serial terminal 102 for the purpose of application development or debugging.

  FIG. 17 is a schematic diagram of a substrate in the optical disc apparatus 100. The semiconductor integrated circuit 10 according to any one of the above embodiments is mounted on the substrate 103 in the optical disc apparatus 100. Therefore, the external interrupt signal from the switch 101 and the serial communication data signal from the serial terminal 102 can be received by the common input terminal 11.

  In addition to the optical disc device 100, the semiconductor integrated circuit 10 can be mounted on any home appliances and information devices such as a television receiver and a mobile phone.

  The semiconductor integrated circuit according to the present invention can be used for both serial reception and external interrupt with a single input terminal, and thus is useful for a semiconductor integrated circuit that requires downsizing and a system including the same.

1 is a configuration diagram of a semiconductor integrated circuit according to a first embodiment. It is a figure which shows the data structure transmitted by general serial communication. It is a flowchart of a general serial reception processing sequence. 4 is a flowchart according to a serial reception processing sequence of the semiconductor integrated circuit according to the first embodiment. It is a block diagram of the semiconductor integrated circuit which concerns on 2nd Embodiment. It is a figure which shows some signal patterns input into a semiconductor integrated circuit. 10 is a flowchart according to a serial reception processing sequence of the semiconductor integrated circuit according to the second embodiment. It is a block diagram of the semiconductor integrated circuit which concerns on 3rd Embodiment. 10 is a flowchart according to a serial reception processing sequence of the semiconductor integrated circuit according to the third embodiment. It is a block diagram of the semiconductor integrated circuit which concerns on 4th Embodiment. It is a figure which shows some signal patterns input into a semiconductor integrated circuit. 14 is a flowchart according to a serial reception processing sequence of the semiconductor integrated circuit according to the fourth embodiment. It is a block diagram of the semiconductor integrated circuit which concerns on 5th Embodiment. It is a figure which shows the data structure of the data frame with which Drive-Key was embedded. 10 is a flowchart according to a serial reception processing sequence of a semiconductor integrated circuit according to a fifth embodiment. It is a general-view figure of the optical disk device as one embodiment of electronic equipment. FIG. 17 is a schematic diagram of a substrate in the optical disc apparatus of FIG. 16.

Explanation of symbols

10 Semiconductor Integrated Circuit 11 Input Terminal 12 CPU
15 Interrupt Notification Unit 153 Timer 154 Signal State Monitor 156 Buffer 158 Comparator

Claims (7)

CPU,
Input terminal common to serial communication data signal and external interrupt signal,
A semiconductor comprising: an interrupt notification unit that notifies the CPU of a serial reception interrupt or an external interrupt based on whether or not a data frame has been detected from an external signal input via the input terminal Integrated circuit. The semiconductor integrated circuit according to claim 1,
The interrupt notification unit includes an end bit detector that detects an end bit of the data frame from the external signal, and notifies the CPU of a serial reception interrupt when the end bit is detected, while the end bit A semiconductor integrated circuit characterized in that an external interrupt is notified to the CPU when it cannot be detected. The semiconductor integrated circuit according to claim 2,
The interrupt notification unit includes a timer for measuring a predetermined time after receiving a notification that the end bit cannot be detected from the end bit detector, and the timer after receiving the notification from the end bit detector. A signal state monitor that monitors the state of the external signal until the predetermined time is counted, and when the state change of the external signal during the monitoring period satisfies a predetermined condition, A semiconductor integrated circuit that notifies an external interrupt to a CPU. The semiconductor integrated circuit according to claim 3,
The interrupt notification unit notifies the CPU of a communication error when the state of the external signal changes during the monitoring of the state of the external signal by the signal state monitor. CPU,
Input terminal common to serial communication data signal and external interrupt signal,
A buffer for temporarily storing a data frame input via the input terminal;
A comparator that compares the data frame stored in the buffer with a predetermined bit pattern, and if they match, notifies the CPU of a serial reception interrupt when the next data frame of the data frame is detected. On the other hand, a semiconductor integrated circuit comprising: an interrupt notification unit for notifying the CPU of an external interrupt when they do not match. CPU,
Input terminal common to serial communication data signal and external interrupt signal,
A buffer for temporarily storing a data frame input via the input terminal;
A comparator for comparing a bit pattern at a predetermined position of the data frame stored in the buffer with a predetermined bit pattern, and when the two match, the CPU is notified of a serial reception interrupt, while the two do not match And an interrupt notification section for notifying the CPU of an external interrupt. An electronic apparatus comprising the semiconductor integrated circuit according to claim 1.

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