JP2001127286A - Insulating gate-type semiconductor device, its manufacture method and inverter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide IGBT where latch-up can be prevented and ON voltage can be reduced. SOLUTION: An n+-type silicon single crystal area 28 is formed in the area 26a of an IGBT1. A barrier formed of the n+-type silicon single crystal area 28 and a p-type base area 14a has a value by which a hole cannot be diffused from the n+-type silicon single crystal area 28 to the p-type base area 14a. N+-type emitter areas 16a and 16b are not formed in the area 26b of the IGBT1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulated gate semiconductor device, a method of manufacturing the same, and an inverter circuit.

[0002]

BACKGROUND OF THE INVENTION As an insulated gate semiconductor device, for example, a power MOS (M
etal Oxide Semiconductor)
Field effect transistors and IGBTs (Insulated
Gate Bicolor Transistor)
There is. These semiconductor elements are used, for example, for power conversion and control.

Incidentally, these semiconductor elements have a parasitic bipolar transistor and a parasitic thyristor due to their structure. When a parasitic bipolar transistor or a parasitic thyristor operates, an overcurrent continues to flow through these semiconductor elements, which may lead to destruction of the semiconductor elements. This phenomenon is called latch-up.

An object of the present invention is to provide an insulated gate semiconductor device, IGB, which can reduce the possibility of latch-up.
It is to provide T and MIS field effect transistors.

Another object of the present invention is to provide an inverter circuit including at least one of these elements.

It is still another object of the present invention to provide a method of manufacturing an insulated gate semiconductor device which can reduce the possibility of latch-up.

It is still another object of the present invention to provide an insulated gate semiconductor device capable of reducing an ON voltage.

[0008]

According to the present invention, there is provided an insulated gate semiconductor device having a plurality of isolation regions separated from each other, wherein a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type are provided. And a third semiconductor region of the second conductivity type, wherein at least one of the isolation regions includes the first semiconductor region and the second semiconductor region, and a carrier of the first conductivity type is formed from the first semiconductor region. The supplied at least one isolation region includes the third semiconductor region, and the isolation region including the third semiconductor region has a first region.
There is no region for supplying a conductive type carrier,
This is an insulated gate semiconductor device.

According to the present invention having the above structure, the possibility of latch-up can be reduced. That is, according to the present invention, some of the isolation regions include the first semiconductor region (for example, an n-type emitter region), and others do not. Carriers of the second conductivity type (for example, holes) flow into both separation regions. If holes flow into the isolation region not including the first semiconductor region, latch-up is unlikely to occur.
The present invention reduces the possibility of latch-up by providing an isolation region that does not include the first semiconductor region.

The insulated gate semiconductor device according to the present invention having the above structure can be manufactured by, for example, the following steps (a) to (d). (A) forming a first semiconductor layer of the first conductivity type; (B) forming a second semiconductor layer of the second conductivity type on the first semiconductor layer; (C) a step of separating the second semiconductor layer into a plurality. (D) at least one of the plurality of second semiconductor layers includes:
Forming a first conductivity type semiconductor region for supplying a first conductivity type carrier, and not forming the semiconductor region on at least one of the plurality of second semiconductor layers;

The present invention can have the following configuration. That is, the present invention further includes a fourth semiconductor region of the first conductivity type and a fifth semiconductor region of the first conductivity type, wherein the fourth semiconductor region has a depletion layer in the isolation region including the third semiconductor region. And the fifth semiconductor region is formed between the second semiconductor region and the fourth semiconductor region so that a first conductive region in the fifth semiconductor region can be formed. The impurity concentration of the mold is
An insulated gate semiconductor device having a higher impurity concentration than the first conductivity type in the semiconductor region.

According to the present invention having the above structure, the breakdown voltage of the insulated gate semiconductor device is maintained by the depletion layer formed by the junction between the fourth semiconductor region and the third semiconductor region.

According to the present invention having the above configuration,
ON of the insulated gate semiconductor device is enabled by the fifth semiconductor region.
Voltage can be reduced. That is, in the isolation region including the second semiconductor region, carriers of the second conductivity type
By decreasing the rate of diffusion from the semiconductor region to the second semiconductor region, the carrier accumulation in the fourth semiconductor region can be increased, so that an increase in the resistance of the fourth semiconductor region can be suppressed. Therefore, the present invention, which can reduce the ON voltage of the insulated gate semiconductor device, can have the following structure. That is,
According to the present invention, the barrier formed by the fifth semiconductor region and the fourth semiconductor region has a value such that carriers of the second conductivity type cannot diffuse from the fourth semiconductor region to the second semiconductor region. This is an insulated gate semiconductor device.

According to the present invention having the above structure, the carriers of the second conductivity type flowing from the fourth semiconductor region are blocked by the barrier and do not diffuse into the second semiconductor region. As a result, carriers of the second conductivity type are accumulated in the fourth semiconductor region. Note that some of the second conductivity type carriers recombine with the first conductivity type carriers in the fifth semiconductor region and disappear. By blocking by the barrier, carriers of the second conductivity type flowing from the fourth semiconductor region can be prevented from flowing into the second semiconductor region, so that the effect of preventing latch-up can be further enhanced. Since the fifth semiconductor region is not formed in the isolation region including the third semiconductor region, a path through which the carrier of the second conductivity type flows is secured by the isolation region.

The present invention can have the following configuration. That is, the present invention further includes a sixth semiconductor region of a first conductivity type, wherein the sixth semiconductor region is formed between the second semiconductor region and the fifth semiconductor region, Is an insulated gate semiconductor device joined to the second semiconductor region so that a depletion layer can be formed in the isolation region including the first semiconductor region and the second semiconductor region.

According to the present invention having the above configuration, the following operation and effect can be obtained. When the barrier is formed, no depletion layer is formed in the isolation region including the first semiconductor region and the second semiconductor region. Therefore, for example, when the width of the isolation region is widened, the breakdown voltage of the insulated gate semiconductor device may be reduced only by the depletion layer formed in the isolation region including the third semiconductor region. Therefore, by adding the sixth semiconductor region, a depletion layer can be formed also in the isolation region including the first semiconductor region and the second semiconductor region, and a decrease in withstand voltage of the insulated gate semiconductor device can be prevented.

According to the present invention, there is provided an insulated gate semiconductor device having a plurality of isolation regions separated from each other, wherein the first conductivity type first semiconductor region, the second conductivity type second semiconductor region, and the first conductivity type are provided. A third semiconductor region and a fourth semiconductor region of a first conductivity type, wherein the isolation region includes the first semiconductor region;
Including the second semiconductor region and the fourth semiconductor region,
A carrier of a first conductivity type is supplied from the first semiconductor region, and at least one isolation region includes the third semiconductor region and is formed by the third semiconductor region and the fourth semiconductor region. The barrier has a value such that carriers of the second conductivity type cannot diffuse from the fourth semiconductor region to the second semiconductor region, and at least one of the isolation regions does not include the third semiconductor region. The fourth semiconductor region is an insulated gate semiconductor device that is joined to the second semiconductor region so that a depletion layer can be formed in the isolation region.

According to the present invention, the ON voltage of the insulated gate semiconductor device can be reduced. That is, the barrier formed by the third semiconductor region and the fourth semiconductor region has such a value that carriers of the second conductivity type cannot diffuse from the fourth semiconductor region to the second semiconductor region. For this reason, in the isolation region including the third semiconductor region, carriers of the second conductivity type become the third region.
Since diffusion from the semiconductor region to the second semiconductor region can be prevented, the resistance at this portion does not increase. Therefore, the ON voltage of the insulated gate semiconductor device can be reduced.

By not forming the third semiconductor region in at least one isolation region, a path through which carriers of the second conductivity type flow is secured.

The present invention relates to an inverter circuit for converting DC power to AC power, which includes any one of the insulated gate semiconductor devices.

As described above, according to the insulated gate semiconductor device, the possibility of latch-up can be reduced. Since the inverter circuit according to the present invention includes these semiconductor devices, the reliability of the inverter circuit can be improved.

[0022]

[First Embodiment] {Description of Structure} FIG. 1 is a cross-sectional view of an IGBT 1 according to a first embodiment of the present invention. First, the cross-sectional structure of the IGBT 1 will be described.

The IGBT 1 has a p ⁺ -type collector region 10,
n-type base region 12, p-type base regions 14a, 14b,
It has n ⁺ -type emitter regions 16a, 16b and trench gate electrodes 18a, 18b, 18c. The n ⁺ -type emitter regions 16a and 16b are examples of a first semiconductor region. The p-type base region 14a is an example of a second semiconductor region. The p-type base region 14b is an example of a third semiconductor region. The n-type base region 12 is an example of a fourth semiconductor region.

The p ⁺ type collector region 10 is formed on a silicon substrate. On the p ⁺ type collector region 10, n ⁺
A mold buffer region 20 is formed. An electrode 34 is formed below the p ⁺ type collector region 10. An n-type base region 12 is formed on n ⁺ -type buffer region 20. On the n-type base region 12, the p-type base region 1
4 are formed.

The trench gate electrodes 18a, 18b, 18
c is buried in the trenches 22a, 22b, 22c, respectively. The trenches 22a, 22b, 22c are
It penetrates the p-type base region 14 and reaches the n-type base region 12. Here, the trench 22a and the trench 22b
The p-type base region 14 sandwiched between
4a. Further, the p-type base region 14 sandwiched between the trenches 22b and 22c is
b.

The trench 22a and the trench gate electrode 18
a, the trench 22b and the trench gate electrode 18b
A silicon oxide layer 24 is formed between the trench 22c and the trench gate electrode 18c. Of the silicon oxide layer 24, the p-type base region 14
The portions facing a and 14b are the gate insulating layers.
Note that another insulating layer can be used instead of the silicon oxide layer 24.

The region 26a is a region defined by the trench 22a and the trench 22b. The region 26b is a region defined by the trench 22b and the trench 22c. The region 26a and the region 26b are separated by the trench 22b. The regions 26a and 26b are examples of the separation region.

An n ⁺ -type silicon single crystal region 28 is formed in region 26a. n ⁺ type silicon single crystal region 2
8 is located between the p-type base region 14a and the n-type base region 12. n ⁺ type silicon single crystal region 28 and p
The joint 40 is formed with the mold base region 14a. The n ⁺ -type silicon single crystal region 28 is an example of a fifth semiconductor region. That is, n ⁺ type silicon single crystal region 2
8 and the potential barrier formed by the concentration difference between the n-type base region 12
This value cannot be diffused to the mold base region 14a. The details of the function of the n ⁺ type silicon single crystal region 28 will be described in “Description of Operation”.

The region 26a has an n ⁺ -type emitter region 16
a and 16b are formed. n ⁺ type emitter region 16
a and 16b are located at a distance from each other on the surface of the p-type base region 14a. n ⁺ type emitter region 16a
Are in contact with the trench 22a. N ⁺ type emitter region 16b is in contact with trench 22b.

In the region 26b, a junction 38 is formed by the n-type base region 12 and the p-type base region 14b. No emitter region is formed in the p-type base region 14b.

In FIG. 1, n ⁺ type emitter regions 16a,
Region 26a in which 6b is formed, n ⁺ type emitter region 16
Regions 26b where a and 16b are not formed only appear one by one. The IGBT 1 includes a plurality of these regions.

On the trenches 22a, 22b and 22c,
An oxide layer 30 is formed. An electrode 32 is formed so as to cover oxide layer 30. The electrode 32 includes the n ⁺ -type emitter regions 16a and 16b and the p-type base region 14
a, 14b.

Next, the planar structure of the IGBT 1 will be described. FIG. 2 is a plan view of the IGBT 1. However, the electrode 32 and the oxide layer 30 are omitted. IGBT1 of FIG.
1 is a cross-sectional view taken along the line A-A. FIG.
As shown in FIG. 7, the region 26a and the region 26b are separated by the trench 22b. A plurality of p-type base regions 14a are formed in the region 26a. Around the p-type base region 14a, an n ⁺ -type emitter region 16 (16
a, 16b) are formed. On the other hand, p in the region 26b
No emitter region is formed in the mold base region 14b.

Note that the conductivity type of each region of the IGBT 1 shown in FIGS. 1 and 2 may be the opposite conductivity type. This means
The same can be said for other embodiments described later.

The IGBT 1 is of a trench gate type. The IGBT 1 can be applied to a planar type. This applies to other embodiments described later.

In the IGBT 1, the trench 22
Areas 26a and 26b are defined by a, 22b, and 22c. The IGBT 1 may define the regions 26a and 26b by another isolation technique such as a LOCOS method, for example. This applies to other embodiments described later.

{Description of Operation} The operation of the IGBT 1 will be described with reference to FIG. First, a description will be given from the turn ON.

(1) Trench gate electrodes 18a, 18
A positive voltage (for example, 10 to 20 V) is applied to b and 18c. Thus, the p-type base regions 14a and 14b have n
A channel 36 is formed.

(2) A positive voltage is applied to the electrode 34. The electrode 32 is grounded. Thereby, the p ⁺ type collector region 10
And a n-type base region 12 is applied with a forward bias voltage. As a result, holes are injected from p ⁺ -type collector region 10 into n-type base region 12.

(3) Since as many electrons as the number of injected holes are collected in the n-type base region 12 and the n ⁺ -type silicon single crystal region 28, the resistance of these regions is reduced. This is called conductivity modulation.

Thus, the IGBT 1 is turned on. Electrons are supplied from the n ⁺ -type emitter regions 16a and 16b, flow through the region 26a, pass through the n-type base region 12, the n ⁺ -type buffer region 20 and the p ⁺ -type collector region 10, and reach the electrode 34.

The holes are supplied from the p ⁺ -type collector region 10 and flow into the regions 26a and 26b through the n ⁺ -type buffer region 20 and the n-type base region 12.
The holes flowing into region 26a reach n ⁺ -type silicon single crystal region 28. The n ⁺ -type silicon single crystal region 28 serves as a barrier to holes, and the holes serve as p-type base regions 14.
a. On the other hand, the holes flowing into the region 26b flow through the p-type base region 14b and reach the electrode 32.

Next, turn-off will be described.

(1) Trench gate electrodes 18a, 18
The voltages applied to b and 18c are set to a threshold voltage or less (for example, 0 to -20 V). As a result, the n-channel 36 disappears.

(2) Hole injection from the p ⁺ -type collector region 10 to the n-type base region 12 stops. The holes that have already been injected also decrease in life. The holes remaining in the n-type base region 12 and the n ⁺ -type silicon single crystal region 28 flow to the region 26b, pass through the p-type base region 14b, and reach the electrode 32.

Thus, the IGBT 1 is turned off. Here, at the time of OFF, the p-type base region 14b and the n-type base region 1 extend from the junction 38 in the region 26b.
2, the breakdown voltage of the IGBT 1 is maintained. On the other hand, since the n ⁺ -type silicon single crystal region 28 has a high n-type impurity concentration, a depletion layer is not formed (or hardly formed) from the junction 40 in the region 26a.

According to the IGBT 1 as described above, latch-up can be prevented and the ON voltage can be reduced. First, the reason why latch-up can be prevented according to the IGBT 1 will be described. Prior to this description, latch-up by a parasitic thyristor of the IGBT will be described.

The IGBT has a parasitic thyristor due to its structure. This will be described using the IGBT 1 shown in FIG. 1 as an example. The parasitic thyristor is an n ⁺ -type emitter region 16.
a, 16b, a p-type base region 14a, an n-type base region 12, and a p ⁺ -type collector region 10.

Assuming that IGBT 1 does not have n ⁺ type silicon single crystal region 28, holes supplied from p ⁺ type collector region 10 pass through n type base region 12 and p type base region 14 a, Reaches 32. Incidentally, since the p-type base region 14a is grounded, the voltage is originally 0V. However, since holes flow through the p-type base region 14a, the p-type base region 14a is replaced by the n ⁺ -type emitter region 16 by the resistance of the p-type base region 14a.
The potential is higher than a and 16b. p-type base region 14a
When the potential difference between the n ⁺ -type emitter regions 16a and 16b exceeds the diffusion potential (about 0.7 V), some holes
It flows into the ⁺ type emitter regions 16a and 16b. Thereby, the npn transistor (n ⁺ type emitter region 16a,
16b, p-type base region 14a, n-type base region 12)
Turns ON. This becomes a trigger, and the parasitic thyristor operates. Since the parasitic thyristor cannot be controlled, a large amount of current continues to flow through the parasitic thyristor, and the IGB
T1 may be destroyed.

The IGBT 1 has an n ⁺ type silicon single crystal region 28. Therefore, the p ⁺ type collector region 10
From the n ⁺ type silicon single crystal region 2
8, the holes do not flow into the p-type base region 14a. Therefore, in the region 26a,
The parasitic thyristor does not operate. On the other hand, area 26
Since b has no emitter region, there is no parasitic thyristor. As described above, according to the IGBT 1, latch-up can be prevented.

Next, the reason why the ON voltage can be reduced according to the IGBT 1 will be described. Assuming that the IGBT 1 does not include the n ⁺ -type silicon single crystal region 28, a junction is formed by the n-type base region 12 and the p-type base region 14. The depletion layer formed from this junction causes IGB
T prevents dielectric breakdown. To increase the breakdown voltage of the IGBT, it is necessary to increase the extension of the depletion layer. For this purpose, the concentration of the n-type impurity in the n-type base region 12 must be reduced.

However, in the portion of the n-type base region 12 near the p-type base region 14, holes easily move to the p-type base region 14. For this reason, in this portion, the number of holes is reduced, and the number of electrons is also reduced. Therefore, the resistance of this portion increases. The ON voltage increases by this amount.

The IGBT 1 has an n ⁺ type silicon single crystal region 28. n ⁺ type silicon single crystal region 28 and n
The potential barrier formed by the p-type base region 12 and the p-type base region 1
This is a value that cannot be spread to 4a. For this reason, in the region 26a, n n near the n ⁺ type silicon single crystal region 28
The reduction of holes in the mold base region 12 can be suppressed, and the resistance at this portion does not increase. Therefore, IGBT
1 can be reduced.

Incidentally, the barrier value can be obtained by increasing the difference between the n-type impurity concentration of the n ⁺ -type silicon single crystal region 28 and the n-type impurity concentration of the n-type base region 12. The n-type impurity concentration of the n-type base region 12 is determined by the element breakdown voltage. Therefore, n
The barrier value is obtained by increasing the n-type impurity concentration of the ⁺ -type silicon single crystal region 28. Specifically, n
⁺ Type silicon single crystal region 28 has an n-type impurity concentration of 10
¹⁷ is a ~10 ²⁰ / cm ^3. The barrier value can also be obtained by increasing the thickness of the n ⁺ -type silicon single crystal region 28.

The n ⁺ type silicon single crystal region 28
It is also possible to lower the mold impurity concentration below the above value.
For example, the n ⁺ -type silicon single crystal region 28 has an n-type impurity concentration of 10 ¹⁴ to 10 ¹⁶ / cm ³ . According to this,
The n ⁺ type silicon single crystal region 28 cannot completely block holes. On the other hand, the extension of the depletion layer formed from the junction 40 can be increased, so that the breakdown voltage can be improved.

The n ⁺ type silicon single crystal region 2 described above
Regarding the n-type impurity concentration of 8, the same can be said of the embodiment including the n ⁺ -type silicon single crystal region 28 among other embodiments described later.

{Description of Manufacturing Method} Next, the manufacturing process of the IGBT 1 will be described. FIG. 3 is a process chart for explaining this.

As shown in FIG. 3A, a silicon substrate including p ⁺ -type collector region 10 is prepared. The thickness of p ⁺ -type collector region 10 is, for example, 200 to 400 μm. The p-type impurity concentration is, for example, 5 × 10 ¹⁸ / c
m is ^3.

P⁺For example, on the mold collector region 10,
If n⁺Mold buffer layer 20
Form. n⁺The thickness of the mold buffer layer 20 is, for example, 5
２０20 μm. The n-type impurity concentration is, for example,
5 × 10¹⁶~ 1 × 10¹⁸/ Cm ^ThreeIt is.

Next, on the n ⁺ -type buffer layer 20, for example,
An n-type base layer 12 is formed by epitaxial growth. The thickness of the n-type base layer 12 is, for example, 40 to 100.
μm. The n-type impurity concentration is, for example, 5 × 1
0 ¹³ to 1 × 10 ¹⁵ / cm ³ .

Next, a p-type base layer 14 is formed on the n-type base layer 12 by, for example, epitaxial growth. p
The thickness of the mold base layer 14 is, for example, 2 to 5 μm.
The p-type impurity concentration is, for example, 1 × 10 ^{16 to} 5 × 1.
0 ¹⁷ / cm ³ .

As shown in FIG. 3B, trenches 22a, 22b and 22c are formed at predetermined intervals in the structure of FIG. 3A by a known method. Trench 22a,
22 b and 22 c have reached the n-type base layer 12.
The depth d of the trenches 22a, 22b, 22c is, for example,
3 to 10 μm, and the width w is, for example, 0.5 to 2 μm.
It is.

The p-type base layer 14 is formed by the trench 22b.
Is separated into a p-type base layer 14a and a p-type base layer 14b. Region 26a is defined by trench 22a and trench 22b. The region 26b is defined by the trench 22b and the trench 22c.

Next, the trench 22 is formed using a known method.
A silicon oxide layer 24 is formed on the side surfaces and the bottom surface of a, 22b, and 22c. Then, the trench gate electrodes 18a, 18b, and 18c are formed in the trenches 22a, 22b, and 22c, respectively, using a known method. Next, a mask for opening the region 26a is formed on the p-type base layer 14. I do. Using this mask, an n ⁺ -type silicon single crystal region 28 is formed below the p-type base region 14a by ion-implanting an n-type impurity into the region 26a.

Next, a mask for partially opening the region 26a is formed on the p-type base layer 14. Using this mask, an n-type impurity is ion-implanted into a predetermined region of the region 26a, so that n ⁺ -type emitter regions 16a and 16
b is formed. Known conditions can be used as the conditions.

Thereafter, by using a usual method,
The IGBT 1 shown in FIG. 1 is completed.

There are also the following modifications. Referring to FIG. 3A, an n-type base 12 is formed. Next, in the n-type base region 12, a region corresponding to the region 26a is ion-implanted to form an n ⁺ -type silicon single crystal region 28.
To form Next, on the n-type base 12 and the n ⁺ -type silicon single crystal region 28, p
A mold base region 14 is formed. Next, the trench 22a,
22b and 22c are formed. And the silicon oxide layer 2
4. The trench gate electrodes 18a, 18b, 18c are formed. Next, the n ⁺ -type emitter region 16 is added to the region 26a.
a and 16b are formed. Subsequent steps are the same as the above-mentioned manufacturing method.

The following embodiments can also be manufactured by using the same method as the method of manufacturing the IGBT 1 shown in FIG. 1 or a modification thereof.

[Second Embodiment] FIG. 4 is a sectional view of an IGBT 3 according to a second embodiment of the present invention. Portions having functions equivalent to those of the IGBT 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. IGBT3 is IGB
The parts different from T1 will be described, and the description of the same parts will be omitted.

IGBT 3 is composed of p-type base region 14a and n-type base region 14a.
^An n − -type silicon single crystal region 42 is provided between the N-type silicon single crystal region 28 and the ⁺ type silicon single crystal region 28. A junction 44 is formed by the p-type base region 14a and the n − -type silicon single crystal region 42. The n-type impurity concentration in the n − -type silicon single crystal region 42 is a value sufficient to expand the depletion layer from the junction 44 to the region 26a. As a specific example, the n-type silicon single crystal region 42 has an n-type impurity concentration of, for example, 1 × 10 ¹⁴
１1 × 10 ¹⁶ / cm ³ .

According to the IGBT 3, the depletion layer can be expanded also in the region 26a, so that the breakdown voltage can be improved.

Note that according to the IGBT 3, the I shown in FIG.
For the same reason as the GBT 1, latch-up can be prevented and the ON voltage can be reduced.

[0073] The number of Third Embodiment In the first and second embodiments, n ⁺ -type emitter region 16a, the number of 16b is formed region, n ⁺ -type emitter region 16a, the region 16b is not formed Are plural. IGBT
If it is desired to further reduce the on-state voltage, the number of regions where the n ⁺ -type emitter regions 16a and 16b are formed may be increased. When importance is placed on preventing IGBT latch-up, n
The number of regions where the ⁺ type emitter regions 16a and 16b are not formed may be increased. In the IGBT according to the third embodiment of the present invention, the number of regions where the n ⁺ -type emitter regions 16a and 16b are formed is increased.

FIG. 5 is a block diagram showing a third embodiment of the present invention.
It is sectional drawing of GBT5. Portions having functions equivalent to those of the IGBT 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. The parts of the IGBT 5 that are different from the IGBT 1 will be described, and descriptions of the same parts will be omitted.

The IGBT 5 has an area 26c located adjacent to the area 26a. In the p-type base region 14c of the region 26c, n ⁺ -type emitter regions 16a and 16b are formed similarly to the region 26a.

According to the IGBT 5, the I shown in FIG.
For the same reason as the GBT 1, latch-up can be prevented and the ON voltage can be reduced.

[Fourth Embodiment] FIG. 6 is a sectional view of an IGBT 7 according to a fourth embodiment of the present invention. Portions having functions equivalent to those of the IGBT 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. IGBT7 is IGB
The parts different from T1 will be described, and the description of the same parts will be omitted.

The IGBT 7 does not include the n ⁺ type buffer region 20. That is, the IGBT 7 is a non-punch-through IGBT. Since the IGBT 7 is a non-punch-through type, the depletion layer does not spread over the entire n-type base region 12. On the other hand, since the IGBTs 1, 3, and 5 are of a punch-through type, the depletion layer can be spread over the entire n-type base region 12. Non-punch through type IGB
T is used for products requiring high withstand voltage. In addition,
According to the IGBT 7, latch-up can be prevented and the ON voltage can be reduced for the same reason as the IGBT 1 shown in FIG.

[Fifth Embodiment] FIG. 7 is a sectional view of an IGBT 9 according to a fifth embodiment of the present invention. Portions having functions equivalent to those of the IGBT 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. IGBT9 is I
Parts different from GBT1 will be described, and description of the same parts will be omitted.

The IGBT 9 does not include the n ⁺ type silicon single crystal region 28. Therefore, the IGBT 9 has no effect due to the provision of the n ⁺ type silicon single crystal region 28.

According to the IGBT 9, the possibility of latch-up can be reduced. That is, IGBT9 is
Region 2 in which n ⁺ -type emitter regions 16a and 16b are formed
6a and a region 26b where the n ⁺ -type emitter regions 16a and 16b are not formed. The holes flow to both regions 26a and 26b. As long as holes flow into the region 26a, the parasitic thyristor may operate. On the other hand, if holes flow into the region 26b, the parasitic thyristor does not operate. The IGBT 9 reduces the possibility of latch-up by providing a region 26b where the n ⁺ -type emitter regions 16a and 16b are not formed.

[Sixth Embodiment] FIG. 8 is a sectional view of an IGBT 2 according to a sixth embodiment of the present invention. Portions having functions equivalent to those of the IGBT 1 according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals. IGBT2 is IGB
The parts different from T1 will be described, and the description of the same parts will be omitted.

The IGBT 2 has n ⁺ -type emitter regions 16a and 16b in a region 26b. Therefore, IGBT
According to 2, since electrons flow in the region 26b, the ON voltage can be reduced.

According to IGBT 2, since it has n ⁺ type silicon single crystal region 28, the IGB shown in FIG.
For the same reason as T1, the ON voltage can be reduced.

[Seventh Embodiment] FIG. 9 is a sectional view of a power MOS field effect transistor 4 according to a seventh embodiment of the present invention. The structure of the power MOS field effect transistor 4 is different from the structure of the IGBT 1 according to the first embodiment shown in FIG. 1 in that the power MOS field effect transistor 4 does not include the p ⁺ -type collector region 10. In other structures, the power M
The OS field effect transistor 4 and the IGBT 1 are the same. Therefore, the reference numerals indicating the components of the power MOS field effect transistor 4 are the same as those of the IGBT 1. However, some components have different functions. That is, in the power MOS field-effect transistor 4, reference numeral 20 denotes a drain region, and reference numeral 12 denotes a drain region.
Is a drift region, reference numeral 14 is a body region,
Reference numerals 16a and 16b are source regions.

The effect of the power MOS field effect transistor 4 will be described. The source region 16a, 1
6b is not formed. Therefore, no parasitic bipolar transistor exists in region 26b. Therefore, the possibility of latch-up of the power MOS field effect transistor 4 can be reduced.

Further, since the power MOS field effect transistor 4 has the n ⁺ type silicon single crystal region 28, the ON resistance can be reduced accordingly.

The first to seventh embodiments are examples in which the present invention is applied to an IGBT or a power MOS field effect transistor. The present invention is not limited to this, and can be applied to other insulated gate semiconductor devices.

[Example of Circuit Having Embodiment of the Present Invention] FIG. 10 shows an inverter circuit 52 having an IGBT 1. The inverter circuit 52 converts a DC power supply 50 such as a battery into a three-phase AC and controls the rotation of the three-phase motor 48. The inverter circuit 52 is used, for example, to drive a motor of an electric vehicle. It should be noted that IGBTs 2, 3, 5, 7, 9 and a power MOS field effect transistor 4 can be used instead of the IGBT 1.

[Brief description of the drawings]

FIG. 1 is a sectional view of an IGBT 1 according to a first embodiment of the present invention.

FIG. 2 is a plan view of the IGBT 1 according to the first embodiment of the present invention.

FIG. 3 is a process diagram for explaining a manufacturing process of the IGBT 1 according to the first embodiment of the present invention.

FIG. 4 is a sectional view of an IGBT 3 according to a second embodiment of the present invention.

FIG. 5 is a sectional view of an IGBT 5 according to a third embodiment of the present invention.

FIG. 6 is a sectional view of an IGBT 7 according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view of an IGBT 9 according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view of an IGBT 2 according to a sixth embodiment of the present invention.

FIG. 9 is a sectional view of a power MOS field-effect transistor 4 according to a seventh embodiment of the present invention.

FIG. 10 is a circuit diagram of an inverter circuit including the IGBT 1 according to the first embodiment of the present invention.

[Description of Signs] 1, 2, 3, 5, 7, 9 IGBT 4 Power MOS field-effect transistor 10 p ⁺ -type collector region 12 n-type base region 14a, 14b, 14cp p-type base region 16a, 16b n ⁺ -type emitter Regions 18a, 18b, 18c Trench gate electrode 20n ⁺ buffer region 22a, 22b, 22c Trench 24 Silicon oxide layer 26a, 26b Region 28n ⁺ silicon single crystal region 30 Oxide layer 32, 34 Electrode 36 n channel 38, 40 Junction 42 n-type silicon single crystal region 44 Junction

Continuing from the front page (72) Inventor Masayasu Ishiko 41-cho, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture 1 Toyota Central Research Laboratory Co., Ltd.

Claims (11)

[Claims] 1. An insulated gate semiconductor device having a plurality of isolation regions separated from each other, comprising: a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, and a third semiconductor region of a second conductivity type. A semiconductor region, wherein the at least one isolation region includes the first semiconductor region and the second semiconductor region, and a carrier of a first conductivity type is supplied from the first semiconductor region; The region includes the third semiconductor region, and the isolation region including the third semiconductor region is not provided with a region for supplying a carrier of the first conductivity type. 2. The semiconductor device according to claim 1, further comprising a fourth semiconductor region of a first conductivity type and a fifth semiconductor region of a first conductivity type, wherein the fourth semiconductor region is provided in the isolation region including the third semiconductor region. The fifth semiconductor region is connected to the second semiconductor region and the fourth semiconductor region so that a depletion layer can be formed.
An insulated gate semiconductor device formed between the semiconductor region and the semiconductor region, wherein a concentration of the first conductivity type impurity in the fifth semiconductor region is higher than a concentration of the first conductivity type impurity in the fourth semiconductor region. 3. The barrier according to claim 2, wherein in the barrier formed by the fifth semiconductor region and the fourth semiconductor region, carriers of the second conductivity type cannot diffuse from the fourth semiconductor region to the second semiconductor region. Value, insulated gate semiconductor device. 4. The semiconductor device according to claim 2, further comprising a sixth semiconductor region of a first conductivity type, wherein the sixth semiconductor region includes the second semiconductor region and the fifth semiconductor region.
A sixth semiconductor region formed between the second semiconductor region and the second semiconductor region so that a depletion layer can be formed in the isolation region including the first semiconductor region and the second semiconductor region. Insulated gate semiconductor device. 5. The device according to claim 1, wherein the number of the isolation regions including the first semiconductor region and the second semiconductor region is equal to the number of the isolation regions including the third semiconductor region. , Insulated gate semiconductor devices. 6. The semiconductor device according to claim 1, wherein the number of the isolation regions including the first semiconductor region and the second semiconductor region is larger than the number of the isolation regions including the third semiconductor region. Insulated gate semiconductor device. 7. The method according to claim 1, wherein the isolation regions are separated from each other by a trench.
Insulated gate semiconductor device. 8. The insulated gate semiconductor device according to claim 1, wherein the insulated gate semiconductor device is a planar type. 9. An insulated gate semiconductor device having a plurality of isolation regions separated from each other, wherein the first conductivity type first semiconductor region, the second conductivity type second semiconductor region, and the first conductivity type third semiconductor region. A semiconductor region and a fourth semiconductor region of a first conductivity type, wherein the isolation region includes the first semiconductor region, the second semiconductor region, and the fourth semiconductor region; A carrier of a conductivity type is supplied, at least one of the isolation regions includes the third semiconductor region, and a barrier formed by the third semiconductor region and the fourth semiconductor region includes a carrier of a second conductivity type. A value that cannot be diffused from the fourth semiconductor region to the second semiconductor region; the third semiconductor region is not formed in at least one of the isolation regions; and the fourth semiconductor region is An insulated gate semiconductor device which is joined to the second semiconductor region so that a depletion layer can be formed. 10. An inverter circuit for converting DC power to AC power, the inverter circuit including any one of the insulated gate semiconductor devices according to claim 1. (A) forming a first conductivity type first semiconductor layer; and (b) forming a second conductivity type second semiconductor layer on the first semiconductor layer. c) a step of separating the second semiconductor layer into a plurality, and (d) at least one of the plurality of second semiconductor layers includes:
Forming a semiconductor region of the first conductivity type for supplying carriers of the first conductivity type, and not forming the semiconductor region in at least one of the plurality of second semiconductor layers. A method for manufacturing a gate type semiconductor device.