KR100742779B1 - Insulated gate bipolar transistor with multiple trench and method for menufacturing insulated gate bipolar transistor with multiple trench - Google Patents

Abstract

An insulated gate bipolar transistor using a multiple trench is provided to improve a latch-up characteristic by forming an oxide layer after a portion of a bipolar transistor in which a hole current path is formed is removed by a trench process. A polysilicon gate(220) is formed in the center of a cell in one cell pitch. A trench-type insulation region(210) is formed of the sidewall on the edge of the cell. An electrode(230) is formed between the polysilicon gate and the trench-type insulation region, made of a conductor. The polysilicon gate can have such a depth as to penetrate N-type and P-type regions of a high density and reach an N-type region of a low density.

Description

Insulated gate bipolar transistor with multiple trench and method of manufacturing the same {Insulated gate bipolar transistor with multiple trench and Method for menufacturing insulated gate bipolar transistor with multiple trench}

1 illustrates the structure of a conventional trench type insulated gate bipolar transistor.

2 is a top view of an insulated gate bipolar transistor using multiple trenches according to an exemplary embodiment of the present invention.

3 illustrates a structure of an insulated gate bipolar transistor using multiple trenches according to an embodiment of the present invention.

4 is a cross-sectional view of an insulated gate bipolar transistor to which multiple trenches are applied according to an embodiment of the present invention.

5A to 5L illustrate a manufacturing process of an insulated gate bipolar transistor using multiple trenches according to an embodiment of the present invention.

6A to 6B illustrate forward blocking voltage characteristics of the insulated gate bipolar transistor according to the related art and the present invention.

7A to 7B illustrate on-state voltage drop characteristics of an insulated gate bipolar transistor according to the related art and the present invention.

8A to 8B illustrate latch-up voltage characteristics of an insulated gate bipolar transistor according to the related art and the present invention.

9A to 9B illustrate latch-up current characteristics of an insulated gate bipolar transistor according to the related art and the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to power semiconductor devices, and more particularly, to an insulated gate bipolar transistor employing multiple trenches and a method of manufacturing the same.

Recently, an insulated gate bipolar transistor having a wide range of applications as a power device has advantages of low voltage drop and high speed switching. In general, an insulated gate bipolar transistor incorporating the concept of a device having both fast switching characteristics of a metal oxide semiconductor field effect transistor (hereinafter referred to as a MOSFET) and low on-resistance characteristics of a bipolar transistor. The low ON-resistance, fast switching speeds, and superior safety operating area (SOA) advantages replace the role of bipolar transistors in power applications.

The biggest problem with such insulated gate bipolar transistors is that they are very susceptible to latchup as parasitic thyristors are formed structurally, and various techniques have been developed to improve latchup.

Representative techniques for suppressing latchup include a method of improving latchup by reducing the resistance of the p-type body or by reducing the current flowing through the p-type body. A method of forming a highly doped p ++ diffusion region in the center of a p-type body as an effective method of reducing resistance is disclosed on pages 192 to 198 of the IEEE Transaction on Electron Device published in 1984. However, if the above p ++ diffusion region is formed, it is difficult to control the threshold voltage of the MOS transistor, so that the p-type body cannot be formed to completely surround the p-type body. As a result, there is a limit to improving latchup.

In addition, conventionally, the impurity layer is formed thick in the structure having the gate in the horizontal direction to produce the latch-up prevention layer to improve the latch-up characteristics. However, it is limited to the formation of a thick impurity layer in the basic horizontal gate structure.

1 illustrates the structure of a conventional trench type insulated gate bipolar transistor.

In the conventional trench type insulated gate bipolar transistor, a latch-up characteristic is deteriorated by a portion where a hole current path occurs. That is, due to an increase in the current path, the PN junction portion may be turned on, thereby causing latchup. Thus, the latchup current is reduced.

Therefore, the conventional insulated gate bipolar transistor has a problem in that it has a limitation in improving latch-up characteristics due to its structural characteristics.

Accordingly, the first technical problem to be achieved by the present invention is to apply multiple trenches in which forward blocking voltage characteristics, on-state voltage drop characteristics, and latch-up voltage and latch-up current characteristics can be improved. An insulated gate bipolar transistor is provided.

It is a second object of the present invention to provide a method of manufacturing an insulated gate bipolar transistor using the above multiple trenches.

In order to achieve the first technical problem, the present invention provides a semiconductor device, in one cell pitch, a polysilicon gate formed at the center of the cell, a trench type insulating region formed by sidewalls of the edge of the cell, and the polysilicon. An insulated gate bipolar transistor including multiple trenches including an electrode formed of a conductor between a gate and the trench type insulating region is provided.

On the other hand, in order to achieve the second technical problem, the present invention is to form epi silicon on silicon, injecting the P-type impurities and N-type impurities in the epi silicon, the step of heat-treating the epi silicon, one cell pitch Forming a first trench in an edge of the cell, filling an insulating material in the first trench, etching back the insulating material, forming a second trench in the center of the cell, and forming the second trench. Filling polysilicon into the trench, etching back the polysilicon, forming a third trench between the first trench and the second trench, filling a conductor in the third trench, and Provided is a method of manufacturing an insulated gate bipolar transistor using multiple trenches including etching back.

In addition, in order to achieve the second technical problem, the present invention is a step of implanting the P-type impurities and N-type impurities in a low concentration of the N-type wafer, the heat treatment of the wafer, within one cell pitch, the edge of the cell Forming a first trench in the first trench, filling an insulating material in the first trench, and etching back the insulating material, forming a second trench in the center of the cell, and filling a polysilicon in the second trench. Etching the polysilicon, forming a third trench between the first trench and the second trench, etching back the lower silicon into the wafer, and implanting impurities into the lower silicon to form an N type. Forming a layer and a high concentration P-type layer, filling a conductor inside the third trench, and etching back the conductor. A method of manufacturing an insulated gate bipolar transistor using a wrench is provided.

The present invention improves the latch-up characteristics by removing the trench with an impurity layer in which the latch-up may occur in the trench gate structure. The insulated gate bipolar transistor according to the present invention has a structure in which an oxide film is filled by digging trenches next to an emitter impurity layer in a trench gate structure. According to the present invention, a trench process for improving latch-up characteristics may be simultaneously performed during a trench process for a gate, thereby manufacturing a device more effectively.

Hereinafter, with reference to the drawings will be described a preferred embodiment of the present invention. However, embodiments of the present invention illustrated below may be modified in many different forms, and the scope of the present invention is not limited to the embodiments described below.

2 is a top view of an insulated gate bipolar transistor using multiple trenches according to an exemplary embodiment of the present invention.

The present invention improves the latch-up characteristic by removing a portion where a hole current path occurs through a trench process and then forming an oxide film.

Trench-type insulating regions 210 are formed within the cell pitch, as sidewalls of the edges of the cells. Like the insulated gate bipolar transistor array of FIG. 2, the oxide film 210 is formed on both sides to improve the latch-up characteristic. The reason why the layout is formed in a circle in FIG. 2 is because the latch-up characteristic is best when the circle is formed.

The polysilicon gate 220 is formed at the center of the cell, within one cell pitch.

A conductor is formed between the polysilicon gate 220 and the trench insulating region 210 of the electrode 230.

3 illustrates a structure of an insulated gate bipolar transistor using multiple trenches according to an embodiment of the present invention.

The trench-type insulating region (Silicon Oxide) of the first trench 310 is formed as a sidewall of the edge of the cell within one cell pitch.

Preferably, as shown in FIG. 3, the trench-type insulating region (Silicon Oxide) of the first trench 310 is formed to have a depth reaching the N-type region of low concentration while penetrating the N-type region and P-type region of high concentration. Can be. At this time, the low concentration N-type region is a uniform N-type (1E12 ~ 1E16 / cm3) region. In this case, the high concentration N-type region may have a doping concentration in a range between 1E13 and 1E20 / cm 3.

The poly Si gate of the second trench 320 is formed at the center of the cell within one cell pitch. Preferably, the poly Si gate of the second trench 320 may be surrounded by an insulating film formed on the sidewall. In this case, the insulating layer may include at least one of oxide (SiO 2), oxy nitride (SiON), silicon nitride (SiN), or hafnium oxide (HfO).

Preferably, as shown in FIG. 3, the polysilicon gate of the second trench 320 may be formed to a depth reaching the low concentration N type region while penetrating the high concentration N type region and the P type region. Can be.

Preferably, as shown in FIG. 3, the poly silicon gate of the second trench 320 may be surrounded by an insulating film formed on the sidewall.

An electrode of the third trench 330 is formed of a conductor between a poly silicon gate of the second trench 320 and a trench type insulating region of the first trench 310. Preferably, the conductor may include at least one of aluminum (Al), tungsten (W) or kappa (Cu). The trench type insulating region of the first trench 310 may be formed of an insulating material other than silicon oxide. In the present invention, the insulating material may be any one of oxide (SiO 2), oxy nitride (SiON), silicon nitride (SiN), or hafnium oxide (HfO).

Preferably, as shown in FIG. 3, the electrode may be formed at a depth lower than that of the low concentration N type region while penetrating the high concentration of the N type region and the P type region.

According to another exemplary embodiment of the present invention, an insulated gate bipolar transistor including multiple trenches has a structure in which two vertical moss are formed in one cell pitch and a trench insulating structure is formed on both sidewalls of a cell in a semiconductor device.

An insulated gate bipolar transistor using multiple trenches according to another embodiment of the present invention has a structure in which a vertical bipolar transistor is formed in a semiconductor device with two vertical source and drain regions in one cell pitch.

4 is a cross-sectional view of an insulated gate bipolar transistor to which multiple trenches are applied according to an embodiment of the present invention.

Trench-type isolation regions 410 are formed within the cell pitch, as sidewalls of the edges of the cells. As shown in FIG. 4, by forming oxide films 410 on both sides, latch-up characteristics are improved.

The polysilicon gate 420 is formed at the center of the cell, within one cell pitch.

A conductor is formed between the polysilicon gate 420 of the electrode 430 and the trench insulating region 410.

5A to 5L illustrate a manufacturing process of an insulated gate bipolar transistor using multiple trenches according to an embodiment of the present invention.

According to the present invention, the number of trench gates in an insulated gate bipolar transistor is increased in one cell to increase latchup and current capacity, and can be implemented through any one of the following two processes.

One of the two processes is to form epi silicon on silicon and inject P-type and N-type impurities into the silicon, heat-treat the epi silicon, form a first trench at the edge of the cell within one cell pitch, Filling the insulating material inside the first trench and etching back the insulating material, forming a second trench in the center of the cell, filling the polysilicon inside the second trench, and etching back the polysilicon; and the first trench and the second Forming a third trench between the trenches, filling the inside of the third trench, and etching back the conductor.

The other one of the two processes is to inject P-type impurities and N-type impurities into a low concentration N-type wafer, heat-treat the wafer, form a first trench at the edge of the cell within one cell pitch, and then Etching the insulating material by filling an insulating material in the cell, forming a second trench in the center of the cell, filling the polysilicon inside the second trench, and etching back the polysilicon, and forming a second trench between the first trench and the second trench. 3 The process of forming a trench, the process of etching back the lower silicon into the wafer and injecting impurities into the lower silicon to form an N-type layer and a high concentration P-type layer, and filling the conductor into the third trench, It includes a process to cure it.

The following describes the former of two processes.

First, after forming epi silicon on silicon as shown in FIG. 5a, impurities are implanted to maintain proper conductivity of the epi silicon. As the impurity at this time, boron, phosphorus, arsenic, or the like may be applied according to the use of the insulated gate bipolar transistor. As shown in FIG. 5A, the top of the silicon is implanted with N-type impurities, the lower part is implanted with P-type impurities, and the epi is implanted with impurities such that the N-type is itself. After that, heat treatment is performed to activate impurities.

Next, as shown in FIG. 5B, a first trench is formed in silicon using a photolithography process. The etching process at this time applies a dry etching process.

Next, as shown in Figure 5c to fill the insulating material in the trench. At this time, the insulating material mainly applies SiO 2 and forms an insulator by chemical vapor deposition (CVD).

Thereafter, as illustrated in FIG. 5D, an etch back for planarization is performed. CMP (Chemical Mechanical Polishing) or dry etching is used.

Next, as shown in FIG. 5E, a second trench, which is a region in which the gate of the transistor is to be formed, is formed through a photolithography and an etching process.

Thereafter, an insulating film is formed on the trench inner sidewall as shown in FIG. 5F. As the insulating film, materials such as silicon oxide (SiO 2), silicon nitride (SiN), silicon oxy nitride (SiON), and the like may be used, and the thickness thereof may be generally 100 to 1000 μm.

Then, polysilicon is filled into the trench as shown in FIG. 5g. In this case, polysilicon is a material having excellent conductivity, which is doped with N type.

Next, as illustrated in FIG. 5H, polysilicon is etched back using CMP (Chemical Mechanical Polishing) or dry etching to reveal silicon to be an active region.

Next, a third trench is formed by applying a photolithography process as shown in FIG. 5I. At this time, the third trench has a depth lower than that of the first / second trenches, and the conductor is later filled to serve to electrically ground the silicon. The back of the silicon is then etched back to form a contact on the back of the silicon. At this time, grinding | polishing by CMP is mainly performed.

Then, as shown in FIG. 5J, the resistance of the contact surface is reduced and the backside P + impurity is implanted for the hole injection.

Next, as shown in FIG. 5K, the third trench is filled with a conductor, and as shown in FIG. 5L, the conductor is etched back to complete the basic process.

In reality, subsequent steps such as a process of forming a contact and a process of forming a wiring are performed later. However, since this is a process of a conventional semiconductor, it will not be described here.

6A to 6B illustrate forward blocking voltage characteristics of the insulated gate bipolar transistor according to the related art and the present invention. 7A to 7B illustrate on-state voltage drop characteristics of an insulated gate bipolar transistor according to the related art and the present invention. 8A to 8B illustrate latch-up voltage characteristics of an insulated gate bipolar transistor according to the related art and the present invention. 9A to 9B illustrate latch-up current characteristics of an insulated gate bipolar transistor according to the related art and the present invention.

As shown in FIGS. 6A to 9B, the on-state voltage drop, latch-up voltage, and latch-up current characteristics of the insulated gate bipolar transistor according to the present invention are improved compared to the conventional trench type insulated gate bipolar transistor. Able to know.

Preferably, a method for manufacturing an insulated gate bipolar transistor using the multiple trenches of the present invention may be provided by recording a program for executing in a computer on a computer-readable recording medium.

The invention can be implemented via software. When implemented in software, the constituent means of the present invention are code segments that perform the necessary work. The program or code segments may be stored on a processor readable medium or transmitted by a computer data signal coupled with a carrier on a transmission medium or network.

The computer-readable recording medium includes all kinds of recording devices in which data is stored which can be read by a computer system. Examples of computer-readable recording devices include ROM, RAM, CD-ROM, DVD ± ROM, DVD-RAM, magnetic tape, floppy disks, hard disks, optical data storage devices, and the like. The computer readable recording medium can also be distributed over network coupled computer devices so that the computer readable code is stored and executed in a distributed fashion.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary and will be understood by those of ordinary skill in the art that various modifications and variations can be made therefrom. However, such modifications should be considered to be within the technical protection scope of the present invention. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, according to the present invention, the forward blocking voltage characteristics, the on-state voltage drop characteristics, the latch-up voltage, and the latch-up current characteristics of the insulated gate bipolar transistor can be improved. It works.

Claims (12)

In a semiconductor device, A poly silicon gate formed at the center of the cell within one cell pitch; A trench isolation region formed by sidewalls of the edge of the cell; And An insulated gate bipolar transistor including multiple trenches including an electrode formed of a conductor between the polysilicon gate and the trench insulation region. The method of claim 1, The polysilicon gate is An insulated gate bipolar transistor using multiple trenches formed through a high concentration of an N type region and a P type region and reaching a low concentration of an N type region. The method of claim 1, The polysilicon gate is An insulating gate bipolar transistor using multiple trenches, wherein the insulating layer is surrounded by an insulating layer formed on sidewalls, wherein the insulating layer includes at least one of oxide, oxy nitride, silicon nitride, and hafnium oxide. The method of claim 1, The trench isolation region is An insulated gate bipolar transistor using multiple trenches formed through a high concentration of an N type region and a P type region and reaching a low concentration of an N type region. The method of claim 1, The electrode is An insulated gate bipolar with multiple trenches penetrating high-concentration N-type and P-type regions, formed at a lower depth than low-concentration N-type regions, and wherein the conductor comprises at least one of aluminum, tungsten, or kappa. transistor. Forming epi silicon on silicon, and implanting P-type impurities and N-type impurities into the epi silicon; Heat-treating the epi silicon; Forming a first trench at an edge of the cell, filling an insulating material inside the first trench, and etching back the insulating material within one cell pitch of the silicon; Forming a second trench in the center of the cell, filling polysilicon into the second trench, and etching back the polysilicon; And Forming a third trench between the first trench and the second trench, filling a conductor in the third trench, and etching back the conductor; Way. The method of claim 6, Etching back the polysilicon And forming the second trench at a depth that penetrates the high concentration of the N type region and the P type region and reaches a low concentration of the N type region. The method of claim 6, Etching back the polysilicon Forming an insulating film on the sidewalls, The insulating film is 12. A method of fabricating an insulated gate bipolar transistor with multiple trenches comprising at least one of oxide, oxy nitride, silicon nitride or hafnium oxide. The method of claim 6, Etching back the insulating material And forming the first trench at a depth that penetrates the high concentration of the N type region and the P type region and reaches the low concentration of the N type region. The method of claim 6, Etching back the conductor And forming the third trench through a high concentration of an N type region and a P type region and having a depth lower than that of a low concentration of the N type region. The method of claim 6, Etching back the conductor And wherein the conductor comprises at least one of aluminum, tungsten or kappa. Implanting P-type impurities and N-type impurities into the low concentration N-type wafer; Heat treating the wafer; Forming a first trench at an edge of the cell, filling an insulating material inside the first trench, and etching back the insulating material within one cell pitch of the wafer; Forming a second trench in the center of the cell, filling polysilicon into the second trench, and etching back the polysilicon; Forming a third trench between the first trench and the second trench; Etching back the lower silicon into the wafer and implanting impurities into the lower silicon to form an N type layer and a high concentration P type layer; Heat-treating the N-type layer and the high concentration P-type layer; And A method of manufacturing an insulated gate bipolar transistor using multiple trenches, the method comprising filling a conductor in the third trench and etching back the conductor.

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