CN117542890A - Trench gate semiconductor device and method of manufacturing the same - Google Patents

Trench gate semiconductor device and method of manufacturing the same Download PDF

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Publication number
CN117542890A
CN117542890A CN202311425834.2A CN202311425834A CN117542890A CN 117542890 A CN117542890 A CN 117542890A CN 202311425834 A CN202311425834 A CN 202311425834A CN 117542890 A CN117542890 A CN 117542890A
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trench
gate
source
semiconductor device
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郑辉
曾大杰
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Shenzhen Shangyangtong Technology Co ltd
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Shenzhen Shangyangtong Technology Co ltd
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Abstract

The invention discloses a trench gate semiconductor device, the device unit includes: the semiconductor device comprises a trench gate, a source trench and a first semiconductor epitaxial layer doped with a first conductivity type, wherein the first semiconductor epitaxial layer is positioned between the source trench and the trench gate and is used as a platform region. The channel region is formed in the mesa region, and the source region is formed in a surface region of the channel region. The gate trench of the trench gate passes longitudinally through the channel region. The source electrode groove is filled with a source electrode lead-out metal. A bottom doped region with heavy doping of the second conductivity type is formed in the bottom region of the source electrode groove in a self-aligned mode, the bottom doped region wraps the bottom of the source electrode lead-out metal, ohmic contact is formed on the bottom doped region, and the side face of the source electrode lead-out metal is in contact with the channel region and the source region. In the longitudinal direction, the bottom surface of the gate trench is located within the depth of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate. The invention also discloses a manufacturing method of the trench gate semiconductor device. The invention can reduce the electric field intensity of the bottom area of the trench gate.

Description

Trench gate semiconductor device and method of manufacturing the same
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a trench gate semiconductor device; the invention also relates to a manufacturing method of the trench gate semiconductor device.
Background
Compared with Si, siC has wider forbidden bandwidth and higher critical breakdown field strength. Therefore, under the condition of the same withstand voltage, the length of the drift region of the SiC device can be greatly reduced, and the doping concentration of the drift region can be greatly improved. Based on this, siC has recently received increasing attention.
Based on SiC materials, more and more devices are being introduced. SiC MOSFETs are one of the most important types of devices. SiC MOSFETs are currently mainly planar and limited by the JFET effect of the channel and drift regions, with minimum cell sizes being difficult to reduce to 3 μm and below.
The trench MOSFET, namely the MOSFET adopting the trench gate, has smaller cell size and better performance because the JFET effect is eliminated. And more importantly, the oxide layer of the SiC MOSFET has high defect density and low mobility. The adoption of the trench MOSFET can obtain higher mobility by selecting the crystal orientation of the oxide layer. The trench type SiC MOSFET is thus a future direction. However, the biggest problem to be solved in the trench SiC MOSFET is how to reduce the electric field intensity at the bottom of the trench, and only the electric field intensity at the bottom of the trench gate is reduced, so that the gate dielectric layer, such as gate oxide, can be protected.
According to the gaussian theorem, the electric field strength of the device in the semiconductor and oxide layer meets the following formula:
Wherein E is semi Is the critical electric field strength, epsilon, of the semiconductor device semi And epsilon oxide The dielectric constants of the semiconductor material and the oxide layer material, respectively. Because the critical electric field strengths of Si and SiC differ by a factor of 10. For Si devices, the gate dielectric layer is dioxygenIn silicon carbide, the electric field strength is difficult to exceed 3X 10 in case of combination 6 V*cm -1 . While for SiC devices, the dielectric constant (epsilon) of SiC semi ) And silicon dioxide dielectric constant (. Epsilon.) oxide ) The ratio of (2) is usually about 2.6, and the electric field strength can be as high as 9×10 in an insulating layer such as silicon dioxide when the critical electric field strength of SiC at the interface of SiC and the insulating layer corresponding to the gate dielectric layer is 3e6V/cm 6 V*cm -1 This has reached or exceeded the critical electric field strength of silicon dioxide. That is, in the Si device, the electric field strength of the gate oxide remains at a low value when the electric field strength in the Si material reaches the critical electric field strength; however, in SiC devices, when the electric field strength in the SiC material reaches the critical electric field strength, the electric field strength of the gate oxide reaches or exceeds the critical electric field strength of the gate oxide, which causes breakdown of the gate oxide, thereby creating reliability problems. Therefore, for the SiC MOSFET, a proper device structure and a proper design method are adopted, so that the electric field intensity of a gate oxide interface at the bottom of the trench gate is reduced when the device breaks down, and the reliability of the device is particularly important.
Disclosure of Invention
The invention aims to provide a trench gate semiconductor device which can shield the electric field intensity of the bottom area of a trench gate, so that the electric field intensity of the bottom area of the trench gate can be reduced, and the reliability of the device is improved; and the method has the advantages of simple process, easy realization and no need of adding extra photolithography mask. The invention also provides a manufacturing method of the trench gate semiconductor device.
In order to solve the above technical problems, a device unit of a trench gate semiconductor device provided by the present invention includes:
the semiconductor device comprises a first semiconductor epitaxial layer doped with a first conductivity type, and a trench gate formed in a selected area of the first semiconductor epitaxial layer, wherein the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench.
And the source electrode groove is formed in a selected area of the first semiconductor epitaxial layer, and the first semiconductor epitaxial layer positioned between the source electrode groove and the groove gate is a platform area.
A channel region doped with a second conductivity type is formed in the mesa region, and a source region heavily doped with the first conductivity type is formed in a surface region of the channel region.
The gate trench extends longitudinally through the channel region, and a surface area of a first side of the channel region covered by the trench gate side is used to form a channel.
And filling a source extraction metal in the source trench.
And a bottom doping region which is heavily doped with the second conductivity type is formed in the bottom region of the source electrode groove in a self-aligned mode, the bottom doping region wraps the bottom of the source electrode lead-out metal, ohmic contact is formed, and the side face of the source electrode lead-out metal is contacted with the second side face of the channel region and the second side face of the source region and is used for leading out the channel region and the source region.
In the longitudinal direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field intensity of the bottom region of the trench gate.
A further improvement is that the depth of the channel region increases gradually from the first side to the second side of the channel region.
The channel region is an inclined ion implantation region, the channel region is formed by adopting inclined ion implantation after the source electrode groove is opened, and the inclined ion implantation is implanted into the platform region from the top surface of the platform region and the side surface of the source electrode groove to form the channel region.
The trench gate semiconductor device is a MOS transistor, and a first conductive type heavily doped drain region is formed on the back surface of the first semiconductor epitaxial layer; the drain region is composed of a thinned semiconductor substrate heavily doped with the first conductivity type or the drain region is composed of a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate.
Or the trench gate semiconductor device is an IGBT device, and a collector region heavily doped with the second conductivity type is formed on the back surface of the first semiconductor epitaxial layer; the collector region is composed of a thinned second-conductivity-type-heavily-doped semiconductor substrate or the collector region is composed of a second-conductivity-type-heavily-doped back-side ion implantation region formed in the thinned semiconductor substrate.
In a further improvement, when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
When the trench gate semiconductor device is an IGBT, a field stop layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
A further improvement is that the semiconductor device includes a plurality of said device cells connected in parallel, each of said device cells being formed in a device cell region.
A transition region surrounds a periphery of the device cell region, and a termination region surrounds a periphery of the transition region.
A second trench is formed in the first semiconductor epitaxial layer of the transition region and a plurality of third trenches are formed in the first semiconductor epitaxial layer of the termination region.
The second trench and each of the third trenches are formed simultaneously with the source trench.
A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between each of the third trenches, the second well region and the channel region having the same process structure and being formed simultaneously.
And filling first lead-out metals in the second trenches and filling second lead-out metals in the second trenches, wherein the first lead-out metals, the second lead-out metals and the source lead-out metals have the same process structure and are formed simultaneously.
And forming a second bottom doping region heavily doped with the second conductivity type at the bottom of each second groove and the bottom of each third groove, wherein the process structure of each second bottom doping region is the same as and is formed simultaneously with the process structure of the bottom doping region.
The tops of the source electrode leading-out metal and the first leading-out metal are connected with a source electrode formed by a front metal layer, and the second leading-out metal floats.
The width of the second groove is more than 10 times of the width of the source groove; the width of the third groove is larger than or equal to the width of the source groove.
And the spacing between the second grooves or the third grooves is larger than or equal to the spacing between the source grooves.
The pitches between the second trenches or the third trenches are equal or the pitches between the second trenches or the third trenches gradually increase in the direction from the device cell region to the termination region.
The number of the third grooves is set according to the operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third grooves is.
The trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.
In order to solve the above technical problems, in the method for manufacturing a trench gate semiconductor device provided by the present invention, the forming steps of the device unit include:
a first semiconductor epitaxial layer with first conductivity type doping is provided, a trench gate is formed in a selected area of the first semiconductor epitaxial layer, and the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench.
And forming a hard mask layer on the surface of the first semiconductor epitaxial layer, and carrying out graphical etching on the hard mask layer, wherein an opening area of the hard mask layer is a source electrode groove forming area.
Etching the first semiconductor epitaxial layer by taking the hard mask layer as a mask to form a source electrode groove; the first semiconductor epitaxial layer is located between the source trench and the trench gate and serves as a mesa region.
And taking the hard mask layer as a blocking layer, performing ion implantation of heavy doping of the second conductivity type on the bottom region of the source electrode groove to form a bottom doping region in a self-aligned mode, wherein implantation energy of the ion implantation of the bottom doping region is ensured not to pass through the hard mask layer outside the source electrode groove.
Performing second-conductivity-type inclined ion implantation by taking the hard mask layer as a blocking layer, wherein the inclined ion implantation is performed from the top surface of the platform region and the side surface of the source electrode groove to the platform region to form a channel region; the depth of the channel region gradually increases from the first side surface to the second side surface of the channel region; the gate trench extends longitudinally through the channel region, and a surface area of a first side of the channel region covered by the trench gate side is used to form a channel.
And removing the hard mask layer, and filling source electrode leading-out metal in the source electrode groove.
And forming a heavily doped source region of the first conductivity type on the surface of the channel region of the platform region.
The bottom doping region wraps the bottom of the source extraction metal and forms ohmic contact, and the side surface of the source extraction metal is contacted with the second side surface of the channel region and the second side surface of the source region and is used for extracting the channel region and the source region.
In the longitudinal direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field intensity of the bottom region of the trench gate.
The further improvement is that the trench gate semiconductor device is a MOS transistor, the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front-side process is completed, the method further comprises the following back-side process:
and thinning the back surface of the semiconductor substrate.
The semiconductor substrate is heavily doped with a first conductive type, and a drain region is formed by the semiconductor substrate with the back thinned; or, performing back ion implantation of the first conductive type heavy doping to form a drain region in the thinned semiconductor substrate.
Or, the trench gate semiconductor device is an IGBT device, and the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front side process is completed, the method further includes the following back side process:
thinning the back surface of the semiconductor substrate; the semiconductor substrate is heavily doped with a second conductive type, and a collector region is formed by the semiconductor substrate with the back thinned; alternatively, back side ion implantation of heavy doping of the second conductivity type is performed to form a collector region in the thinned semiconductor substrate.
In a further improvement, when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
When the trench gate semiconductor device is an IGBT, a field stop layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
A further improvement is that the semiconductor device includes a plurality of said device cells connected in parallel, each of said device cells being formed in a device cell region.
A transition region surrounds a periphery of the device cell region, and a termination region surrounds a periphery of the transition region.
A second trench is formed in the first semiconductor epitaxial layer of the transition region and a plurality of third trenches are formed in the first semiconductor epitaxial layer of the termination region.
The second trench and each of the third trenches are formed simultaneously with the source trench.
A second well region is formed between the source trench and the second trench, between the second trench and the third trench, and between each of the third trenches, the second well region and the channel region having the same process structure and being formed simultaneously.
And filling first lead-out metals in the second trenches and filling second lead-out metals in the second trenches, wherein the first lead-out metals, the second lead-out metals and the source lead-out metals have the same process structure and are formed simultaneously.
And forming a second bottom doping region heavily doped with the second conductivity type at the bottom of each second groove and the bottom of each third groove, wherein the process structure of each second bottom doping region is the same as and is formed simultaneously with the process structure of the bottom doping region.
The tops of the source electrode leading-out metal and the first leading-out metal are connected with a source electrode formed by a front metal layer, and the second leading-out metal floats.
The width of the second groove is more than 10 times of the width of the source groove; the width of the third groove is larger than or equal to the width of the source groove.
And the spacing between the second grooves or the third grooves is larger than or equal to the spacing between the source grooves.
The pitches between the second trenches or the third trenches are equal or the pitches between the second trenches or the third trenches gradually increase in the direction from the device cell region to the termination region.
The number of the third grooves is set according to the operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third grooves is.
The trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.
The trench gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The invention sets the source groove in the device unit of the groove gate semiconductor device and forms the bottom doping area of the second conductive type heavy doping in the bottom of the source groove, the depth of the source groove is similar to or slightly deeper than the depth of the grid groove, the depth of the bottom surface of the grid groove can be positioned in the depth range of the bottom doping area, thus the bottom area of the groove gate can be shielded by the bottom doping area, so that the electric field lines converged at the bottom area of the groove gate, especially at the bottom corner of the groove gate, are reduced when the device is reversely biased, the electric field intensity of the bottom area of the groove gate can be reduced, and the reliability of the device is improved; the invention is particularly suitable for SiC devices, and improves the reliability of SiC devices such as SiC MOSFET devices.
The source electrode groove is also used for filling metal to form source electrode leading-out metal leading out of the channel region and the source electrode region, and the bottom doping region can be used as an ohmic contact region between the channel region and the source electrode leading-out metal at the same time, so that the invention does not need to introduce an additional process structure, and is beneficial to the size reduction of a device.
In addition, the channel region can be formed by adopting ion implantation with an inclined angle after the source electrode groove is formed and before filling, and the bottom doped region can also be formed at the bottom of the source electrode groove by adopting vertical ion implantation self-alignment after the source electrode groove is formed, so that the channel region and the bottom doped region do not need to additionally introduce a photoetching plate, and the method is easy to realize, simple in process and low in cost.
In addition, the angled ion implantation can also gradually increase the depth of the channel region from the trench gate to the source trench, which is beneficial to reducing the JFET effect of the device.
The structure of the source electrode groove, the channel region and the bottom doped region can be applied to the transition region and the terminal region, so that the terminal structure does not need an extra photoetching plate, and the process cost can be reduced; moreover, the voltage resistance of the device can be adjusted by adjusting the number of the third grooves corresponding to the source grooves in the terminal area, so that the applicability of the invention is better.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic structural view of a device unit of a trench gate semiconductor device according to a first embodiment of the present invention;
fig. 2 is a schematic structural view of a termination structure of a trench gate semiconductor device according to a first embodiment of the present invention;
fig. 3 is a schematic structural view of a device unit of a trench gate semiconductor device according to a second embodiment of the present invention;
fig. 4A is a schematic view of a device structure in which a bottom doped region is formed in a method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention;
fig. 4B is a schematic view of a device structure for forming a channel region in the method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention.
Detailed Description
As shown in fig. 1, a schematic structure of a device unit of a trench gate semiconductor device according to a first embodiment of the present invention; the device unit of the trench gate semiconductor device of the embodiment of the invention comprises:
a first semiconductor epitaxial layer 3 having a first conductivity type doping, and a trench gate is formed in a selected region of the first semiconductor epitaxial layer 3, the trench gate including a gate trench 10, a gate dielectric layer 4 formed on an inner side surface of the gate trench 10, and a gate conductive material layer 5 filled in the gate trench 10.
A source trench 11 formed in a selected region of the first semiconductor epitaxial layer 3, the first semiconductor epitaxial layer 3 located between the source trench 11 and the trench gate being a mesa region.
A channel region 8 doped with the second conductivity type is formed in the mesa region, and a source region 9 heavily doped with the first conductivity type is formed in a surface region of the channel region 8.
The gate trench 10 extends longitudinally through the channel region 8 and the surface area of the first side of the channel region 8 covered by the trench gate side is used to form a channel.
The first semiconductor epitaxial layer 3 at the bottom of the channel region 8 constitutes a drift region.
The source trench 11 is filled with a source extraction metal 7.
A bottom doped region 6 heavily doped with the second conductivity type is formed in the bottom region of the source trench 11 in a self-aligned manner, and the bottom doped region 6 wraps the bottom of the source extraction metal 7 and forms an ohmic contact, and the side surface of the source extraction metal 7 contacts the second side surface of the channel region 8 and the second side surface of the source region 9 and serves to extract the channel region 8 and the source region 9.
In the longitudinal direction, the bottom surface of the gate trench 10 is located within the depth range of the bottom doped region 6, and the bottom doped region 6 forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field strength of the bottom region of the trench gate. As shown in fig. 1, if the bottom doped region 6 is not provided during reverse bias of the device, the electric lines of force are easily converged at the bottom of the gate trench 10, particularly at the bottom corner; in the first embodiment of the present invention, the bottom doped region 6 is provided, so that the bottom doped region 6 can deplete the drift region, and the bottom doped region 6 attracts most of the electric lines of force, so that the electric lines of force converging to the bottom region of the gate trench 10 can be shielded, thereby reducing the electric field strength of the bottom region of the trench gate.
In the first embodiment of the present invention, the depth of the channel region 8 gradually increases from the first side to the second side of the channel region 8. This structural arrangement of the channel region 8 reduces the JFET effect formed by the channel region 8 and the drift region; in the prior art, in order to reduce the electric field intensity at the bottom of the trench gate, a serious JFET effect is often introduced.
The channel region 8 is an inclined ion implantation region, and the channel region 8 is formed by using an inclined ion implantation after the source trench 11 is opened, and the inclined ion implantation is implanted into the mesa region from the top surface of the mesa region and the side surface of the source trench 11 to form the channel region 8. In this way, the channel region 8 does not require the addition of an additional reticle.
Similarly, the bottom doped region 6 is self-aligned to the bottom of the source trench 11, so no additional photolithography is required.
In the first embodiment of the present invention, the trench gate semiconductor device is a MOS transistor, and a heavily doped drain region of the first conductivity type is formed on the back surface of the first semiconductor epitaxial layer 3; the drain region is composed of a thinned semiconductor substrate 1 heavily doped with the first conductivity type. In other embodiments can also be: the drain region is composed of a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate 1.
When the trench gate semiconductor device is a MOS transistor, a buffer layer 2 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the semiconductor substrate 1, and the doping concentration of the buffer layer 2 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1. The buffer layer 2 is also an epitaxial layer, but has a doping concentration between the first semiconductor epitaxial layer 3 and the semiconductor substrate 1, which reduces defects of the semiconductor substrate 1 affecting the first semiconductor epitaxial layer 3 and thus the performance of the device.
Fig. 2 is a schematic structural view of a termination structure of a trench gate semiconductor device according to a first embodiment of the present invention; in a first embodiment of the present invention, a semiconductor device includes a plurality of the device cells connected in parallel, each of the device cells being formed in a device cell region.
A transition region surrounds a periphery of the device cell region, and a termination region surrounds a periphery of the transition region.
In fig. 2, the right side of the dashed line AA is the device unit region, that is, the cell region, and the transition region is between the dashed lines AA and BB; to the left of the dashed line BB is the termination region. A termination structure is located in the transition region and the termination region.
A second trench 11a is formed in the first semiconductor epitaxial layer 3 of the transition region and a plurality of third trenches 11b are formed in the first semiconductor epitaxial layer 3 of the termination region.
The second trench 11a and each of the third trenches 11b are formed simultaneously with the source trench 11.
A second well region (not shown) having the same process structure and simultaneously formed as the channel region 8 is formed between the source trench 11 and the second trench 11a, between the second trench 11a and the third trench 11b, and between each of the third trenches 11b.
The second trenches 11a are filled with a first lead-out metal 7a, and each of the second trenches 11a is filled with a second lead-out metal 7b, and the first lead-out metal 7a, the second lead-out metal 7b, and the source lead-out metal 7 have the same process structure and are formed simultaneously.
A second bottom doping region (not shown) heavily doped with the second conductivity type is formed at the bottom of each of the second trenches 11a and the third trenches 11b, and the process structure of each of the second bottom doping regions is the same as and is simultaneously formed with the process structure of the bottom doping region 6.
The source extraction metal 7 and the top of the first extraction metal 7a are both connected to a source (not shown) formed of a front side metal layer, and the second extraction metal 7b floats.
The front side structure of the device further comprises: an interlayer film and a front metal layer; forming a grid electrode and the source electrode after the front metal layer is patterned; the gate electrode is contacted with the gate conductive material layer through a contact hole penetrating the interlayer film.
In some embodiments, the width of the second trench 11a is more than 10 times the width of the source trench 11; the width of the third trench 11b is equal to or greater than the width of the source trench 11.
The spacing between the second trenches 11a or the third trenches 11b is equal to or greater than the spacing between the source trenches 11.
The pitches between the second trenches 11a or the third trenches 11b are equal or the pitches between the second trenches 11a or the third trenches 11b gradually increase in the direction from the device unit region to the termination region.
The number of the third trenches 11b is set according to an operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third trenches 11b is.
In the first embodiment of the present invention, the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer 3 is SiC; the material of the buffer layer 2 and the semiconductor substrate 1 is SiC. The structure of the first embodiment of the invention is particularly suitable for SiC devices and is used for reducing the electric field intensity at the bottom of a trench gate in the SiC devices, which is a technical problem which needs to be solved urgently for the SiC devices. In other embodiments, it can also be: the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer 3 is silicon.
In the first embodiment of the present invention, the trench gate semiconductor device is an N-type device, i.e., an N-type SiC MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type; in SiC devices, nitrogen (Nitrogen) is typically used as the N-type dopant and Aluminum (Aluminum) is typically used as the P-type dopant. In other embodiments can also be: the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
According to the first embodiment of the invention, the source electrode groove 11 is arranged in the device unit of the groove gate semiconductor device, the bottom of the source electrode groove 11 is self-aligned to form the bottom doping region 6 with the second conductive type heavy doping, the depth of the source electrode groove 11 is similar to or slightly deeper than the depth of the gate electrode groove 10, the depth of the bottom surface of the gate electrode groove 10 can be positioned in the depth range of the bottom doping region 6, thus the bottom region of the groove gate can be shielded by the bottom doping region 6 to form an electric field, and the electric field lines converged at the bottom region of the groove gate, particularly at the bottom corner of the groove gate, during the reverse bias of the device are reduced, so that the electric field intensity of the bottom region of the groove gate can be reduced, and the reliability of the device is improved; the invention is particularly suitable for SiC devices, and improves the reliability of SiC devices such as SiC MOSFET devices.
The source trench 11 of the first embodiment of the present invention is further used for filling metal to form the source lead-out metal 7 that leads out of the channel region 8 and the source region 9, and the bottom doped region 6 can be used as an ohmic contact region between the channel region 8 and the source lead-out metal 7 at the same time, so that no additional process structure is required to be introduced in the first embodiment of the present invention, which is beneficial to the size reduction of the device.
In addition, the channel region 8 of the first embodiment of the present invention can be formed by using the ion implantation with an inclination angle after the formation of the source trench 11 and before the filling, and the bottom doped region 6 can also be formed at the bottom of the source trench 11 by using the vertical ion implantation self-alignment after the formation of the source trench 11, so that the channel region 8 and the bottom doped region 6 of the first embodiment of the present invention do not need to additionally introduce a photolithography mask, and are easy to implement, simple in process and low in cost.
The structures of the source trench 11, the channel region 8 and the bottom doped region 6 of the first embodiment of the present invention can be applied to the transition region and the terminal region, so that the terminal structure does not need an additional photolithography mask, and the process cost can be reduced; moreover, the voltage resistance of the device can be adjusted by adjusting the number of the third trenches 11b in the termination region and corresponding to the source trenches 11, so that the applicability of the present invention is better.
The trench gate semiconductor device of the second embodiment of the present invention:
the trench gate semiconductor device according to the second embodiment of the present invention can be obtained by converting the trench gate semiconductor device according to the first embodiment of the present invention, in which:
the trench gate semiconductor device is an IGBT device, and a collector region 11 heavily doped with a second conductivity type is formed on the back surface of the first semiconductor epitaxial layer 3; the collector region 11 is composed of a thinned semiconductor substrate heavily doped with the second conductivity type, and for an N-type SiC device, the semiconductor substrate is a p+ doped SiC substrate. In some embodiments can also be: the collector region 11 is composed of a back ion implantation region heavily doped with the second conductivity type formed in the thinned semiconductor substrate 1; for an N-type SiC device, aluminum is used as an impurity ion-implanted into the back surface constituting the collector region 11.
A field stop layer 12 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the collector region 11, and the doping concentration of the field stop layer 12 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1. The field stop layer 12 is mainly used to reduce the electric field strength of the drift region to 0.
Fig. 4A is a schematic view of a device structure in which a bottom doped region is formed in the method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention; fig. 4B is a schematic view of a device structure for forming a channel region in the method for manufacturing a trench gate semiconductor device according to an embodiment of the present invention; in the method for manufacturing the trench gate semiconductor device according to the embodiment of the invention, the forming steps of the device unit include:
as shown in fig. 1, a first semiconductor epitaxial layer 3 having a first conductivity type doping is provided, and a trench gate is formed in a selected region of the first semiconductor epitaxial layer 3, the trench gate including a gate trench 10, a gate dielectric layer 4 formed on an inner side surface of the gate trench 10, and a gate conductive material layer 5 filled in the gate trench 10.
As shown in fig. 4A, a hard mask layer 201 is formed on the surface of the first semiconductor epitaxial layer 3, and the hard mask layer 201 is subjected to patterned etching, wherein an opening region of the hard mask layer 201 is a formation region of the source trench 11.
As shown in fig. 4A, the first semiconductor epitaxial layer 3 is etched with the hard mask layer 201 as a mask to form a source trench 11; the first semiconductor epitaxial layer 3 located between the source trench 11 and the trench gate is a mesa region.
As shown in fig. 4A, with the hard mask layer 201 as a blocking layer, ion implantation of heavy doping of the second conductivity type, as shown by reference numeral 202, is performed to form a bottom doped region 6 in a self-aligned manner in a bottom region of the source trench 11, and the implantation energy of the ion implantation of the bottom doped region 6 outside the source trench 11 is ensured not to pass through the hard mask layer 201. As can be seen from fig. 4A, the ion implantation 202 is a vertical implantation.
As shown in fig. 4B, with the hard mask layer 201 as a blocking layer, a second conductivity type angled ion implantation is performed, as shown by reference numeral 203, and the angled ion implantation is performed from the top surface of the mesa region and the side surface of the source trench 11 into the mesa region to form a channel region 8; the depth of the channel region 8 increases gradually from the first side to the second side of the channel region 8; the gate trench 10 extends longitudinally through the channel region 8 and the surface area of the first side of the channel region 8 covered by the trench gate side is used to form a channel. This structural arrangement of the channel region 8 reduces the JFET effect formed by the channel region 8 and the drift region.
The hard mask layer 201 is removed, and the source electrode trench 11 is filled with a source electrode extraction metal 7.
A heavily doped source region 9 of the first conductivity type is formed at the surface of the channel region 8 of the mesa region.
The bottom doped region 6 wraps the bottom of the source extraction metal 7 and forms an ohmic contact, and a side surface of the source extraction metal 7 contacts with the second side surface of the channel region 8 and the second side surface of the source region 9 and serves to extract the channel region 8 and the source region 9.
In the longitudinal direction, the bottom surface of the gate trench 10 is located within the depth range of the bottom doped region 6, and the bottom doped region 6 forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field strength of the bottom region of the trench gate.
The method according to the embodiment of the present invention can manufacture the device according to the first embodiment of the present invention, wherein the trench gate semiconductor device is a MOS transistor, and the first semiconductor epitaxial layer 3 is formed on the surface of the semiconductor substrate 1.
A buffer layer 2 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the semiconductor substrate 1, and the doping concentration of the buffer layer 2 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1.
The following front-side process is also performed:
and forming an interlayer film, a contact hole and a front metal layer, and patterning the front metal layer to form a grid electrode and a source electrode. The gate electrode is contacted with the gate conductive material layer through a contact hole penetrating the interlayer film. The source electrode is connected to the source lead-out metal 7.
After the front side process is completed, the method further comprises the following back side process:
the semiconductor substrate 1 is thinned on the back side.
The semiconductor substrate 1 is heavily doped with a first conductive type, and a drain region is formed by the semiconductor substrate 1 with the back thinned. Other embodiments of the method can also be: back side ion implantation of the first conductivity type heavy doping is performed to form a drain region in the thinned semiconductor substrate 1.
The method of the embodiment of the invention can also manufacture the device structure of the second embodiment of the invention, and at the moment: the trench gate semiconductor device is an IGBT device, and the first semiconductor epitaxial layer 3 is formed on the surface of the semiconductor substrate.
A field stop layer 12 doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer 3 and the top surface of the collector region 11, and the doping concentration of the field stop layer 12 is greater than the doping concentration of the first semiconductor epitaxial layer 3 and less than the doping concentration of the semiconductor substrate 1.
After the front side process is completed, the method further comprises the following back side process:
thinning the back surface of the semiconductor substrate; the semiconductor substrate is heavily doped with the second conductivity type, and the collector region 11 is formed by the semiconductor substrate 1 with the back thinned. Other embodiments of the method can also be: back side ion implantation of heavy doping of the second conductivity type is performed to form a collector region 11 in the thinned semiconductor substrate.
The semiconductor device comprises a plurality of parallel device units, and each device unit is formed in a device unit area.
A transition region surrounds a periphery of the device cell region, and a termination region surrounds a periphery of the transition region.
A second trench 11a is formed in the first semiconductor epitaxial layer 3 of the transition region and a plurality of third trenches 11b are formed in the first semiconductor epitaxial layer 3 of the termination region.
The second trench 11a and each of the third trenches 11b are formed simultaneously with the source trench 11.
A second well region is formed between the source trench 11 and the second trench 11a, between the second trench 11a and the third trench 11b, and between each of the third trenches 11b, the second well region and the channel region 8 having the same process structure and being formed simultaneously.
The second trenches 11a are filled with a first lead-out metal 7a, and each of the second trenches 11a is filled with a second lead-out metal 7b, and the first lead-out metal 7a, the second lead-out metal 7b, and the source lead-out metal 7 have the same process structure and are formed simultaneously.
A second bottom doped region heavily doped with the second conductivity type is formed at the bottom of each of the second trenches 11a and the third trenches 11b, and the process structure of each of the second bottom doped regions is the same as and is formed simultaneously with the process structure of the bottom doped region 6.
The source extraction metal 7 and the top of the first extraction metal 7a are both connected to a source formed of a front side metal layer, and the second extraction metal 7b floats.
The width of the second trench 11a is 10 times or more the width of the source trench 11; the width of the third trench 11b is equal to or greater than the width of the source trench 11.
The spacing between the second trenches 11a or the third trenches 11b is equal to or greater than the spacing between the source trenches 11.
The pitches between the second trenches 11a or the third trenches 11b are equal or the pitches between the second trenches 11a or the third trenches 11b gradually increase in the direction from the device unit region to the termination region.
The number of the third trenches 11b is set according to an operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third trenches 11b is.
In the device of the first embodiment of the present invention formed by the method of the embodiment of the present invention, the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer 3 is SiC; the material of the buffer layer 2 and the semiconductor substrate 1 is SiC. The device of the first embodiment of the invention formed by the method of the embodiment of the invention is particularly suitable for SiC devices, is used for reducing the electric field intensity at the bottom of the trench gate in the SiC devices, and is a technical problem which needs to be solved urgently for the SiC devices. In other embodiments, it can also be: the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer 3 is silicon.
In the first embodiment device formed by the method of the embodiment of the invention, the trench gate semiconductor device is an N-type device, namely an N-type SiC MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type; in SiC devices, nitrogen (Nitrogen) is typically used as the N-type dopant and Aluminum (Aluminum) is typically used as the P-type dopant. In other embodiments can also be: the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The device according to the first embodiment of the present invention will be further described with reference to specific parameters, and the following description will take an N-type SiC MOSFET as an example:
the semiconductor substrate 1 is a SiC substrate: the substrate, i.e. the semiconductor substrate 1, is intended to serve as a support. It is desirable that the thinner the substrate, the better the doping concentration of the substrate, i.e. the lower the resistivity, the better the doping of the substrate, typically Nitrogen (Nitrogen). This can reduce the thermal resistance of the device and reduce the substrate resistance. But the thickness of the substrate is limited by the process capability and the doping concentration of the substrate is limited by the nature of the material. At present, the thickness of a substrate of a typical SiC MOSFET is about 150 mu m, and the resistivity of the substrate is about 0.020 omega cm.
The buffer layer 2 is provided with: the thickness is usually 1 μm, and the doping concentration is usually 1e18cm -3 Nearby, doping is typically performed by Nitrogen. The buffer layer 2 serves to reduce the impact of substrate defects on device performance.
The first semiconductor epitaxial layer 3 is provided as: the doping concentration and thickness of the epitaxial layer, i.e. the first semiconductor epitaxial layer 3, determine the breakdown voltage of the device, typically for a 650V SiC MOSFET, the thickness of the epitaxial layer is typically around 6 μm, the corresponding doping concentration being 2e16cm -3 A vicinity; for a 1200V SiC MOSFET, the thickness of its epitaxial layer is typically around 11 μm, with a corresponding doping concentration of 1e16cm -3 A vicinity; for a 170V SiC MOSFET, the thickness of the epitaxial layer is usually about 16 μm, and the corresponding doping concentration is 7e17cm -3 Nearby.
The gate dielectric layer 4 is set as follows: an oxide layer is adopted; the mobility of the oxide layer has a very large influence on the device performance; there are many methods to improve the mobility of oxide layers; the most dominant way is annealing in an N2 ambient. The material currently commonly selected for the oxide layer is SiO2, which is typically of a thicknessNearby.
The gate conductive material layer 5 is provided as: the material adopts polysilicon gate, and can also adopt metal; the gate conductive material layer 5 is formed by gate trench etching plus a conductive material such as metal or polysilicon filling.
The bottom doped region 6 is arranged to: is heavily doped P-type and is connected to the channel region 8. The bottom doped region 6 has two functions:
the doping concentration of the first and the bottom doped regions 6 can form good ohmic contact with the source lead-out metal 7.
Second, the bottom doped region 6 can act as a shield (Shielding) to reduce the electric field strength at the surface of the trench gate bottom region. The bottom doped region 6 is typically implanted with Al ions (implant).
The channel region 8 is arranged to: is a P-type channel region, the doping concentration of the channel region 8 determines the threshold voltage of the device.
The source region 9 is arranged to: is a heavily doped N-type source region which is connected by sidewalls to the source lead-out metal 7 and thus to the source consisting of a front side metal layer.
As can be seen from the above, two trenches, the gate trench 10 and the source trench 11, respectively, are included in one of the device cells. The dimensions of the two grooves are set as follows:
1. the width of the gate trench 10 is 0.7 μm, the width of the gate trench 10 corresponds to a in fig. 1, and only half of the gate trench 10 is drawn in the device unit, i.e., cell, in fig. 1; the depth of the gate trench 10 is 1.0 μm.
2. A Mesa (Mesa) region, the width of the Mesa region, i.e., mesa region, is 0.5 μm; this is chosen to be small because no extra metal contact holes need to be made at the Mesa, the source extraction metal 7 being connected to the heavily doped source region 9 by sidewalls.
3. The source trench 11 has a width of 0.8 μm and a corresponding depth of 1.2 μm. The depth of the source electrode groove 11 is slightly deeper than that of the grid electrode groove 10, so that the electric field intensity at the bottom of the grid electrode can be better shielded, and the reliability of the device is improved. In some embodiments, the corresponding step (Pitch) is 0.7 μm+0.5 μm+2+0.8 μm, for a total of 2.5 μm.
The first embodiment of the present invention has the following features:
1. the bottom doped region 6 and the channel region 8 do not require the use of an additional reticle.
2. The termination structure of the device is also formed simultaneously by the formation process of the bottom doped region 6 and the channel region 8.
As shown in fig. 4A, after Source trench 11 is etched, the hard mask layer 201 (hard mask) is still on, which may be used as a barrier for subsequent ion implantation (implant). Because of the Hard mask, no additional photolithographic layers are required to form the bottom doped region 6 and the channel region 8.
The bottom doped region 6 is implanted with high dose Al μm to form a heavily doped P-type region. It adopts vertical injection, without angle or with very small angle, preventing channeling effect (Channeling Effect); typical values of the injected dose are 1e15cm -2 In the vicinity, typical values of the implantation energy are 50 to 100keV.
As shown in fig. 4B, the channel region 8 is implanted with an oblique angle, and the maximum implantation angle is 15 degrees to 60 degrees, and typically 30 degrees, or even 45 degrees. The channel region 8 is used to form a channel, the typical value of the implant dose is 1e12cm -2 ～1e13cm -2 Near, typical values of implant energy are around 100-600 keV.
In the first embodiment of the present invention, the bottom doped region 6 and the channel region 8 are formed at one time, and no additional photolithography mask is required, thereby reducing the cost. And more importantly, because the channel region 8 is implanted at an oblique angle, the doping concentration profile of the channel region 8 is deep near Source Trench and shallow near gate Trench 10, which reduces JFET effects in the channel region 8 and drift region. This is different from the conventional structure, which introduces a very serious JFET effect in order to reduce the electric field strength at the bottom of the trench gate. This also allows better Shielding because the channel region 8 will also be implanted into the bottom of the Source Trench.
In the terminal structure of the first embodiment of the present invention, no additional photolithography mask is required.
The terminal of the first embodiment of the present invention is a terminal structure employing a Floating Ring (Floating Ring). A typical terminal structure is shown with reference to fig. 2.
The terminal structure of the first embodiment of the present invention has the following characteristics:
1. and the Source-Trench is used as a terminal structure, so that an additional photoetching plate is not required to be added.
2. In the transition region, there is a relatively large Source-Trench, i.e., the second Trench 11a, and the width of the second Trench 11a is at least 10 times that of the cell region, i.e., the device cell region.
3. The metal in the Source-Trench of the termination region, i.e. the second extraction metal, is floating, i.e. floating, only the first extraction metal in the first of said second trenches 11a in the transition region is connected to the Source metal, the remainder being floating.
4. The termination region is composed of a plurality of floating second lead-out metals filled in the Source-Trench, and the number of the floating second lead-out metals is greatly related to the required breakdown voltage. Typically for 650V devices, 15 floating second extraction metals are required; for 1200V devices 30 floating second extraction metals are required.
5. The Source-Trench spacing in the transition region and the termination region is greater than that in the primordial region. Each Source-tree may be equally spaced, e.g., the distance between Source-tree and Source-tree is 3 μm; more preferably, the distance between Source-trends is gradually increased, and one approach is linear increase.
6. The width of the Source-tree in the transition region and the terminal region may be the same as the width of the Source-tree in the cell region. But more preferably is greater than the Source-Trench width of the primordial region; one example is a Source-Trench width of the terminal of 1 μm.
According to the first embodiment of the invention, a double-groove design and a double-P-type channel oblique angle injection technology are adopted, so that the electric field intensity at the bottom of the groove of the SiC MOSFET is reduced, the JFET effect of the groove and a drift region is reduced, and the reliability of the device is improved; the P-type channel does not need an extra photoetching plate, so that the production cost is reduced; in addition, the technology adopted by the first embodiment of the invention is also suitable for improving the reliability of Silicon (Silicon) devices and SiC IGBT products.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. A trench-gate semiconductor device, wherein the device cell comprises:
a first semiconductor epitaxial layer with first conductivity type doping, wherein a trench gate is formed in a selected area of the first semiconductor epitaxial layer, and comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench;
a source trench formed in a selected region of the first semiconductor epitaxial layer, the first semiconductor epitaxial layer between the source trench and the trench gate being a mesa region;
A channel region doped with a second conductivity type is formed in the platform region, and a source region heavily doped with the first conductivity type is formed in a surface region of the channel region;
the gate trench passing longitudinally through the channel region, a surface area of a first side of the channel region being covered by the trench gate side for forming a channel;
a source electrode leading-out metal is filled in the source electrode groove;
a bottom doping region which is heavily doped with a second conductivity type is formed in the bottom region of the source electrode groove in a self-aligning mode, the bottom doping region wraps the bottom of the source electrode lead-out metal, ohmic contact is formed, and the side face of the source electrode lead-out metal is contacted with the second side face of the channel region and the second side face of the source region and used for leading out the channel region and the source region;
in the longitudinal direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field intensity of the bottom region of the trench gate.
2. The trench-gate semiconductor device of claim 1, wherein: the depth of the channel region increases gradually from the first side to the second side of the channel region.
3. The trench-gate semiconductor device of claim 2, wherein: the channel region is an inclined ion implantation region, the channel region is formed by adopting inclined ion implantation after the source electrode groove is opened, and the inclined ion implantation is implanted into the platform region from the top surface of the platform region and the side surface of the source electrode groove to form the channel region.
4. The trench-gate semiconductor device of claim 1, wherein: the trench gate semiconductor device is a MOS transistor, and a drain region heavily doped with a first conductivity type is formed on the back surface of the first semiconductor epitaxial layer; the drain region consists of a thinned semiconductor substrate heavily doped with the first conductivity type or the drain region consists of a back ion implantation region heavily doped with the first conductivity type formed in the thinned semiconductor substrate;
or the trench gate semiconductor device is an IGBT device, and a collector region heavily doped with the second conductivity type is formed on the back surface of the first semiconductor epitaxial layer; the collector region is composed of a thinned second-conductivity-type-heavily-doped semiconductor substrate or the collector region is composed of a second-conductivity-type-heavily-doped back-side ion implantation region formed in the thinned semiconductor substrate.
5. The trench-gate semiconductor device of claim 4, wherein: when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with a first conductivity type is formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate;
when the trench gate semiconductor device is an IGBT, a field stop layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
6. The trench-gate semiconductor device of claim 3, wherein: the semiconductor device comprises a plurality of device units connected in parallel, and each device unit is formed in a device unit area;
the transition region surrounds the peripheral side of the device unit region, and the terminal region surrounds the peripheral side of the transition region;
forming a second trench in the first semiconductor epitaxial layer of the transition region and forming a plurality of third trenches in the first semiconductor epitaxial layer of the termination region;
The second trench and each third trench are formed simultaneously with the source trench;
forming a second well region between the source trench and the second trench, between the second trench and the third trench, and between the third trenches, the second well region and the channel region having the same process structure and being formed simultaneously;
a first lead-out metal is filled in the second grooves, a second lead-out metal is filled in each second groove, and the first lead-out metal, the second lead-out metal and the source lead-out metal have the same process structure and are formed simultaneously;
forming a second bottom doping region heavily doped with a second conductivity type at the bottoms of the second trenches and the third trenches, wherein the process structure of each second bottom doping region is the same as that of the bottom doping region and is formed simultaneously;
the tops of the source electrode leading-out metal and the first leading-out metal are connected with a source electrode formed by a front metal layer, and the second leading-out metal floats.
7. The trench-gate semiconductor device of claim 6, wherein: the width of the second groove is more than 10 times of the width of the source groove; the width of the third groove is larger than or equal to the width of the source groove;
The spacing between the second grooves or the third grooves is larger than or equal to the spacing between the source grooves;
the pitches between the second trenches or the third trenches are equal or the pitches between the second trenches or the third trenches gradually increase in the direction from the device cell region to the termination region;
the number of the third grooves is set according to the operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third grooves is.
8. The trench-gate semiconductor device of any of claims 1-7, wherein: the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.
9. A method of fabricating a trench gate semiconductor device, the device cell forming step comprising:
providing a first semiconductor epitaxial layer with first conductivity type doping, and forming a trench gate in a selected area of the first semiconductor epitaxial layer, wherein the trench gate comprises a gate trench, a gate dielectric layer formed on the inner side surface of the gate trench and a gate conductive material layer filled in the gate trench;
Forming a hard mask layer on the surface of the first semiconductor epitaxial layer, and carrying out graphical etching on the hard mask layer, wherein an opening area of the hard mask layer is a source electrode groove forming area;
etching the first semiconductor epitaxial layer by taking the hard mask layer as a mask to form a source electrode groove; the first semiconductor epitaxial layer is positioned between the source electrode groove and the groove gate and is a platform area;
taking the hard mask layer as a blocking layer, performing ion implantation of heavy doping of a second conductivity type in the bottom area of the source electrode groove to form a bottom doping area in a self-aligned mode, and ensuring that implantation energy of the ion implantation of the bottom doping area does not pass through the hard mask layer outside the source electrode groove;
performing second-conductivity-type inclined ion implantation by taking the hard mask layer as a blocking layer, wherein the inclined ion implantation is performed from the top surface of the platform region and the side surface of the source electrode groove to the platform region to form a channel region; the depth of the channel region gradually increases from the first side surface to the second side surface of the channel region; the gate trench passing longitudinally through the channel region, a surface area of a first side of the channel region being covered by the trench gate side for forming a channel;
Removing the hard mask layer, and filling source extraction metal in the source electrode groove;
forming a first conductive type heavily doped source region on the surface of the channel region of the mesa region;
the bottom doping region wraps the bottom of the source extraction metal and forms ohmic contact, and the side surface of the source extraction metal is contacted with the second side surface of the channel region and the second side surface of the source region and is used for extracting the channel region and the source region;
in the longitudinal direction, the bottom surface of the gate trench is located within the depth range of the bottom doped region, and the bottom doped region forms an electric field shielding structure for the bottom region of the trench gate, so as to reduce the electric field intensity of the bottom region of the trench gate.
10. The method of manufacturing a trench gate semiconductor device as claimed in claim 9, wherein: the trench gate semiconductor device is a MOS transistor, the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front surface process is completed, the trench gate semiconductor device further comprises the following back surface process:
thinning the back surface of the semiconductor substrate;
the semiconductor substrate is heavily doped with a first conductive type, and a drain region is formed by the semiconductor substrate with the back thinned; or, performing back ion implantation of the first conductive type heavy doping to form a drain region in the thinned semiconductor substrate;
Or, the trench gate semiconductor device is an IGBT device, and the first semiconductor epitaxial layer is formed on the surface of the semiconductor substrate, and after the front side process is completed, the method further includes the following back side process:
thinning the back surface of the semiconductor substrate; the semiconductor substrate is heavily doped with a second conductive type, and a collector region is formed by the semiconductor substrate with the back thinned; alternatively, back side ion implantation of heavy doping of the second conductivity type is performed to form a collector region in the thinned semiconductor substrate.
11. The method of manufacturing a trench gate semiconductor device as claimed in claim 10, wherein: when the trench gate semiconductor device is a MOS transistor, a buffer layer doped with a first conductivity type is formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the semiconductor substrate, and the doping concentration of the buffer layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate;
when the trench gate semiconductor device is an IGBT, a field stop layer doped with the first conductivity type is further formed between the bottom surface of the first semiconductor epitaxial layer and the top surface of the collector region, and the doping concentration of the field stop layer is greater than that of the first semiconductor epitaxial layer and less than that of the semiconductor substrate.
12. The method of manufacturing a trench gate semiconductor device as claimed in claim 9, wherein: the semiconductor device comprises a plurality of device units connected in parallel, and each device unit is formed in a device unit area;
the transition region surrounds the peripheral side of the device unit region, and the terminal region surrounds the peripheral side of the transition region;
forming a second trench in the first semiconductor epitaxial layer of the transition region and forming a plurality of third trenches in the first semiconductor epitaxial layer of the termination region;
the second trench and each third trench are formed simultaneously with the source trench;
forming a second well region between the source trench and the second trench, between the second trench and the third trench, and between the third trenches, the second well region and the channel region having the same process structure and being formed simultaneously;
a first lead-out metal is filled in the second grooves, a second lead-out metal is filled in each second groove, and the first lead-out metal, the second lead-out metal and the source lead-out metal have the same process structure and are formed simultaneously;
forming a second bottom doping region heavily doped with a second conductivity type at the bottoms of the second trenches and the third trenches, wherein the process structure of each second bottom doping region is the same as that of the bottom doping region and is formed simultaneously;
The tops of the source electrode leading-out metal and the first leading-out metal are connected with a source electrode formed by a front metal layer, and the second leading-out metal floats.
13. The method of manufacturing a trench gate semiconductor device as claimed in claim 12, wherein: the width of the second groove is more than 10 times of the width of the source groove; the width of the third groove is larger than or equal to the width of the source groove;
the spacing between the second grooves or the third grooves is larger than or equal to the spacing between the source grooves;
the pitches between the second trenches or the third trenches are equal or the pitches between the second trenches or the third trenches gradually increase in the direction from the device cell region to the termination region;
the number of the third grooves is set according to the operating voltage of the semiconductor device, and the larger the operating voltage of the semiconductor device is, the larger the number of the third grooves is.
14. A method for manufacturing a trench gate semiconductor device as claimed in any one of claims 9 to 3, characterized in that: the trench gate semiconductor device is a SiC device, and the material of the first semiconductor epitaxial layer is SiC; or the trench gate semiconductor device is a silicon-based device, and the material of the first semiconductor epitaxial layer is silicon.
15. The method of manufacturing a trench gate semiconductor device of claim 14, wherein: the trench gate semiconductor device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the trench gate semiconductor device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
CN202311425834.2A 2023-10-31 2023-10-31 Trench gate semiconductor device and method of manufacturing the same Pending CN117542890A (en)

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