CN116259644A - Planar SiC MOSFET device - Google Patents

Planar SiC MOSFET device Download PDF

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CN116259644A
CN116259644A CN202111498285.2A CN202111498285A CN116259644A CN 116259644 A CN116259644 A CN 116259644A CN 202111498285 A CN202111498285 A CN 202111498285A CN 116259644 A CN116259644 A CN 116259644A
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曾大杰
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Shanghai Dingyangtong Semiconductor Technology Co ltd
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Abstract

The invention discloses a planar SiC MOSFET device, which comprises: forming an anti-JFET region on the surface of the drift region between two adjacent channel regions; two or more first ion implantation regions of the channel region are set as: the deeper the injection peak position, the larger the injection peak; the shallower the injection peak position, the smaller the injection peak; the implantation peak position and implantation dose of one or more second ion implantation regions of the anti-JFET region are set as: the implant peak size and location of the second ion implant region is located between the sizes and locations of the shallowest and deepest implant peaks in the channel region. The invention can simultaneously meet the requirements of threshold voltage and reducing the short channel effect of the device and the anti-JFET region not only can meet the requirements of reducing the specific on-resistance of the device, but also can prevent the electric field intensity on the surface of the anti-JFET from being increased so as to increase the reliability of the device.

Description

Planar SiC MOSFET device
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a planar SiC MOSFET device.
Background
SiC has very superior material properties compared to Si, which is mainly represented by a forbidden band width of 3.2 electron volts (eV), which is nearly 3 times higher than 1.12 of silicon. The critical breakdown field strength is 10 times that of silicon. If the same withstand voltage is to be realized, the drift region length of SiC can be 1/10 of that of silicon, and the doping concentration can be increased by tens of times. At the same time, the high forbidden bandwidth and the low intrinsic carrier concentration enable the number of the intrinsic carriers of the SiC device to be lower than that of the Si device at normal temperature (25 degrees) even at the junction temperature of 250 degrees and 300 degrees. The high-temperature electric leakage of the SiC device is greatly reduced. The main limitation of its operating temperature is encapsulation rather than the device itself.
Based on the SiC MOSFET, the SiC MOSFET is widely applied and has a huge market prospect.
As shown in fig. 1, a schematic cross-sectional structure of a conventional planar SiC MOSFET device is shown; taking an N-type SiC MOSFET as an example for description, the conventional planar SiC MOSFET device includes:
the resistivity of the N-type heavily doped SiC substrate 101 is typically around 20mΩ×cm. The substrate resistivity of the Si device, on the other hand, can be less than 1mΩ×cm. This is because too high a substrate doping concentration can increase device defects. The substrate resistance of SiC substrate 101 is much higher than that of Si devices. In order to reduce the substrate resistance, it is generally desirable to make the thickness of SiC substrate 101 thinner as well. In addition, the thinner the substrate thickness, the lower the thermal resistance of the device;
an N-type doped Buffer layer 102 formed of SiC material is formed on a SiC substrate 101, the Buffer layer 102 has a high doping concentration of 1e18/cm 3 A vicinity; the Buffer layer 102 is formed by epitaxial growth, so that the defect density of the Buffer layer 102 is superior to that of the substrate. The Buffer layer 102 is typically around 1 μm thick.
An N-type doped SiC epitaxial layer 103 is formed on the surface of the Buffer layer 102, and the doping concentration of the SiC epitaxial layer 103 determines the breakdown voltage of the device. The higher the breakdown voltage of the device, the thicker the thickness of SiC epitaxial layer 103, and the lower the doping concentration of SiC epitaxial layer 103. For current 1200V SiC MOSFETs, the thickness of the SiC epitaxial layer 103 is typically between 8 μm and 13 μm, and the doping concentration of the SiC epitaxial layer 103 is typically 5e15/cm 3 ～2e16/cm 3 Between them. The SiC epitaxial layer 103 is currently typically single-layer or double-layer epitaxy. For double-layer epitaxy, the doping concentration near the surface is high, and the JFET effect of the MOSFET is reduced.
A P-type doped channel region 104 is formed in the SiC epitaxial layer 103, and the design of the channel region 104 is a difficulty of the SiC MOSFET. This is because the channel region 104 of a SiC MOSFET has very low carrier mobility, typically less than 1/10 of that of a silicon device; it is desirable to make the channel length Lc shorter the better. But the doping concentration of the channel region 104, in particular the doping concentration of the surface, must not be too high in order to guarantee a certain threshold voltage.
In addition, the doping concentration of the drift region of the SiC MOSFET is also greatly increased, and the drift region is composed of the SiC epitaxial layer 103 outside the channel region 104, which requires an increase in both the doping concentration of the channel region 104 and the channel length Lc, which would otherwise have very serious short channel effects.
The region between adjacent channel regions 104 typically has JFET effect, and the distance Wj between adjacent channel regions 104 is also a difficulty. There will be a depletion between the channel region 104 and the N-type drift region, i.e., JFET effect, which reduces the conduction region. If the distance Wj is too small, the JFET effect is too severe and the specific on-resistance of the device increases dramatically. If the distance Wj is too large, the step (Pitch) of the device increases, the density of the cells decreases, and the specific on-resistance of the device increases. To maintain a relatively low specific on-resistance at small inter-channel distances, an Anti-JFET Implant (Anti-JFET Implant) is typically added to form an Anti-JFET Implant region between adjacent channel regions 104. But this JFET implant region increases the electric field strength of the gate oxide 107. For SiC MOSFETs, because the critical breakdown field strength of SiC is as high as 3MV/cm or more; the material of the gate oxide 107 is typically SiO 2 Furthermore, because of the SiC material and SiO at the interface of the SiC epitaxial layer 103 and the gate oxide 107 2 The difference in dielectric constant causes SiO of gate oxide 107 2 The electric field strength in the material can be improved by more than 2 times. This can easily be achieved or exceeded by SiO 2 Is a critical breakdown voltage of (a). Causing damage to the device or degradation of long-term operation. For this reason, how to design the channel regions 104 and the doping concentration of the anti-JFET regions between adjacent channel regions 104 is a difficult problem, which is also a problem to be solved by the present invention. In a word, the invention mainly solves the problem of how to design reasonable doping concentration of the channel region 104 and reduce the short channel effect of the device; how to design the doping of the anti-JFET regionThe concentration is such that the breakdown field strength of the surface can still be lower when the on-resistance of the device is lower.
An N-type heavily doped source region 106 and a P-type heavily doped body contact region 105 are formed in a surface region of a selected region of the channel region 104. The high doping concentration of the body contact region 105 can reduce the base resistance of the parasitic triode of the device and prevent Snapback (Snapback) of the device.
The source metal 110 composed of the front metal layer is connected to the source region 106 through a source region via and a bottom body contact region 105, the source region via and the bottom body contact region 105 and the source region 106 realize ohmic contact, and the channel region 104 is connected to the source region via and the source metal 110 through the body contact region 105.
The gate oxide 107 is typically SiO 2 . The drive power of SiC MOSFETs typically needs to exceed 18V, even up to 20V. The gate oxide thickness required for such high drive voltages is typically relatively thick. At present, the thickness of the grid oxide of the SiC planar MOSFET is usually
Figure BDA0003401743470000031
I.e. 50nm.
A gate conductive material layer 108 is formed on the surface of the gate oxide 107, and a gate structure is formed by superposition of the gate oxide 107 and the gate conductive material layer 108. The surface of the channel region 104 covered by the gate structure forms a conductive channel when the device is on. The layer of gate conductive material 108 typically employs an N-type heavily doped polysilicon gate.
The interlayer film 109 realizes isolation between the source metal 10 and the gate conductive material layer 108. The interlayer film 109 is also typically SiO 2 The thickness is typically between 0.4 μm and 2.0 μm.
Disclosure of Invention
The invention aims to solve the technical problem of providing a planar SiC MOSFET device, wherein the doping of a channel region can meet the requirement of threshold voltage and the requirement of reducing the short channel effect of the device, and meanwhile, an anti-JFET region can meet the requirement of reducing the specific on-resistance of the device and can prevent the electric field intensity on the surface of the anti-JFET from being increased so as to increase the reliability of the device.
In order to solve the above technical problems, the planar SiC MOSFET device provided by the present invention includes:
a channel region formed in a selected region of the first conductivity type doped SiC epitaxial layer, a surface of the channel region covered by the gate structure for forming a conductive channel; the SiC epitaxial layer outside the channel region forms a drift region.
An anti-JFET region is formed on the drift region surface between two adjacent channel regions.
The gate structure also extends onto the surface of the anti-JFET region.
The gate structure is formed by laminating a gate dielectric layer and a gate conductive material layer.
The channel region is formed by overlapping more than two second-conductivity-type-doped first ion implantation regions with different implantation peak positions.
The anti-JFET region is formed by overlapping more than one second ion implantation regions doped with the first conductivity type and different in implantation peak positions.
Each of the first ion implantation regions in the channel region is configured to:
the deeper the injection peak position, the larger the injection peak; the shallower the injection peak position, the smaller the injection peak.
The threshold voltage of the planar SiC MOSFET device is regulated by the first ion implantation regions with the shallowest implantation peak positions, and short channel effect is reduced by the first ion implantation regions with the implantation peak positions below the shallowest implantation peak positions.
The implantation peak position and implantation dose of each of the second ion implantation regions of the anti-JFET region are set as follows:
and the injection peak position of each second ion injection region is deeper than the shallowest injection peak position in the channel region so as to reduce the electric field intensity at the interface of the gate dielectric layer and the SiC epitaxial layer.
The injection peak position of each second ion injection region is shallower than the deepest injection peak position in the channel region, so that the breakdown voltage of the device is ensured.
The injection peak value of each second ion injection region is larger than the injection peak value of the first ion injection region with the shallowest injection peak position in the channel region, and the injection peak value of each second ion injection region is smaller than the injection peak value of the first ion injection region with the deepest injection peak position in the channel region, so that the JFET effect is reduced, and the specific on-resistance of the device is reduced.
In a further improvement, the channel region is formed by superposing two second-conductivity-type-doped first ion implantation regions with different implantation peak positions.
A further improvement is that the anti-JFET region consists of a second ion-implanted region doped with the first conductivity type.
The anti-JFET region is formed by superposing two second ion implantation regions doped with the first conductivity type and different in implantation peak positions, and the implantation peak sizes of the two second ion implantation regions are the same or different.
The channel region is formed by superposing three first ion implantation regions doped with the second conductivity type and different in implantation peak positions.
A further improvement is that the anti-JFET region consists of a second ion-implanted region doped with the first conductivity type.
A further improvement is that the implantation peak position of the second ion implantation region of the anti-JFET region is located between the shallowest implantation peak position and the sub-shallowest implantation peak position of the channel region; alternatively, the implantation peak position of the second ion implantation region of the anti-JFET region is located between the sub-shallow implantation peak position and the deepest implantation peak position of the channel region.
A further improvement is that a heavily doped source region of the first conductivity type is also formed in a surface region of a selected region of the channel region, the gate structure also extending onto the source region surface.
A further improvement is that a heavily doped body contact region of the second conductivity type is also formed in a surface region of a selected region of the channel region.
A further improvement is that the surfaces of the body contact region and the source region are connected to a source electrode composed of a front side metal layer through a source contact hole penetrating the interlayer film.
A further improvement is that the planar SiC MOSFET device comprises a plurality of device cells;
and 2 adjacent device units form a primitive cell, wherein in the primitive cell, the two device units share the anti-JFET region, channel regions of the two device units are symmetrically arranged at two sides of the anti-JFET region, and gate structures of the two device units are connected above the surface of the anti-JFET region to form an integral structure.
A further improvement is that the planar SiC MOSFET device comprises a plurality of device cells;
and 2 adjacent device units form a primitive cell, wherein in the primitive cell, the two device units share the anti-JFET region, channel regions of the two device units are symmetrically arranged at two sides of the anti-JFET region, and the grid structures of the two device units are spaced above the surface of the anti-JFET region so as to reduce input capacitance.
The planar SiC MOSFET device comprises a plurality of device units, wherein 1 device unit forms a primitive cell;
providing only one of the gate structures on top of each of the channel regions and forming one of the conductive channels;
a second side of the gate structure of each of the device cells extends from the second side of the channel region onto an adjacent surface of the anti-JFET region and is spaced from an adjacent first side of the channel region;
the source region and the body contact region are formed between a first side of the gate structure and a first side of the channel region of each of the device cells.
A further improvement is that the SiC epitaxial layer is formed on a SiC substrate with a first conductivity type doped buffer layer between the SiC epitaxial layer and the SiC substrate.
The planar SiC MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the planar SiC MOSFET device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
A further improvement is that the P-type dopant impurity comprises aluminum and the N-type dopant impurity comprises nitrogen.
In the invention, the channel region and the anti-JFET region are both composed of ion implantation regions, and the ion implantation regions of the channel region and the anti-JFET region are specially arranged, mainly comprising the following steps:
the invention sets the size and position of the injection peak of each first ion injection region according to the requirement of meeting the threshold voltage of the device and the requirement of reducing the short channel effect, and finally, the doping of the channel region can meet the requirement of meeting the threshold voltage and the requirement of reducing the short channel effect of the device.
The size and the position of the injection peak value of the second ion injection region of the anti-JFET region are set according to the size and the position of the injection peak value of each first ion injection region of the channel region, and under the condition that the injection peak value position of the second ion injection region of the anti-JFET region is ensured to be positioned at the bottom of the injection peak value position of the shallowest first ion injection region of the channel region, the electric field intensity of the surface region of the anti-JFET region can be reduced, namely the electric field intensity at the interface between the gate dielectric layer and the SiC epitaxial layer can be reduced, so that the reliability of the device can be improved; under the condition that the injection peak position of the second ion injection region of the anti-JFET region is ensured to be positioned above the injection peak position of the deepest first ion injection region of the channel region, the breakdown voltage of the device can be ensured; the size of the injection peak of the second ion injection region of the anti-JFET region and the combination of the position setting of the injection peak can meet the requirement of the anti-JFET effect, so that the specific on-resistance of the device is reduced.
In addition, in the field of semiconductor manufacturing, an implantation peak corresponding to an ion implantation process refers to a maximum value of a doping concentration in an implantation region after ion implantation, and a magnitude of the implantation peak, that is, the maximum value of the doping concentration in the implantation region itself, and an implantation dose of the ion implantation correspond to each other; the position of the implantation peak, i.e., the depth position corresponding to the maximum value of the doping concentration in the implantation region, is also simply referred to as the implantation peak position, and corresponds to the implantation energy of the ion implantation.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic cross-sectional structure of a conventional planar SiC MOSFET device;
fig. 2 is a schematic cross-sectional structure of a planar SiC MOSFET device according to a first embodiment of the present invention;
fig. 3A is a first doping concentration profile of the channel region and the anti-JFET region of a planar SiC MOSFET device according to a first embodiment of the invention;
fig. 3B is a doping concentration profile when the implantation peak position of the anti-JFET region is shallower than the desired value on the basis of fig. 3A;
fig. 3C is a doping concentration profile of the anti-JFET region of fig. 3A with the implanted peak position deeper than desired;
fig. 4 is a second doping concentration profile of the channel region and anti-JFET region of a planar SiC MOSFET device according to the first embodiment of the invention;
fig. 5 is a third doping concentration profile of the channel region and anti-JFET region of a planar SiC MOSFET device according to the first embodiment of the invention;
fig. 6 is a fourth doping concentration profile of the channel region and the anti-JFET region of a planar SiC MOSFET device according to the first embodiment of the invention;
fig. 7 is a schematic cross-sectional structure of a planar SiC MOSFET device according to a second embodiment of the present invention;
fig. 8 is a schematic cross-sectional structure of a planar SiC MOSFET device according to a third embodiment of the present invention.
Detailed Description
First embodiment planar SiC MOSFET device of the present invention:
as shown in fig. 2, a schematic cross-sectional structure of a planar SiC MOSFET device according to a first embodiment of the present invention; the planar SiC MOSFET device of the first embodiment of the invention comprises:
a channel region 4 formed in a selected region of the first conductivity type doped SiC epitaxial layer 3, a surface of the channel region 4 covered by the gate structure being used to form a conductive channel; the SiC epitaxial layer 3 outside the channel region 4 constitutes a drift region.
In a first embodiment of the invention, the SiC epitaxial layer 3 is formed on the SiC substrate 1 with a buffer layer 2 doped with a first conductivity type between the SiC epitaxial layer 3 and the SiC substrate 1.
An anti-JFET region 3a is formed on the drift region surface between two adjacent channel regions 4. The anti-JFET region 3a is achieved by adding a first conductivity type doping to the SiC epitaxial layer 3 between adjacent channel regions 4, which is represented by the dashed box 3a alone in fig. 2.
The gate structure also extends onto the surface of the anti-JFET region 3a.
The gate structure is formed by overlapping a gate dielectric layer 7 and a gate conductive material layer 8. The gate dielectric layer 7 is typically formed by using gate oxide, such as silicon dioxide, and the gate conductive material layer 8 is typically formed by using a polysilicon gate.
The channel region 4 is formed by overlapping more than two second-conductivity-type-doped first ion implantation regions with different implantation peak positions.
The anti-JFET region 3a is formed by superposing more than one second ion implantation regions doped with the first conductivity type and different in implantation peak positions.
Each of the first ion implantation regions in the channel region 4 is configured to:
the deeper the injection peak position, the larger the injection peak; the shallower the injection peak position, the smaller the injection peak.
The threshold voltage of the planar SiC MOSFET device is regulated by the first ion implantation regions with the shallowest implantation peak positions, and short channel effect is reduced by the first ion implantation regions with the implantation peak positions below the shallowest implantation peak positions.
The implantation peak position and implantation dose of each of the second ion implantation regions of the anti-JFET region 3a are set as follows:
the injection peak position of each second ion injection region is deeper than the shallowest injection peak position in the channel region 4, so as to reduce the electric field intensity at the interface of the gate dielectric layer 7 and the SiC epitaxial layer 3.
The injection peak position of each second ion injection region is shallower than the deepest injection peak position in the channel region 4, so that the breakdown voltage of the device is ensured.
The injection peak value of each second ion injection region is larger than the injection peak value of the first ion injection region with the shallowest injection peak position in the channel region 4, and the injection peak value of each second ion injection region is smaller than the injection peak value of the first ion injection region with the deepest injection peak position in the channel region 4, so that the JFET effect is reduced, and the specific on-resistance of the device is reduced.
In some embodiments, the channel region 4 is formed by overlapping two doped first ion implantation regions of the second conductivity type with different implantation peak positions. The anti-JFET region 3a consists of a second ion implantation region doped with the first conductivity type. In this case, referring to fig. 3A, fig. 3A is a first doping concentration profile of a channel region and an anti-JFET region 3A of a planar SiC MOSFET device according to a first embodiment of the present invention; in fig. 3A, curve 201 shows the doping concentration profile of fig. 2 at solid line AA, which extends longitudinally from the top surface of channel region 4 down into SiC epitaxial layer 3 at the bottom of channel region 4, so that curve 201 includes the doping profile of channel region 4; curve 202 is the doping concentration profile at dashed line BB in fig. 2, the longitudinal extent of dashed line BB extending all the way down from the top surface of SiC epitaxial layer 3 between channel regions 4, so that the doping concentration profile of anti-JFET region 3a is included in curve 202. The lateral coordinate in fig. 3A is the depth from the top surface of the SiC epitaxial layer 3, the top surface of the channel region 4 and the top surface of the SiC epitaxial layer 3 are flat, and the vertical coordinate is the doping concentration. As can be seen from fig. 3A, the curve 201 includes two injection peaks, and the curve 202 includes one injection peak; on the abscissa, the position of the injection peak of curve 202 is located between the positions of the two injection peaks of curve 201; on the ordinate, the size of the shallower injection peak in curve 201 is smaller than the size of the deeper injection peak, and the size of the injection peak in curve 202 is located between the sizes of the two injection peaks in curve 201.
The size of the shallower injection peak in the curve 201 is lower, so that the adjustment of the threshold voltage of the device can be realized; the larger magnitude of the deeper implant peak in curve 201 reduces short channel effects.
The position of the injection peak of curve 202 is located between the positions of the two injection peaks of curve 201, which has the advantage that a relatively low specific on-resistance is obtained while the device still has a high breakdown voltage, and that the highest electric field strength at the SiC and SiO2 interface, i.e. at the interface between the SiC epitaxial layer 3 and the gate dielectric layer 7, is reduced to an acceptable range, such as less than 2.0MV/cm, even below 1.5MV/cm, when the device is near breakdown.
In contrast, the shallow or deep injection peak of the curve 202 causes corresponding problems, and the following description will be made with reference to fig. 3B and 3C, respectively:
as shown in fig. 3B, the doping concentration profile of the JFET region is shown on the basis of fig. 3A when the implantation peak position of the JFET region is shallower than the desired value; curve 201a in fig. 3B is the same as curve 201 in fig. 3A; curve 202a is the doping concentration profile at dashed line BB in fig. 2, and it can be seen that the location of the injection peak of curve 202a is shallower than the location of the shallower injection peak in curve 201 a; the adverse effect of this situation is that the injection peak of curve 202a is closer to the surface, i.e., the SiC and SiO2 interface, and the highest electric field strength increases after the doping concentration at the SiC and SiO2 interface increases, which can affect the reliability of the device.
As shown in fig. 3C, the doping concentration profile of the JFET region is shown based on fig. 3A when the implantation peak position of the JFET region is deeper than the required value; curve 201B in fig. 3B is the same as curve 201 in fig. 3A; curve 202b is the doping concentration profile at dashed line BB in fig. 2, and it can be seen that the location of the injection peak of curve 202b is deeper than the location of the deeper injection peak in curve 201 b; the adverse effect of this is that the injection peak of curve 202b is farther from the surface, resulting in an increase in doping concentration inside the drift region, which can affect the breakdown voltage of the device, which can decrease.
In other embodiments, the anti-JFET region 3a is formed by stacking two doped second ion implantation regions of the first conductivity type with different implantation peak positions, and the implantation peak sizes of the two second ion implantation regions are the same or different. As shown in fig. 4, a second doping concentration profile of the channel region and the anti-JFET region of the planar SiC MOSFET device of the first embodiment of the invention; the abscissa and ordinate of fig. 4 are the same as those of fig. 3A, and the curve 201c is also the doping concentration profile along the solid line AA of fig. 2, and the curve 202c is also the doping concentration profile along the broken line BB of fig. 2, and the curve 201c is the same as that of fig. 3A. The curve 202c has two injection peaks, and the positions of the two injection peaks of the curve 202c are located between the positions of the two injection peaks of the curve 201c, and the sizes of the two injection peaks of the curve 202c are also located between the sizes of the two injection peaks of the curve 201 c.
In other embodiments, the channel region 4 is formed by overlapping three doped first ion implantation regions of the second conductivity type with different implantation peak positions. The anti-JFET region 3a consists of a second ion implantation region doped with the first conductivity type. The implantation peak position of the second ion implantation region of the anti-JFET region 3a is located between the shallowest implantation peak position and the sub-shallowest implantation peak position of the channel region 4; alternatively, the implantation peak position of the second ion implantation region of the anti-JFET region 3a is located between the sub-shallow implantation peak position and the deepest implantation peak position of the channel region 4.
As shown in fig. 5, a third doping concentration profile of the channel region and the anti-JFET region of the planar SiC MOSFET device according to the first embodiment of the present invention; the abscissa and ordinate of fig. 5 are the same as fig. 3A, and curve 201d is also the doping concentration profile along the solid line AA of fig. 2, and curve 202d is also the doping concentration profile along the broken line BB in fig. 2. It can be seen that curve 201d has three injection peaks and curve 202d has one injection peak, with the injection peak of curve 202d being located between the shallower two injection peaks of curve 201 d.
As shown in fig. 6, a fourth doping concentration profile of the channel region and the anti-JFET region of the planar SiC MOSFET device of the first embodiment of the invention; the abscissa and ordinate of fig. 6 are the same as fig. 3A, and curve 201e is also the doping concentration profile along the solid line AA of fig. 2, and curve 202e is also the doping concentration profile along the broken line BB in fig. 2. It can be seen that curve 201e has three injection peaks and curve 202e has one injection peak, with the injection peak of curve 202e being located between the positions of the two deeper injection peaks of curve 201 d.
Although only the fourth doping concentration profile is specifically disclosed above, other doping concentration profiles may not be listed one by one in the specification. In practice, however, in the first embodiment of the invention, the doping concentrations of the channel region 4 and the anti-JFET region 3a ensure that the following conditions are met:
1. the channel region 4 contains at least 2 implant peak concentrations and the anti-JFET region 3a contains at least one implant peak concentration.
2. The first injection peak concentration of the anti-JFET region 3a can be closer to the SiC body than the first injection peak concentration of the channel region 4.
3. The last injection peak concentration of the anti-JFET region 3a is closer to the surface of SiC than the last injection peak concentration of the channel region 4.
For more ion implantation conditions of the channel region 4 and the anti-JFET region 3a, a suitable implantation peak concentration profile can be obtained as described above and as actually needed.
In the first embodiment of the present invention, a heavily doped source region 6 of the first conductivity type is also formed in the surface region of the selected region of the channel region 4, and the gate structure also extends onto the surface of the source region 6.
A body contact region 5 heavily doped with the second conductivity type is also formed in a surface region of a selected region of the channel region 4.
The surfaces of the body contact region 5 and the source region 6 are connected to a source electrode 10 composed of a front metal layer through a source contact hole penetrating through an interlayer film 9.
In the first embodiment of the present invention, the planar SiC MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, it can also be: the planar SiC MOSFET device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.
The P-type dopant impurity includes aluminum (Al. Mu.m), and the N-type dopant impurity includes Nitrogen (Nitrogen).
Taking an N-type device as an example:
the channel region 4 and the anti-JFET region 3a are both formed by ion implantation. Wherein the ion implantation of the channel region 4 is typically implantation of Al μmin μm and the ion implantation of the anti-JFET region 3a is typically implantation of Nitrogen; in order to reduce damage to the SiC device from ion implantation, the temperature of the ion implantation may be increased, for example, to 500 degrees.
In some exemplary embodiments the following specific parameters can be employed:
the first is: the length of the channel region 4 is 0.5 μm and the width of the JFET region 3a is 1.5 μm; the implantation of the channel region 4 comprises 2 times, wherein the condition of the implantation is 0 degree implantation, the first time is implantation energy of 120keV and implantation dosage of 6.0e12cm -2 Al μm, the second time with an implantation energy of 600keV and an implantation dose of 8.0e13cm -2 Al μm implant of (C). The implantation of the anti-JFET region 3a comprises 1 time, the anti-JFET region 3a is implanted at an angle of 0 degrees, the implantation of the anti-JFET region 3a is performed at an implantation energy of 180keV and an implantation dose of 2.0e12cm -2 Nitrogen implant of (C) can also be increased to 3.0e12cm -2 . This situation corresponds to the first doping concentration profile shown in fig. 3A.
The second is: the length of the channel region 4 is 0.5 μm and the width of the JFET region 3a is 1.5 μm; the implantation of the channel region 4 comprises 2 times, wherein the condition of the implantation is 0 degree implantation, the first time is implantation energy of 120keV and implantation dosage of 6.0e12cm -2 The second time with an implantation energy of 600keV and an implantation dose of 8.0e13cm -2 Al μm implant of (C). The implantation of the anti-JFET region 3a comprises 2 times, namely 0 degree implantation, the first time with an implantation energy of 180keV and an implantation dose of 2.0e12cm -2 Nitrogen implant of (2) with an implant energy of 300keV and an implant dose of 2.0e12cm -2 Is injected by Nitrogen. This situation corresponds to the second doping concentration profile shown in fig. 4.
The planar SiC MOSFET device comprises a plurality of device units;
a cell is formed by 2 adjacent device units, in which a cell structure is shown in fig. 2, two of the device units share the JFET-resistant region 3a, channel regions 4 of the two device units are symmetrically disposed on both sides of the JFET-resistant region 3a, and the gate structures of the two device units are connected above the surface of the JFET-resistant region 3a to form a unitary structure.
In the first embodiment of the present invention, the channel region 4 and the anti-JFET region 3a are both composed of ion implantation regions, and the present invention specifically sets the ion implantation regions of the channel region 4 and the anti-JFET region 3a, mainly:
the ion implantation region of the channel region 4 is formed by overlapping a plurality of first ion implantation regions, so that the size and the position of the implantation peak value of each first ion implantation region can be respectively adjusted.
The size and position of the injection peak of the second ion injection region of the anti-JFET region 3a are set according to the size and position of the injection peak of each first ion injection region of the channel region 4, and under the condition that the injection peak position of the second ion injection region of the anti-JFET region 3a is ensured to be positioned at the bottom of the injection peak position of the shallowest first ion injection region of the channel region 4, the electric field intensity of the surface region of the anti-JFET region 3a can be reduced, namely the electric field intensity at the interface between the gate dielectric layer 7 and the SiC epitaxial layer 3 can be reduced, so that the reliability of the device can be improved; under the condition that the injection peak position of the second ion injection region of the anti-JFET region 3a is ensured to be positioned above the injection peak position of the deepest first ion injection region of the channel region 4, the breakdown voltage of the device can be ensured; the size of the injection peak of the second ion injection region of the anti-JFET region 3a in combination with the position setting of the injection peak can satisfy the requirement of the anti-JFET effect, so that the specific on-resistance of the device is reduced.
In addition, in the field of semiconductor manufacturing, an implantation peak corresponding to an ion implantation process refers to a maximum value of a doping concentration in an implantation region after ion implantation, and a magnitude of the implantation peak, that is, the maximum value of the doping concentration in the implantation region itself, and an implantation dose of the ion implantation correspond to each other; the position of the implantation peak, i.e., the depth position corresponding to the maximum value of the doping concentration in the implantation region, is also simply referred to as the implantation peak position, and corresponds to the implantation energy of the ion implantation.
Second embodiment planar SiC MOSFET device of the present invention:
as shown in fig. 7, a schematic cross-sectional structure of a planar SiC MOSFET device according to a second embodiment of the present invention; the second embodiment planar SiC MOSFET device of the present invention is different from the first embodiment planar SiC MOSFET device of the present invention in that the second embodiment planar SiC MOSFET device of the present invention has the following distinguishing features:
the planar SiC MOSFET device comprises a plurality of device units;
a cell is formed by 2 adjacent device units, in which a structure of one cell is shown in fig. 7, two device units share the anti-JFET region 3a, channel regions 4 of two device units are symmetrically disposed at both sides of the anti-JFET region 3a, and the gate structures of two device units have a space above the surface of the anti-JFET region 3a to reduce input capacitance. In fig. 7, two adjacent layers of gate conductive material of the gate structure are individually identified by the marks 8a and 8 b. As can be seen from comparison with fig. 2, the gate structure in fig. 2 covers the whole area between the channel regions 4, i.e. increases the overlap area between the gate and the drain, so that the gate-drain capacitance Cgd increases; in the device corresponding to fig. 7 according to the second embodiment of the present invention, the area coverage between the gate structure and the channel region 4 is smaller, so Cgd is reduced.
Third embodiment of the invention planar SiC MOSFET device:
fig. 8 is a schematic cross-sectional view of a planar SiC MOSFET device according to a third embodiment of the present invention; the difference between the planar SiC MOSFET device according to the third embodiment of the present invention and the planar SiC MOSFET device according to the first embodiment of the present invention is that the planar SiC MOSFET device according to the third embodiment of the present invention has the following distinguishing features:
the planar SiC MOSFET device comprises a plurality of device units, wherein 1 device unit forms a primitive cell; two of the device units, i.e. two of the primordia-tes, are shown in fig. 8.
Only one of the gate structures is provided on top of each of the channel regions 4 and one of the conductive channels is formed. The gate conductive material layer 8 of the gate structure is shown in fig. 8.
The second side of the gate structure of each of the device cells extends from the second side of the channel region 4 onto the adjacent surface of the anti-JFET region 3a and is spaced from the adjacent first side of the channel region 4.
The source region 6 and the body contact region 5 are formed between the first side of the gate structure and the first side of the channel region 4 of each of the device cells.
In fig. 2, since only one of the cells is shown, in practice, each cell is repeatedly arranged, the gate structure is formed on both sides of the channel region 4, and the central region of the channel region 4 is the source region 6 and the body contact region 5. Since a channel is formed on the surface of the channel region 4 covered by the gate structure, channels are formed on both sides of the channel region 4, and two channels are formed in total; in the cell of fig. 2, 2 channels are shown, each consisting of one channel of one of the channel regions 4.
Unlike the structure shown in fig. 2, only one of the gate structures is formed on one side of one of the channel regions 4 in fig. 8, and only one of the conductive channels is formed in the channel region 4 because the conductive channel is formed only in the coverage area of the gate structure; only one conductive channel is present in the cell in fig. 8.
Therefore, the structure shown in fig. 8 can increase the cell density, but decrease the channel density, and the channel resistance of the device increases, but the capacitance of the device decreases due to the decrease of the channel density.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (16)

1. A planar SiC MOSFET device, comprising:
a channel region formed in a selected region of the first conductivity type doped SiC epitaxial layer, a surface of the channel region covered by the gate structure for forming a conductive channel; the SiC epitaxial layer outside the channel region forms a drift region;
forming an anti-JFET region on the surface of the drift region between two adjacent channel regions;
the gate structure also extends onto the surface of the anti-JFET region;
the grid structure is formed by laminating a grid dielectric layer and a grid conductive material layer;
the channel region is formed by overlapping more than two second conductive type doped first ion implantation regions with different implantation peak positions;
the anti-JFET region is formed by overlapping more than one second ion implantation regions doped with the first conductivity type and different in implantation peak positions;
each of the first ion implantation regions in the channel region is configured to:
the deeper the injection peak position, the larger the injection peak; the shallower the injection peak position, the smaller the injection peak;
the threshold voltage of the planar SiC MOSFET device is regulated by the first ion implantation regions with the shallowest implantation peak positions, and short channel effects are reduced by the first ion implantation regions with the implantation peak positions below the shallowest implantation peak positions;
the implantation peak position and implantation dose of each of the second ion implantation regions of the anti-JFET region are set as follows:
the injection peak position of each second ion injection region is deeper than the shallowest injection peak position in the channel region so as to reduce the electric field intensity at the interface of the gate dielectric layer and the SiC epitaxial layer;
the injection peak position of each second ion injection region is shallower than the deepest injection peak position in the channel region, so that the breakdown voltage of the device is ensured;
the injection peak value of each second ion injection region is larger than the injection peak value of the first ion injection region with the shallowest injection peak position in the channel region, and the injection peak value of each second ion injection region is smaller than the injection peak value of the first ion injection region with the deepest injection peak position in the channel region, so that the JFET effect is reduced, and the specific on-resistance of the device is reduced.
2. A planar SiC MOSFET device as set forth in claim 1, wherein: the channel region is formed by superposing two second-conductivity-type-doped first ion implantation regions with different implantation peak positions.
3. A planar SiC MOSFET device as recited in claim 2, wherein: the anti-JFET region is composed of a second ion implantation region doped with a first conductivity type.
4. A planar SiC MOSFET device as recited in claim 2, wherein: the anti-JFET region is formed by superposing two doped second ion implantation regions with different implantation peak positions and the implantation peak sizes of the two second ion implantation regions are the same or different.
5. A planar SiC MOSFET device as set forth in claim 1, wherein: the channel region is formed by overlapping three first ion implantation regions doped with the second conductivity type and different in implantation peak positions.
6. A planar SiC MOSFET device as recited in claim 5, wherein: the anti-JFET region is composed of a second ion implantation region doped with a first conductivity type.
7. A planar SiC MOSFET device as recited in claim 6, wherein: an implantation peak position of the second ion implantation region of the anti-JFET region is located between a shallowest implantation peak position and a sub-shallowest implantation peak position of the channel region; alternatively, the implantation peak position of the second ion implantation region of the anti-JFET region is located between the sub-shallow implantation peak position and the deepest implantation peak position of the channel region.
8. A planar SiC MOSFET device as set forth in claim 1, wherein: a heavily doped source region of the first conductivity type is also formed in a surface region of a selected region of the channel region, the gate structure also extending onto the source region surface.
9. A planar SiC MOSFET device as recited in claim 8, wherein: a body contact region of a second conductivity type heavily doped is also formed in a surface region of a selected region of the channel region.
10. A planar SiC MOSFET device as recited in claim 9, wherein: the surfaces of the body contact region and the source region are connected to a source electrode composed of a front side metal layer through a source contact hole penetrating through an interlayer film.
11. A planar SiC MOSFET device as recited in claim 10, wherein: the planar SiCNMOSFET device comprises a plurality of device units;
and 2 adjacent device units form a primitive cell, wherein in the primitive cell, the two device units share the anti-JFET region, channel regions of the two device units are symmetrically arranged at two sides of the anti-JFET region, and gate structures of the two device units are connected above the surface of the anti-JFET region to form an integral structure.
12. A planar SiC MOSFET device as recited in claim 10, wherein: the planar SiCNMOSFET device comprises a plurality of device units;
and 2 adjacent device units form a primitive cell, wherein in the primitive cell, the two device units share the anti-JFET region, channel regions of the two device units are symmetrically arranged at two sides of the anti-JFET region, and the grid structures of the two device units are spaced above the surface of the anti-JFET region so as to reduce input capacitance.
13. A planar SiC MOSFET device as recited in claim 10, wherein: the planar SiCNMOSFET device comprises a plurality of device units, wherein 1 device unit forms a primitive cell;
providing only one of the gate structures on top of each of the channel regions and forming one of the conductive channels;
a second side of the gate structure of each of the device cells extends from the second side of the channel region onto an adjacent surface of the anti-JFET region and is spaced from an adjacent first side of the channel region;
the source region and the body contact region are formed between a first side of the gate structure and a first side of the channel region of each of the device cells.
14. A planar SiC MOSFET device as set forth in claim 1, wherein: the SiC epitaxial layer is formed on a SiC substrate and a buffer layer doped with a first conductivity type is arranged between the SiC epitaxial layer and the SiC substrate.
15. A method of fabricating a planar SiC MOSFET device according to any one of claims 1-14, characterized in that: the planar SiC MOSFET device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the planar SiC MOSFET device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
16. The planar SiC MOSFET device of claim 15, wherein: the P-type dopant impurity includes aluminum and the N-type dopant impurity includes nitrogen.
CN202111498285.2A 2021-12-09 2021-12-09 Planar SiC MOSFET device Pending CN116259644A (en)

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