JP2001118901A - Overlap deviation measuring method and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an overlap deviation measuring method capable of accurately measuring deviation of overlap between a first layer and a second layer which are formed by lamination in a manufacturing process of a semiconductor device, and the semiconductor device. SOLUTION: An LOCOS 12, an active region 13, and a gate oxide film 14 are formed sequentially on a silicon substrate 11. Halves of patterns of polysilicons 15-1, 15-2 are arranged on the LOCOS 12, remaining halves of the patterns are arranged on the active region 13. Capacitor elements 17-1, 17-2 which are composed of the active region 13, and the polysilicons 15-1, 15-2 which sandwich the gate oxide film 14, are formed. By measuring the difference in capacitances C1 and C2 of the capacitor elements 17-1, 17-2, overlap deviation between the active region 13 and the polysilicons 15-1, 15-2 is measured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overlay displacement measuring method for measuring an overlay displacement between a first layer and a second layer which are formed in an overlapping manner in a semiconductor device manufacturing process, and a semiconductor device. Related to the device.

[0002]

2. Description of the Related Art Generally, a semiconductor element (hereinafter simply referred to as an element) constituting a semiconductor device is formed from a plurality of patterned layers or films. The accuracy of the misalignment between the first layer and the second layer formed by superimposing the plurality of patterned layers or films has a large influence on the electrical characteristics of the device. When there is a large misalignment between the first layer and the second layer, adverse effects such as an increase in leak current and an increase in contact resistance occur. If the misalignment is extremely large, the element may not operate at all.

In a semiconductor device, a pattern (base pattern) of a first layer formed and processed in a certain patterning step and a pattern of a second layer formed and processed after the pattern processing of the first layer are performed. Conventionally, in order to measure the misalignment between the overlay patterns, the overlay measurement patterns are arranged in scribe lines of the patterns of the first and second layers, and the positional relationship between the overlay measurement patterns is optically determined. It is performed to measure at once. As the measurement pattern, a vernier pattern for visual inspection by a human, a box-in-box pattern or a bar-in-bar pattern for automatic measurement by an overlay measurement device is generally used.

FIG. 12 is a plan view of a vernier pattern for visual inspection.

FIG. 12 shows a main scale 121 which is a vernier pattern formed in a pattern of a first layer (lower layer) at a predetermined pitch, and a second scale at a pitch slightly different from the pitch of the main scale 121. The vernier scale 122 which is a vernier pattern formed in the pattern of the layer (upper layer) is shown. By visually inspecting the deviation between the main scale 121 and the sub-scale 122, it is determined whether or not the superposition deviation between the pattern of the first layer and the pattern of the second layer is good.
Note that FIG. 12 shows a state where the main scale 121 and the sub-scale 122 match.

FIG. 13 is a plan view of a box-in-box pattern for automatic measurement by the overlay measuring device.

FIG. 13 shows a main scale 1 which is a rectangular box pattern formed in the pattern of the first layer (lower layer).
31 and a sub-scale 132 which is a box pattern formed in the pattern of the second layer (upper layer) so as to surround the main scale 131 thereof. By measuring the shift between the main scale 131 and the sub-scale 132 with the overlay measuring device, it is determined whether or not the overlay shift between the first layer pattern and the second layer pattern is good. Note that FIG.
FIG. 3 shows a state in which the main scale 131 is perfectly placed in the sub-scale 132 without misalignment.

FIG. 14 is a plan view of a bar-in-bar pattern for automatic measurement by the overlay measuring device.

FIG. 14 shows a main scale 141 which is a bar pattern formed in a pattern of a first layer (lower layer) and a pattern of a second layer (upper layer) surrounding the main scale 141. The vernier 142 that is the formed bar pattern is shown. By measuring the deviation between the main scale 141 and the sub-scale 142 with the overlay measuring device, it is determined whether or not the overlay deviation between the first layer pattern and the second layer pattern is good. FIG. 14 shows a state in which there is no misalignment, and the upper, lower, left, and right distances of the main scale 141 and the sub-scale 142 match.

[0010]

In the above-described conventional optical overlay displacement measuring method, when the overlay measurement pattern (hereinafter, referred to as an overlay measurement mark) has an asymmetric shape, accurate measurement is difficult. is there. As a manufacturing process for inducing asymmetry of an overlay measurement mark in a semiconductor device, a CMP (Chemical Mecha)
(N.Political) step, an epitaxial step, and the like. In recent years, in the manufacturing process of semiconductor devices, in particular, the CMP process has been actively used. In the CMP process, STI (Shallow) which is a transistor forming process in a semiconductor device manufacturing process is performed.
A trench isolation (STI CMP) process is performed after a trench isolation process, an oxide CMP process is a wiring process in a semiconductor device manufacturing process for planarizing an interlayer insulating film, and a tungsten burying process is performed after the trench isolation process. There are a tungsten CMP process for removing and planarizing unnecessary tungsten, and a metal CMP process for removing and planarizing an unnecessary metal film in a dual damascene process.

In general, in a CMP process, while rotating a substrate wafer, an oxide film or a metal film on the surface of the substrate wafer is polished by utilizing a frictional force and a chemical etching force generated during the rotation to flatten or flatten the substrate wafer. Unnecessary metal film is removed. At this time, since the substrate wafer is rotated,
A constant force in the direction of rotation of the substrate wafer is applied to the substrate wafer and the polishing cloth. There is also a method of simultaneously rotating the substrate wafer and the polishing cloth. In the former case, polishing is always performed in a fixed direction. The latter is polished in a limited vector direction. In each case, anisotropy occurs in the polishing direction. As described above, in the case where the anisotropy occurs in the polishing direction, when a film having an original step is flattened by the CMP process, a difference in polishing speed occurs depending on the direction of the original step. Hereinafter, description will be made with reference to FIGS.

FIG. 15 is a sectional view of a pattern of the semiconductor device before being polished by an oxide film CMP process.
FIG. 4 is a cross-sectional view of a pattern of the semiconductor device after being polished by an oxide film CMP process.

FIG. 15 shows a silicon substrate 151 and a gate oxide film 152 formed on the silicon substrate 151.
A gate electrode 154 having a sidewall 153 formed on the gate oxide film 152 and an interlayer insulating film 155 formed so as to cover the gate electrode 154 are shown. The gate electrode 154 forms a main scale. The surface of the interlayer insulating film 155 has a step. here,
By the oxide film CMP process, the interlayer insulating film 155 is formed as shown in FIG.
When polishing is performed in the direction A indicated by the arrow 6, the step on the surface is reduced. However, it is not completely flat, and a small step remains on the interlayer insulating film 155 depending on the polishing direction after the CMP process. Therefore, the cross section of the interlayer insulating film 155 has an asymmetric shape as shown in FIG. When the main scale is optically observed through the interlayer insulating film 155 having an asymmetric surface, the displacement is observed. Therefore, the interlayer insulating film 1
When another layer having a vernier scale is formed on 55, an error occurs in the overlay displacement measurement.

[0014] Also, in the tungsten CMP process, the misalignment of the overlay measurement mark similarly occurs. Hereinafter, description will be made with reference to FIGS.

FIG. 17 is a diagram showing a tungsten C of a semiconductor device.
FIG. 1 is a sectional view of a pattern before being polished by an MP process.
FIG. 8 is a pattern sectional view of the same semiconductor device after being polished by a tungsten CMP process.

FIG. 17 shows a silicon substrate 171, an interlayer insulating film 173 having an opening formed on the silicon substrate 171, and a tungsten film having a main scale formed to cover the interlayer insulating film 173. 174 are shown. Here, when the tungsten film 174 is polished by the tungsten CMP process until the surface of the interlayer insulating film 173 is exposed in the direction indicated by the arrow A in FIG. 18, the tungsten film 174 embedded in the opening of the interlayer insulating film 173 is formed.
Forms a main scale. After this tungsten CMP process, a small step remains on the tungsten film 174 depending on the polishing direction. Therefore, the surface of the tungsten film 174 has an asymmetric shape as shown in FIG. Therefore, the main scale also has an asymmetric shape. Furthermore, interlayer insulating film 17
If another layer having a vernier scale is formed on 3, an error in overlay measurement occurs.

FIG. 19 is a view showing a bar-in-bar pattern after polishing in the tungsten CMP step and its waveform.

Since the main scale 191 constituting the bar-in-bar pattern shown in FIG. 19A is formed in the lower layer whose cross-sectional shape is asymmetric after the tungsten CMP process as described above, the main scale 191 is asymmetric. It has a shape. When the main scale 191 having such an asymmetric shape and the sub-scale 192 formed on the upper layer are measured by an overlay measuring device, the measurement waveform 191a of the main scale 191 is asymmetric as shown in FIG. Therefore, there is a problem that a measurement error occurs. The alignment mark used in such conventional optical measurement has a relatively large dimension with a width of about 1 μm to 10 μm. At such a large dimension, asymmetry in the CMP process occurs remarkably,
This leads to large measurement errors. In particular, in a line-shaped mark as shown in FIG. 19, asymmetry occurs remarkably in the CMP process.

Further, in the semiconductor device, as the manufacturing process proceeds, another layer is sequentially formed on the layer having the overlay measurement mark. For this reason, in the conventional optical misalignment measurement method, there is a problem that it is difficult to accurately measure the overlay measurement mark due to another layer overlapping the layer having the overlay measurement mark. .

In view of the above circumstances, the present invention provides an overlay capable of accurately measuring an overlay deviation between a first layer and a second layer which are formed in a semiconductor device manufacturing process. An object of the present invention is to provide a misalignment measuring method and a semiconductor device.

[0021]

According to the present invention, there is provided a method for measuring a displacement of a semiconductor device, comprising the steps of: forming an overlap between a first layer and a second layer which are formed in a manufacturing process of a semiconductor device; An overlay displacement measuring method for measuring misalignment, comprising an element having a pattern of a first layer and a pattern of a second layer, and having an electrical characteristic that changes according to the amount of the overlay displacement. It is characterized by including an element forming step and a characteristic measuring step of measuring electric characteristics of the element.

Since the overlay displacement measuring method of the present invention forms an element whose electric characteristics change in the element forming step and measures the electric characteristics of the element in the characteristic measuring step,
Compared with the conventional optical overlay displacement measurement method, STI
Due to the asymmetric cross section induced in the CMP process, the oxide film CMP process, the tungsten CMP process, the metal CMP process, the sputtering process, the etching process, the epitaxial process, etc., the position of the overlay measurement mark is shifted and a measurement error occurs. In the manufacturing process of the semiconductor device, without the fact that it is difficult to accurately measure the overlay measurement mark due to the layer superimposed on the layer having the overlay measurement mark. Overlapping deviation between the first layer and the second layer formed by superposition can be accurately measured.

Here, it is effective that the characteristic measuring step is a step of constructing a bridge circuit including the element and measuring an electric characteristic of the element.

As described above, when the bridge circuit is formed and the electric characteristics of the element are measured, the electric characteristics of the element can be measured with high accuracy.

Further, the element forming step is a step of forming an element whose capacitance changes according to the amount of misalignment, and the characteristic measuring step measures the capacitance deviation of the element. It may be a process.

Further, the element forming step is a step of forming an element whose contact resistance changes according to the amount of misalignment, and the characteristic measuring step is a step of measuring a deviation of the resistance value of the element. There may be.

Further, the element forming step is a step of forming a first element and a second element whose electric characteristics change in opposite directions according to the misalignment, and the characteristic measuring step is The step of measuring a difference between electrical characteristics of the first element and the second element may be performed.

As described above, when the difference between the electrical characteristics of the first element and the second element is measured, it is possible to more accurately measure the misalignment between the first layer and the second layer. it can.

A semiconductor device according to the present invention, which achieves the above object, has a first structure formed by overlapping in a manufacturing process.
And an element having electrical characteristics changed in accordance with misalignment between the second layer and the second layer, and a terminal connected to the element for measuring the electrical characteristics of the element. And

According to the semiconductor device of the present invention,
It is possible to accurately measure an overlay shift between a first layer and a second layer which are formed by being overlapped in a semiconductor device manufacturing process. Therefore, a highly reliable semiconductor device in which an increase in leakage current and an increase in contact resistance are suppressed can be manufactured.

[0031]

Embodiments of the present invention will be described below.

FIG. 1 is a cross-sectional view of a semiconductor device for the overlay displacement measuring method according to the first embodiment of the present invention, and FIG.
FIG. 2 is a plan view showing an overlap region of an active region and polysilicon in the semiconductor device shown in FIG. 1.

The overlay displacement measuring method according to the first embodiment measures an overlay displacement between a first layer and a second layer which are formed by superposition in a semiconductor device manufacturing process. A measurement method, comprising: an element formation step of forming an element including a pattern of the first layer and a pattern of the second layer, the element having an electrical characteristic that changes in accordance with the amount of misalignment of the overlay; And a characteristic measuring step of measuring electric characteristics of the element.

More specifically, the element forming step is a step of forming a capacitor element whose capacitance changes in accordance with the amount of misalignment, and the element forming step is performed in accordance with the misalignment. Forming a first capacitor element and a second capacitor element whose capacitances change in opposite directions.

The characteristic measuring step is a step of constructing a bridge circuit including the first and second capacitor elements and measuring the capacitance of the first and second capacitor elements. Further, the characteristic measuring step is a step of measuring a difference between the capacitances of the capacitor elements, and is a step of measuring a difference between the capacitances of the first and second capacitor elements.

In order to form the semiconductor device 10 shown in FIG. 1, first, the silicon substrate 11
An active region 13 (corresponding to the pattern of the first layer according to the present invention) is formed by forming a LOCOS 12 for maintaining insulation between elements on the upper surface, and then performing ion implantation using the LOCOS 12 as a mask. Further, a gate oxide film 14 is formed, a polysilicon film is formed, a gate pattern is baked, and the polysilicon film is etched to form polysilicon 15_1 and 15_2 (gates according to the present invention). (Corresponding to the pattern of the second layer). In the semiconductor device 10, the patterns of the polysilicons 15 _ 1 and 15 _ 2 serving as the gate electrodes are arranged halfway on the LOCOS 12, and the other half is arranged on the active region 13. FIG. 2 shows an overlapping region 16_1 between the polysilicon 15_1 and the active region 13 and an overlapping region 16_2 between the polysilicon 15_2 and the active region 13. In these overlapping regions 16_1 and 16_2,
First and second capacitor elements 17_1 and 17_2 formed of the active region 13 and the polysilicons 15_1 and 15_2 with the gate oxide film 14 interposed therebetween are formed. In the first capacitor element 17_1, the capacitance C1 changes according to the amount of misalignment of the overlap between the active region 13 and the polysilicon 15_1, and the second capacitor element 17_2
The capacitance C2 changes in accordance with the amount of misalignment between the active region 13 and the polysilicon 15_2.

Next, in the characteristic measuring step, the first and second
Of the capacitor elements 17_1 and 17_2
The difference of C2 is measured. In this characteristic measuring step,
A bridge circuit including the second capacitor elements 17_1 and 17_2 is formed and the first and second capacitor elements 1
The difference between the capacitances C1 and C2 of 7_1 and 17_2 is measured.

FIG. 3 is a diagram showing a bridge circuit in a characteristic measuring step of the overlay displacement measuring method according to the first embodiment of the present invention.

The bridge circuit 20 shown in FIG. 3 has the capacitor elements 17_1 and 17_2 shown in FIG. 2 and the resistance elements 21_1 and 21_2 having a predetermined resistance value R. Capacitor elements 17_1 and 17_ constituting bridge circuit 20
Connection point 22_1 and the resistance elements 21_1 and 21_
An AC power supply 23 is connected to the second connection point 22_2. In addition, the capacitor element 17_1 and the resistance element 21_1
Is connected to a first voltage measuring terminal 24_1, and the capacitor element 17_2 and the resistance element 21_2
The second voltage measurement terminal 24_2 is connected to the connection point 22_4. In the characteristic measuring step of the present embodiment, using such a bridge circuit 20, an AC voltage is applied from the AC power supply 23 to the bridge circuit 20, and the voltage between the voltage measurement terminals 24_1 and 24_2 is measured. Here, when there is no misalignment, the overlap between the polysilicon 15_1 and the polysilicon 15_2 on the active region 13 is equal, and therefore, the difference between the capacitances C1 and C2 is almost zero. Here, the resistance elements 21_1, 21_2
May be formed in the semiconductor device 10 using, for example, polysilicon, or may be formed outside the semiconductor device 10. When the resistance elements 21_1 and 21_2 are formed in the semiconductor device 10, the bridge circuit 20 may be formed by wiring in the semiconductor device 10 in advance, or the bridge circuit may be formed by using wiring outside the semiconductor device 10 during measurement. 20 may be configured.

FIG. 4 is a cross-sectional view of a semiconductor device having a relatively large overlay displacement between the active region and polysilicon for the overlay displacement measuring method according to the first embodiment of the present invention.

In the semiconductor device 30 of FIG. 4, the polysilicons 35_1 and 35_2 are shifted to the right with respect to the active region 33 in the figure. Therefore, the capacitance of the capacitor element 37_1 formed between the polysilicon 35_1 and the active region 33 is the same as that of the semiconductor element 1 shown in FIG.
0 is larger than the capacitance of the capacitor element 17_1.
On the other hand, the capacitance of the capacitor element 37_2 formed between the polysilicon 35_2 and the active region 33 is as shown in FIG.
Is smaller than the capacitance of the capacitor element 17_2 of the semiconductor element 10 of FIG. Therefore, the capacity of the capacitor element 37_1 is larger than the capacity of the capacitor element 37_2.

FIG. 5 is a graph showing the measured voltage measured by the bridge circuit shown in FIG. 3 for each of a plurality of semiconductor devices prepared by changing the overlay deviation between the active region and the polysilicon.

Since the bridge circuit 20 shown in FIG. 3 is an AC bridge circuit, as in the semiconductor device 10 shown in FIG.
_1 and the polysilicon 15_2 have the same amount of overlap, the capacitor elements 17_1 and 17
_2 become the same (Cl = C2), and the voltage between the voltage measurement terminals 24_1 and 24_2 is
As shown in the graph of FIG.

Further, as in the semiconductor device 30 shown in FIG. 4, the active region 33 and the polysilicons 35_1, 35
In the case where the direction of the overlay shift of _2 is the right direction in FIG. 4 (the overlay shift dimension is on the + side), Cl> C2, and the voltage between the voltage measurement terminals 24_1 and 24_2 is as shown in FIG.
Is higher than the voltage 0 V shown in the graph of FIG. On the other hand, the direction of the misalignment of the active region 33 and the polysilicons 35_1 and 35_2 is shown in FIG.
(To the minus side)
Cl <C2, and the voltage between the voltage measurement terminals 24_1 and 24_2 is a voltage in the left region that is larger than the voltage 0V shown in the graph of FIG. As described above, the measurement voltage increases regardless of the direction of the overlay shift. Based on such a voltage, the overlay displacement between the active region and the polysilicon can be accurately measured.

The overlay displacement measuring method of this embodiment is as follows.
As described above, the capacitance of the capacitor element formed according to the displacement of the overlap between the active region and the polysilicon is measured, and the overlap between the active region and the polysilicon formed by the overlap is measured. Is a method of measuring the displacement of the STI CMP process, the oxide film CMP process,
The measurement error of the overlay measurement mark does not occur due to the asymmetric surface shape induced in the tungsten CMP process, the metal CMP process, the epitaxial process, and the like. Further, it is not difficult to accurately measure the overlay measurement mark due to the layer overlapping the layer having the overlay measurement mark. Therefore, it is possible to accurately measure the shift of the overlap between the polysilicon and the active region formed in the semiconductor device manufacturing process.

In the manufacture of such semiconductor devices 10 and 30, processes such as a CMP process and an epitaxial process that generate asymmetrical shapes are not used. Even if such an asymmetrical process is used, it does not cause a large deviation measurement error.

For example, when STI is used for isolation between elements, an STI CMP process for flattening an insulating film buried in an isolation trench is performed. For this reason, the surface of the insulating film buried in the wide separation groove is not completely flattened, and an asymmetric step remains. However, in the overlay displacement measurement of the present embodiment, the capacitor elements 17_1, 17_2, and 37_ used for the overlay displacement measurement.
Active regions 13 and 3 forming 1, 37_2
No asymmetrical step is formed on the surface of No. 3. For this reason, in the overlay displacement measurement of the present embodiment, ST
Even if the I CMP process is used, the overlay displacement can be measured with high accuracy without being affected by asymmetry.

In the present embodiment, a bridge circuit is formed, and a difference between the capacitances of the capacitor elements is measured. Since the overlay deviation between the active region and the polysilicon is measured with high accuracy, the overlay deviation between the active region and the polysilicon can be measured with high accuracy. The bridge circuit needs to form a connection point (terminal) for connecting to an external device. In the normal manufacturing process, when the polysilicon layer is formed,
Such terminals are not formed, but are formed after the subsequent steps of contact formation and wiring formation. For this reason, at the stage where the polysilicon layer is formed, it is not possible to measure the misalignment between the active region and the polysilicon. Therefore, in the present embodiment, for example, a characteristic test is performed after the wiring process is completed, and a chip in which an abnormality is found may be used for investigating the cause of the abnormality. In such a case, the conventional optical measurement method has a problem that the measurement accuracy is deteriorated because a large number of layers are stacked on the measurement mark.
On the other hand, in the present embodiment, since the measurement is performed electrically,
Even if another layer is overlaid on the bridge element, there is an advantage that accurate measurement can be performed without being affected by the other layer.
However, at least in the wiring process, the measurement can be performed at the stage when the process to be measured is completed.

In this embodiment, the difference between the capacitances of the capacitor elements is measured by the bridge circuit. However, the capacitance of one of the capacitor elements or the capacitance of one of the capacitor elements is measured by a measuring device other than the bridge circuit. The capacitance of both capacitor elements may be measured, and the overlay displacement between the active region and the polysilicon may be measured based on the measurement results.

FIG. 6 is a sectional view of a semiconductor device for the overlay displacement measuring method according to the second embodiment of the present invention, and FIG.
FIG. 7 is a plan view showing an overlap region of a contact plug and polysilicon in the semiconductor device shown in FIG. 6.

The element forming step in the overlay displacement measuring method according to the second embodiment is a step of forming a resistive element whose contact resistance changes in accordance with the amount of overlay displacement. This is a step of forming a first resistance element and a second resistance element whose contact resistances change in opposite directions according to misalignment.

The characteristic measuring step is a step of forming a bridge circuit including the first and second resistance elements and measuring the resistance values of the first and second resistance elements. Further, the characteristic measuring step is a step of measuring a deviation of the resistance value of the resistance element, and is a step of measuring a difference between the resistance values of the first and second resistance elements.

In order to form the semiconductor device 40 shown in FIG. 6, first, a gate oxide film 42 is formed on a silicon substrate 41, and a sidewall 43 is formed on the gate oxide film 42.
44_1, 44 serving as gate electrodes having
— 2 is formed. Further, an interlayer insulating film 45 is formed, and then the interlayer insulating film 45 is partially etched using a mask,
A metal film is embedded in the etched portion to form a contact plug 4
6_1 and 46_2 are formed. Next, metals 47_1 and 47_2 are formed on portions of the interlayer insulating film 45 where the contact plugs 46_1 and 46_2 are formed. In the present embodiment, as shown in FIG.
In the middle, 1, 46_2 are arranged on polysilicons 44_1, 44_2 which function as gate electrodes. A first resistance element 49 which is a contact resistance between the contact plug 46_1 and the polysilicon 44_1 is provided in an overlapping region 48_1 of the contact plug 46_1 and the polysilicon 44_1.
— 1 is formed. A second resistance element 49_2, which is a contact resistance between the contact plug 46_2 and the polysilicon 44_2, is formed in an overlapping region 48_2 of the contact plug 46_2 and the polysilicon 44_2. First
The resistance element 49_1 has a resistance value R1 that changes in accordance with the amount of misalignment of the overlap between the contact plug 46_1 and the polysilicon 44_1, and the second resistance element 49_2 has an overlap between the contact plug 46_2 and the polysilicon 44_2. The resistance value R2 changes in accordance with the amount of deviation.

Next, in the characteristic measuring step, the first and second
The difference between the resistance values R1 and R2 of the resistance elements 49_1 and 49_2 is measured.

FIG. 8 is a view showing a bridge circuit in a characteristic measuring step of the overlay displacement measuring method according to the second embodiment of the present invention.

The bridge circuit 50 shown in FIG. 8 has the resistance elements 49_1 and 49_2 shown in FIG. 7 and the resistance elements 51_1 and 51_2 having a predetermined resistance value R. A DC power supply 53 is connected to a connection point 52_1 between the resistance elements 49_1 and 49_2 and a connection point 52_2 between the resistance elements 51_1 and 51_2 which constitute the bridge circuit 50. Also,
Connection point 52_3 between the resistance element 49_1 and the resistance element 51_1
Is connected to a first voltage measurement terminal 54_1, and a connection point 52_4 between the resistance element 49_2 and the resistance element 51_2 is connected to a second voltage measurement terminal 54_2. In the characteristic measuring step of the present embodiment, such a bridge circuit 50 is used.
To apply a DC voltage from the DC power supply 33 to the bridge circuit 50 to measure the voltage between the voltage measurement terminals 54_1 and 54_2. Here, when there is no misalignment, the amount of overlap of the contact plugs 46_1 and 46_2 with respect to the polysilicons 44_1 and 44_2 is equal, and therefore, the resistance value R of the resistance elements 49_1 and 49_2 is equal.
The difference between 1 and R2 is almost 0.

FIG. 9 shows a semiconductor device 60 having a relatively large overlay shift between polysilicon and a contact plug for the overlay shift measuring method according to the second embodiment of the present invention.
FIG.

In the semiconductor device 60 of FIG. 9, the contact plugs 66_1 and 66_2 are
_1 and 64_2 are shifted rightward in the figure. Therefore, the resistance of the resistance element 69_1 formed between the contact plug 66_1 and the polysilicon 64_1 is larger than the resistance of the resistance element 49_1 of the semiconductor element 40 in FIG. On the other hand, a resistance element 69_ formed between the contact plug 66_2 and the polysilicon 64_2.
2 is the resistance element 49_2 of the semiconductor element 40 of FIG.
Small compared to the resistance of Therefore, the resistance of the resistance element 69_1 is larger than the resistance of the resistance element 69_2.

FIG. 10 is a graph showing the measured voltage measured by the bridge circuit shown in FIG. 8 for each of a plurality of semiconductor devices prepared by changing the overlay deviation between the polysilicon and the contact plug.

Since the bridge circuit 50 shown in FIG. 8 is a DC bridge circuit, the amount of overlap between the polysilicon 44_1 and 44_2 and the contact plugs 46_1 and 46_2 is the same as in the semiconductor device 40 shown in FIG. , The resistance value R of the resistance elements 49_1 and 49_2
1 and R2 are the same (R1 = R2), and the voltage measuring terminal 5
The voltage between 4_1 and 54_2 becomes the minimum voltage 0V as shown in the graph of FIG.

As in the case of the semiconductor device 60 shown in FIG. 9, the direction of misalignment between the polysilicon 64_1 and 64_2 and the contact plugs 66_1 and 66_2 is changed as shown in FIG.
When the position is to the right of
R1> R2, and the voltage between the voltage measurement terminals 54_1 and 54_2 is a voltage on the negative side of the voltage 0V shown in the graph of FIG. On the other hand, when the direction of misalignment between the polysilicons 64_1 and 64_2 and the contact plugs 66_1 and 66_2 is the left direction in FIG. 9 (the misalignment dimension is a minus side), R1 <R2, and the voltage measurement terminal 54_
1, 54_2 is a voltage 0 shown in the graph of FIG.
The voltage is on the positive side of V. Based on such a voltage, the misalignment between the polysilicon and the contact plug can be accurately measured.

Here, the semiconductor device 4 shown in FIGS.
In the manufacture of 0,60, it is also possible to use a CMP process. For example, an oxide CMP process can be used to planarize the interlayer insulating films 45 and 65. In this step, an asymmetric step may be formed on the surface of the interlayer insulating film. However, in the overlay displacement measurement method according to the present embodiment, since an electrical measurement is performed instead of an optical measurement, the asymmetric shape of the interlayer insulating film surface does not cause a large measurement error. Also, a tungsten CMP process can be used to form the contact plugs 46_1, 46_2 and 66_1, 66_2. However, the size of the contact hole is, for example, 0.2
In the 5 μm generation, it is as small as about 0.32 μm. Moreover, it is not a line pattern but a hole pattern. In such a small hole pattern, the asymmetry due to the CMP process does not significantly occur. Even if a small asymmetry occurs, the influence on the electrical measurement performed in the present embodiment is small. Therefore, in the overlay displacement measuring method of the present embodiment, even when the CMP process is used,
The overlay displacement can be accurately measured.

FIG. 11 is a schematic view of a semiconductor device according to one embodiment of the present invention.

A semiconductor device 70 shown in FIG. 11 has a first layer 71 and a second layer
Elements 73_1 and 73_2 whose electrical characteristics change in accordance with the misalignment between the layers 72_1 and 72_2. First layer 71, second layers 72_1, 72_
2 includes terminals 74_1, 74_2, and 7 for measuring electrical characteristics.
4_3 are connected. Here, the first layer 71 and the second layers 72_1 and 72_2 are, for example, the active region 13 and the polysilicons 15_1 and 15_2 shown in FIG. 1, and the elements 73_1 and 73_2 having electrical characteristics include a capacitor element and a resistor. Element, inductance element and the like. By forming such a semiconductor device 70, measuring devices are connected to terminals 74_1, 74_2, and 74_3 for measuring electrical characteristics to measure capacitances, resistance values, inductors, and the like of the elements 73_1 and 73_2. The first layer 71 and the second layer 7
2_1 and 72_2 can be accurately measured. Therefore, a highly reliable semiconductor device in which an increase in leakage current and an increase in contact resistance are suppressed can be manufactured.

[0065]

As described above, according to the present invention,
It is possible to accurately measure an overlay shift between a first layer and a second layer which are formed by being overlapped in a semiconductor device manufacturing process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a semiconductor device for an overlay displacement measuring method according to a first embodiment of the present invention.

FIG. 2 is a plan view showing an overlap region of an active region and polysilicon in the semiconductor device shown in FIG. 1;

FIG. 3 is a diagram illustrating a bridge circuit in a characteristic measuring step of the overlay displacement measuring method according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a semiconductor device having a relatively large overlay displacement between an active region and polysilicon for the overlay displacement measurement method according to the first embodiment of the present invention.

FIG. 5 is a graph showing measured voltages measured by the bridge circuit shown in FIG. 3 for each of a plurality of semiconductor devices created by changing the overlay shift between the active region and the polysilicon.

FIG. 6 is a cross-sectional view of a semiconductor device for an overlay displacement measuring method according to a second embodiment of the present invention.

FIG. 7 is a plan view showing an overlapping region of a contact plug and polysilicon in the semiconductor device shown in FIG. 6;

FIG. 8 is a diagram illustrating a bridge circuit in a characteristic measuring step of the overlay displacement measuring method according to the second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a semiconductor device having relatively large overlay shift between polysilicon and a contact plug for the overlay shift measuring method according to the second embodiment of the present invention.

FIG. 10 is a graph showing measured voltages measured by the bridge circuit shown in FIG. 8 for each of a plurality of semiconductor devices created by changing the misalignment between the polysilicon and the contact plug.

FIG. 11 is a schematic view of a semiconductor device according to an embodiment of the present invention.

FIG. 12 is a plan view of a vernier pattern for visual inspection.

FIG. 13 is a plan view of a box-in-box pattern for automatic measurement by the overlay measurement device.

FIG. 14 is a plan view of a bar-in-bar pattern for automatic measurement by the overlay measurement device.

FIG. 15 is a pattern cross-sectional view of the semiconductor device before being polished by an oxide film CMP process.

FIG. 16 is a pattern cross-sectional view of the semiconductor device after being polished by an oxide film CMP step.

FIG. 17 is a sectional view of a pattern of the semiconductor device before being polished by a tungsten CMP process.

FIG. 18 is a sectional view of a pattern of the semiconductor device after being polished by a tungsten CMP process.

FIG. 19 is a view showing a bar-in-bar pattern after polishing in a tungsten CMP process and a measured waveform thereof.

[Explanation of symbols]

10, 30, 40, 60, 70 Semiconductor device 11, 31, 41, 61 Silicon substrate 12, 32 LOCOS 13, 33 Active region 14, 34, 42, 62 Gate oxide film 15_1, 15_2, 35_1, 35_2, 44_1,
44_2, 64_1, 64_2 Polysilicon 16_1, 16_2, 48_1, 48_2 Overlap area 17_1, 17_2, 37_1, 37_2 Capacitor element 20, 50 Bridge circuit 21_1, 21_2, 49_1, 49_2, 51_1
51_2, 69_1, 69_2 resistance element 22_1, 22_2, 22_3, 22_4, 52_1,
52_2, 52_3, 52_4 Connection point 23, AC power supply 24_1, 24_2, 54_1, 54_2 Voltage measurement terminal 43, 63 Sidewall 45, 65 Interlayer insulating film 46_1, 46_2, 66_1, 66_2 Contact plug 47_1, 47_2 Metal 71 First Layer 72_1, 72_2 Second layer 73_1, 73_2 Element 74_1, 74_2, 74_3 Terminal

Claims (6)

[Claims] An overlay displacement measuring method for measuring an overlay displacement between a first layer and a second layer which are formed in an overlapping manner in a manufacturing process of a semiconductor device, the method comprising: An element forming step of forming an element including a layer pattern and a pattern of the second layer, the element having an electrical property that changes in accordance with the amount of misalignment, and a property measuring step of measuring the electrical property of the element And a superposition misalignment measuring method. 2. The overlay displacement measuring method according to claim 1, wherein the characteristic measuring step is a step of configuring a bridge circuit including the element and measuring an electric characteristic of the element. 3. The element forming step is a step of forming an element whose capacitance changes according to the amount of misalignment, and the characteristic measuring step measures a deviation of the capacitance of the element. The method according to claim 1, wherein the method is a step. 4. The element forming step is a step of forming an element whose contact resistance changes according to the amount of misalignment, and the characteristic measuring step is a step of measuring a deviation of a resistance value of the element. The overlay displacement measuring method according to claim 1, wherein: 5. The element forming step is a step of forming a first element and a second element whose electric characteristics change in opposite directions according to overlay deviation. 2. The method according to claim 1, further comprising the step of measuring a difference between electrical characteristics of the first element and the second element. 6. An element having electric characteristics changed according to a shift in superposition between a first layer and a second layer formed by superposition in a manufacturing process, and an element connected to the element. A semiconductor device comprising: a terminal for measuring electrical characteristics of the element.