JP2001118060A - Fast parallel image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fast parallel image processor which can speed up the data transfer between image processing units and can process an image fast by suppressing the restriction of the number of image processors and greatly increasing their parallelism. SOLUTION: Plural data transfer units 20 and 21 are connected in a network by arraying plural image processing units 22 for every specific area on the top surface of an object 30 of image processing and constituting a multistage tree structure above the image processing units 22 in the bottom layer. According to plural feature data obtained from image data by the specific areas that the image processing units 22 take in, the data transfer units 21 and 20 in the higher layer specify reference data representing features of the pattern of the top surface of the object 30 of image processing. The specified reference data are transferred form the data transfer unit 20 in the top layer to the respective image processing units 22 along the tree structure and the image processing units 22 process the image in parallel while referring to the reference data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed parallel image processing device used for a semiconductor macro inspection device, a flat panel display appearance inspection device, a steel plate inspection device, a paint inspection device, and the like.

[0002]

2. Description of the Related Art Conventional wide-range image processing is often performed using a line sensor, and when high-speed processing is required, a plurality of line sensors are connected in parallel. A method of scanning side by side is used. When using a line sensor,
A high-performance stage that moves the object in synchronization with the scanning of the line sensor is required. Further, due to the characteristics of the line sensor, it is necessary for the object to be image-inputted to have a constant shape in the scanning direction, for example, a flat shape or a linear shape extruded from a certain mold. When a plurality of line sensors are used to improve the input resolution, each sensor is taken into one image processing unit and processed by one processor. This is because the image processing processor of the line sensor is not as widely used as the area sensor, and is expensive hardware.

On the other hand, when performing a wide range of image processing using an area sensor, a single area sensor is most often used because captured image data is often used as continuous data. However, the resolution is often lower than that of the line sensor, so that the resolution may be increased by narrowing the visual field range, and the entire surface of the image processing object may be processed by the operation of the stage or the like. Even when multiple area sensors (or line sensors) are used, discontinuity of image data between input sensors cannot be processed at high speed, so image data from multiple sensors is imported into one image processing unit and processed. I do. In addition, when the processing of the image data captured by each sensor is independent and there is no particular correlation between the image data, a wide range of image processing is performed using a plurality of area sensors (or line sensors).

The reason why a plurality of image input sensors are processed by one image processing processor is that there is no good means for distributing data at high speed among the plurality of image processing processors.

As shown in FIG. 5, in the case of an image processing apparatus in which image processors 11 are connected by bus connection, data transfer between the image processors 11 is fast,
When accessing the memory 12 on the bus 10,
Therefore, there are disadvantages that the other image processing processors 11 cannot operate, and the number of processors that can be coupled to the bus 10 is limited due to a problem in electrical characteristics.
Further, such an image processing apparatus requires a dedicated hardware design, and is relatively expensive.

Other image processing apparatuses include the simplest method of causing an image processor to perform processing in parallel, such as Ethernet or USB (Universal Serial Bus).
There is a method in which a plurality of image processors are connected by a method such as star connection by loose coupling.

FIG. 6 is a schematic block diagram of a star-coupled image processing apparatus. This image processing apparatus includes a plurality of image processors 11 and each image processor 11.
And one HUB (line concentrator) 13 to which is connected. This image processing apparatus, when transferring an event captured by a specific sensor (not shown) to another image processor 11, communication time increases in proportion to the number of image processors 11, and The advantages of processing cannot be fully utilized. That is, in the parallel image processing of this image processing apparatus, there is a problem that it is difficult to efficiently access the distributed data evenly. Therefore, an operation with feedback such as processing the data using local image data, sequentially applying the processed data to the entire input image data in a local range, and performing the entire processing. Requires a parallel processing mechanism that can evenly access data to the entire image memory.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed parallel image processing capable of speeding up data transfer between image processing units, increasing the number of image processing processors, and dramatically improving parallelism to perform high-speed image processing. It is to provide a device.

[0009]

In order to achieve the above object, a high-speed parallel image processing apparatus according to the present invention is arranged for each predetermined area on the surface of an object to be image-processed. A plurality of image processing units, and a plurality of data transfer units that are connected to a network such that the plurality of image processing units are the lowermost layer to form a multi-level tree structure and process data transferred from the lower layer side Wherein each of the data transfer units transfers data from the lower layer side to the upper layer side and from the upper layer side to the lower layer side along the tree structure.

According to the high-speed parallel image processing apparatus having the above configuration, the plurality of image processing units are arranged in, for example, a grid or a straight line for each predetermined area on the surface of the object to be image-processed. Process the captured image data every time. A plurality of data transfer units network-connected so as to form a multi-stage tree structure at an upper level with the plurality of image processing units as the lowest layer, data is transferred from the lower layer side to the upper layer side along the tree structure. To transfer. Then, the data obtained from the plurality of image processing units is processed and extracted by the data transfer unit on the upper layer side, and the processing result (for example, the characteristic of the pattern of the surface of the image processing object) is obtained. Again, the image data is efficiently distributed to the image processing units at a high speed, and the parallel processing can be performed by the image processing units according to the processing result. Therefore, the speed of data transfer between the image processing units can be increased, the restriction on the number of image processing processors can be suppressed, and the parallel processing can be dramatically improved to perform image processing at high speed.

In one embodiment of the present invention, each of the image processing units analyzes the image data captured for each of the predetermined regions, and sends data representing the analysis result to each of the image processing units. The data is transferred to the corresponding upper layer data transfer unit.Among the data transfer units, the intermediate layer data transfer unit analyzes the data representing the analysis result on the lower layer side and converts the data representing the analysis result. Further, the data is transferred to a data transfer unit of an upper layer, and the data transfer unit of the uppermost layer among the data transfer units is characterized by a pattern characteristic of the surface of the image processing object based on data representing an analysis result from the lower layer. It is characterized by performing extraction.

According to the high-speed parallel image processing apparatus of the embodiment, each of the image processing units analyzes the image data captured for each of the predetermined regions, and data representing the analysis result corresponds to each of the image processing units. To the upper layer data transfer unit. The data transfer unit of the intermediate layer analyzes the data representing the analysis result of the lower layer, transfers the data representing the analysis result to the data transfer unit of the upper layer, and transmits the data transfer unit of the uppermost layer. Since the feature extraction of the pattern on the surface of the image processing object is performed, the concentration of data can be reduced and the feature extraction of the image data can be performed at high speed.

In one embodiment of the present invention, the high-speed parallel image processing apparatus is arranged so that the uppermost data transfer unit along the tree structure transfers the lowermost layer image processing unit to the image processing object surface pattern. It is characterized in that reference data representing a feature is transferred.

According to the high-speed parallel image processing apparatus of the above embodiment, by utilizing the network having the tree structure, the reference data representing the characteristics of the pattern of the surface of the image processing object is effectively dispersed, and The reference data can be transferred to the processing unit, and the data transfer time can be reduced.

[0015] In one embodiment, the high-speed parallel image processing apparatus according to the present invention is characterized in that the data transfer of the upper layer is performed based on a plurality of characteristic data obtained from the image data for each of the predetermined regions, which are taken in by each of the image processing units. The unit specifies reference data representing the characteristics of the pattern on the surface of the image processing object, and converts the reference data specified by the data transfer unit of the upper layer from the data transfer unit of the upper layer along the tree structure to the most. The image data is transferred to the lower image processing units, and the image processing units perform image processing in parallel with reference to the reference data.

According to the high-speed parallel image processing apparatus of the above embodiment, based on a plurality of feature data obtained from the image data of each predetermined area taken in by the image processing unit,
The upper layer data transfer unit specifies reference data representing the characteristics of the pattern of the image processing object surface, and the upper layer data transfer unit specifies the reference data specified by the upper layer data transfer unit along the tree structure. The data is transferred from the data transfer unit to each of the image processing units as the lowest layer, and the image processing units perform image processing in parallel with reference to the transferred reference data. Therefore, by specifying the reference data representing the characteristics of the pattern of the object for each image processing target, without being affected by the fluctuation component due to the variation of the state or brightness of the work for each image processing target, High-precision image processing can be performed.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A high-speed parallel image processing apparatus according to the present invention will be described below in detail with reference to the illustrated embodiments.

FIG. 1 is a schematic block diagram of an image processing unit of a high-speed parallel image processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a three-stage tree structure of the high-speed parallel image processing apparatus. It is. In FIG. 1, reference numeral 1 denotes a sensor, 2 denotes an image processor for processing image data from the sensor 1, and 3 denotes a communication interface. The sensor 1, the image processor 2, and the communication interface 3 constitute an image processing unit 22. Then, as shown in FIG. 2, the plurality of image processing units 22 are divided into groups of five, and each group is connected to a plurality of intermediate layer data transfer units 21, respectively.
Further, the data transfer unit 21 of the intermediate layer is connected to the uppermost data transfer unit 20 to form a tree-structured network. The image processing unit 22
Are arranged in a grid pattern for each predetermined area on the surface of the object 30 for image processing. The image processor 2 has an image memory (not shown) for storing image data.

In the high-speed parallel image processing apparatus having the above configuration, when an image acquisition command is transferred from the data transfer unit 20 of the uppermost layer to the data transfer unit 21 of the intermediate layer, the image acquisition command is immediately sent to the lowermost layer. The image is transmitted to the image processing unit 22. When an image acquisition command is transmitted to the image processing units 22, each image processing unit 22 acquires images in parallel. Therefore, unlike the case where a line sensor is used, there is no need to change the positional relationship between the sensor and the target object and perform image acquisition many times. Next, when the image is obtained, the image data is processed and extracted in each image processing unit 22 to compress the information amount of the image data.
For example, data processing such as extraction of a necessary portion, calculation of average illuminance, feature extraction, and band limitation is performed. Next, the intermediate-layer data transfer unit 21 collectively processes and extracts a plurality of image data as the feature data transferred from the image processing unit 22 having the lower structure, and transfers the processed data to the data transfer unit 20 of the highest layer. I do. As an example of the process at this time, a process of transferring the image data as it is to the upper data transfer unit, removing data outside 3σ (standard error), or extracting only the median value may be applied. Then, the data transfer unit 20 of the uppermost layer uses the feature data processed by the multi-stage processing and the feature extraction filter,
Reference data (data representing the characteristics of the pattern on the surface of the object) suitable for the object 30 currently undergoing image processing is reconstructed.
Then, the reference data is stored in a plurality of image processing units 22.
At high speed through a tree-structured network.
After that, each image processing unit 2 to which the reference data is distributed
In 2, the image processing is performed again based on the reference data.

Next, the case where the high-speed parallel image processing apparatus is applied to an automatic wafer macro inspection apparatus will be described.

As shown in FIG. 3, one part (23 in FIG. 3) of the reference data as the characteristic data obtained from the image data captured by the sensor 1 (shown in FIG. 1) of the lowermost image processing unit 22. ), The reference pattern 24 is synthesized by the intermediate layer data transfer unit 21 using pattern matching and the known inter-camera distance. Then, as shown in FIG. 4, in the data transfer unit 20 of the uppermost layer, the average of the reference patterns 24 created by the data transfer units 21 of each intermediate layer is averaged, and only one reference data 25 representing the whole is obtained. create.

In this automatic wafer macro inspection apparatus, new reference data 25 representing the whole is distributed to each of the lowermost image processing units 22 (shown in FIGS. 1 and 2), and each image processing unit 22 performs pattern logic. The ideal input image data is created based on the address (the coordinates of the sensor 1), and the pattern data is offset from the actual input image data, thereby extracting a flaw or a pattern defect. For example, FIG. 7 shows an IC pattern on an IC wafer and a field of view 15 of each sensor 1 (only four are shown in FIG. 7), and an IC pattern 16 on the wafer repeats the same pattern at a constant cycle. Then, a part of the pattern is taken out and a reference pattern 14 as reference data is created.
Then, a pattern existing in each visual field range 15 and locally the same as the reference pattern 14 is erased, thereby extracting a flaw or a pattern defect other than the reference pattern. FIG. 8 is a schematic diagram for explaining the extraction of this flaw or pattern defect. FIG. 8B shows a cross-sectional pattern of the in-field data with respect to the cross-sectional pattern of the reference data shown in FIG. When a pattern defect is included as shown in FIG. 8C, the pattern defect is extracted as shown in FIG. 8C by canceling the reference data.

As described above, based on the characteristic data obtained from the plurality of image processing units 22, the upper layer side data transfer units 21 and 20 obtain the reference data representing the characteristics of the pattern on the surface of the image processing object. Then, the reference data is efficiently and quickly distributed to the respective image processing units 22,
Each image processing unit 22 according to the distributed reference data
To perform parallel processing. Therefore, the data transfer between the image processing units 22 can be performed at high speed, the restriction on the number of image processing processors can be suppressed, and the parallel processing can be dramatically improved to perform high-speed image processing.

Each of the image processing units 22 analyzes the image data captured for each predetermined area, and transfers data representing the analysis result to the data transfer unit 21 of the intermediate layer. Numeral 21 analyzes data representing the analysis result of the lower layer, transfers the data representing the analysis result to the data transfer unit 20 of the uppermost layer, and causes the data transfer unit 20 of the uppermost layer to perform image processing on the object. Since the feature extraction of the surface pattern is performed, the concentration of data can be reduced, and the feature extraction of the image data can be executed at high speed.

Further, the reference data representing the characteristics of the pattern on the surface of the object 30 can be effectively dispersed by using the network having the tree structure, and the reference data can be transferred to each image processing unit 22. Can be shortened.

Further, by specifying the reference data representing the feature of the pattern of the object for each image processing object, the influence of the fluctuation component due to the variation of the state of the work or the brightness of each image processing object can be eliminated. High-precision image processing can be performed.

In the above embodiment, the data transfer unit 21 of the intermediate layer is connected to each of the five image processing units 22, and the data transfer units 21 of the four intermediate layers are connected to the data transfer unit 20 of the uppermost layer. Although the high-speed parallel image processing apparatus having a tree structure with a tiered structure has been described, the tree structure of the image processing unit and the data transfer unit is not limited to this, and may be set as appropriate according to the configuration of the image processing target and the sensor.

In the above embodiment, the image processing units 22 are arranged in a lattice, but may be applied to a high-speed parallel image processing apparatus in which image processing units are arranged in a straight line.

[0029]

As is apparent from the above description, the high-speed parallel image processing apparatus of the present invention makes it possible to execute filter processing and the like in multiple stages in parallel on image data simultaneously fetched from a plurality of image processing units. In addition, feature extraction of image data can be executed at high speed. In addition, the extracted reference data representing the characteristics of the pattern on the surface of the image processing object can be distributed to a plurality of image processing units at high speed, and each image processing unit uses the reference data to generate a fluctuation component (workpiece). , And high-accuracy image processing in which variations in brightness and brightness are suppressed. Also, compared to a bus-coupled parallel image processing system, the number of image processors can be significantly increased, and the bottleneck of data transfer is alleviated compared to a loosely-coupled network using a star connection. The number of processing units can be greatly increased, and a high-speed parallel image processing device capable of processing a wide range of images at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing unit of a high-speed parallel image processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a tree structure of a three-stage configuration of the high-speed parallel image processing apparatus.

FIG. 3 is a diagram showing a concept of creating reference data in an intermediate layer data transfer unit from image data obtained from a lowermost image processing unit.

FIG. 4 is a diagram showing a concept of creating one reference data as a whole from reference data of a plurality of intermediate layers.

FIG. 5 is a schematic block diagram showing a configuration of a bus-coupled parallel image processor of a conventional image processing apparatus.

FIG. 6 is a schematic block diagram showing the configuration of a star-coupled parallel image processor of a conventional image processing apparatus.

FIG. 7 is a plan view showing a pattern on an IC wafer and a visual field range.

FIG. 8 is a schematic diagram for explaining a pattern defect extracted based on reference data.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Sensor, 2 ... Image processor, 3 ... Communication interface, 10 ... Bus, 11 ... Image processor 12 ... Memory, 13 ... HUB, 14 ... Reference pattern, 15 ... Viewing range, 16 ... IC pattern, 20 ... Most Upper layer data transfer unit, 21 intermediate layer data transfer unit, 22 lowermost layer image processor, 23 part of reference data, 24 reference data synthesized in intermediate layer, 25 created in uppermost layer Reference data obtained, 30 ... object.

 ──────────────────────────────────────────────────の Continued on the front page F term (reference) 5B057 AA04 CA08 CA12 CB08 CB12 CH04 CH11 DA03 DA08 DB02 DC30

Claims (4)

[Claims] 1. A plurality of image processing units arranged for each predetermined area on the surface of an image processing object, and taking in and processing image data for each of the predetermined areas; A plurality of data transfer units network-connected to form a multi-stage tree structure, wherein each of the data transfer units is arranged from the lower layer side to the upper layer side and from the upper layer side to the lower layer side along the tree structure. A high-speed parallel image processing apparatus for transferring data to a computer. 2. The high-speed parallel image processing device according to claim 1, wherein each of the image processing units analyzes the image data captured for each of the predetermined regions, and converts data representing the analysis result into each of the image processing. The data is transferred to the upper layer data transfer unit corresponding to the unit. The data transfer unit of the intermediate layer among the data transfer units analyzes the data representing the analysis result of the lower layer side and represents the analysis result. The data is further transferred to the data transfer unit on the upper layer side, and the data transfer unit on the uppermost layer among the data transfer units is arranged on the surface of the image processing object based on the data representing the analysis result from the lower layer. A high-speed parallel image processing apparatus for extracting pattern features. 3. The high-speed parallel image processing apparatus according to claim 1, wherein the data processing unit of an upper layer is transferred from the data transfer unit of an upper layer to each of the image processing units of a lower layer along the tree structure. A high-speed parallel image processing device for transferring reference data representing a feature of a pattern. 4. The high-speed parallel image processing device according to claim 1, wherein the upper layer includes a plurality of feature data obtained from the image data for each of the predetermined regions, which are taken in by each of the image processing units. The data transfer unit specifies reference data representing the characteristics of the pattern on the surface of the image processing object, and converts the reference data specified by the data transfer unit in an upper layer into the data transfer unit in an upper layer along the tree structure. A high-speed parallel image processing apparatus, wherein the image data is transferred to the image processing units, which are the lowest layers, and the image processing units perform image processing in parallel with reference to the reference data.