JP2001113751A - Driving ic, light emitting element and optical printing head - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an optical printing head suppressed in brightness irregularity. SOLUTION: In a driving IC equipped with a plurality of output terminals DO for driving elements, the first drive part 2 connected to the output terminals DO, a plurality of group selecting terminals CD for selecting a plurality of groups (m) and the second drive part 3 connected to the group selecting terminals CD, a plurality of sets of terminal parts 31 each constituted of the terminals CD for selecting a plurality of groups, are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical print head used for a recording head of a printer or the like.
The present invention relates to a novel driving IC for driving a light emitting element configured to perform time-division driving within the element, and an optical print head using the same.

[0002]

2. Description of the Related Art As shown in Japanese Utility Model Publication No. 6-48887, a light emitting element (array) used in a conventional optical print head has individual electrodes corresponding to a plurality of light emitting portions on a one-to-one basis. And a common electrode for each light emitting unit is provided on the back side of the element, so that it is not possible to perform time-division driving within one element. Since it is not possible to perform time-division driving, it is necessary to provide the same number of individual electrodes as the number of light-emitting portions. As the density of the light-emitting portions increases, the individual electrodes are correspondingly arranged at a high density. There was a problem that connection became difficult.

In order to solve such a problem, Japanese Patent Laid-Open No.
JP-163980A proposes a light emitting device capable of time-division driving within the device. That is, a plurality of light emitting units on a light emitting element are divided into a plurality of m groups, m common electrodes are provided so as to be connected to the light emitting units of each group, and individual electrodes connected to m light emitting units belonging to different groups. By providing n light emitting elements, a light emitting element having m × n light emitting units has been proposed. According to this light emitting element, the number of individual electrodes is reduced to 1 / the value of the conventional one by selecting m common electrodes in a time-division manner.
m, so that connection with the driving IC can be facilitated.

[0004] Such a light emitting element can be driven in a time-division manner by using a driving IC similar to the conventional one. However, in this case, a driving circuit for selecting a common electrode in a time-division manner is separately required. Therefore, development of a versatile driving IC suitable for time-division driving is desired.

Accordingly, the applicant of the present application has considered the above points,
Japanese Patent Laid-Open No. Hei 10-226102 proposes a driving IC incorporating a driving circuit for selecting a common electrode in a time-sharing manner. Since the terminal section in which the above terminals are assembled is arranged at the center of the IC, the following problems have been encountered.

[0006]

That is, a plurality of (n = 96) light-emitting elements are connected to one group selection terminal. When these light-emitting elements are turned on simultaneously, only one light-emitting element is turned on. The first problem is that the luminance of the light emitting unit differs when the light emitting units belonging to the same group connected to one group selection terminal are simultaneously turned on. There is a second problem that there is a difference. The first problem was found to be due to the fact that the amount of voltage drop due to the internal resistance existing around the group selection terminal fluctuates depending on the number of lighting of the light emitting unit, and thereby the driving voltage of the light emitting unit fluctuates. Was. Further, it has been found that the second problem is caused by the fact that the wiring resistance between the group selection terminal and the light emitting unit differs depending on the position of the light emitting unit.

Accordingly, the present invention has been made in view of the above points, and has as its main object to provide an optical print head capable of suppressing a printing unevenness by reducing a luminance difference generated between light emitting units belonging to the same group. Make it an issue. Another object of the present invention is to provide a driving IC suitable for such an optical print head.
One.

[0008]

According to a first aspect of the present invention, there is provided a driving IC comprising: a plurality of output terminals for driving an element; a first driving section connected to each of the output terminals; A driving IC including a plurality of group selection terminals for selecting a group (m) and a second driving unit connected to each of the group selection terminals
, Wherein a plurality of sets of the same terminal section as a terminal section formed by terminals for selecting the plurality of groups are provided.

According to a second aspect of the present invention, in the driving IC according to the first aspect, the output terminal and the group selection terminal are arranged on the same side of the driving IC. , Terminal portions of the group selection terminals are dispersedly arranged.

According to a third aspect of the present invention, there is provided a driving IC according to the first or second aspect.
The second drive section is constituted by a plurality of sets of circuits corresponding to the plurality of sets of terminal sections.

According to a fourth aspect of the present invention, there is provided a driving IC according to the first or second aspect, wherein the second driving unit is a common one of the plurality of sets of terminal units. It is characterized by comprising of three circuits.

According to a fifth aspect of the present invention, there is provided a light emitting device including a pad electrode corresponding to a plurality of terminals of the driving IC according to any one of the first to fourth aspects. Features.

According to a sixth aspect of the present invention, there is provided an optical print head including the driving IC according to any one of the first to fourth aspects.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit block diagram of a driving IC. FIG. 2 shows one of a plurality of output terminals DO1 to DO96 of the circuit block diagram shown in FIG.
FIG. 3 is a main part circuit block diagram mainly extracted from a part related to 1; First, a description will be given with reference to these drawings.

As shown in FIG. 1, the driving IC 1 includes an individual terminal portion composed of a plurality of (n) output terminals DO for driving an element (for an individual electrode 28 described later), and each output terminal DO.
And a first drive unit 2 for supplying a predetermined current output as a drive signal thereto and a plurality of (m) group selection terminals CD for selecting a plurality of groups (m). And a second drive unit 3 connected to each output terminal CD and selectively switching these to a predetermined power supply potential, for example, a ground potential VSS. Hereinafter, a case where n = 96, m = 4, and g = 3 will be described as an example, but the present invention is not limited to this.

The first drive unit 2 includes a data signal storage circuit 4 for temporarily storing serial input data signals sequentially applied through a plurality of (r) data input terminals SI1 to SI4.
A drive circuit 5 for outputting a drive signal to each of the output terminals DO1 to DO96 based on the data signal output from the data signal storage circuit 4, a current supply circuit 6 for supplying a constant current to the drive circuit 5, The first driving unit 2 and the second driving unit 2
A timing control circuit 7 for supplying a predetermined timing signal to each section of the drive section 3;

The data signal storage circuit 4 takes in data signals serially input from the data input terminals SI1 to SI4 in synchronization with the clock signal CLK1, and serially outputs n × m (38) from the data output terminals SO1 to SO4.
4) A multi-input shift register 8 having a bit structure, and an n × m (384) bit structure for taking in the data signals taken in the shift register 8 in units of n × m (384) bits in parallel based on the load signal LOAD1. And a latch circuit 9. The n × m (384) data signals output in parallel from the shift register 8 can be supplied to the storage circuit 10 without passing through the latch circuit 9.

When the data signal is composed of a plurality of bits, the configurations of the shift register 8 and the latch circuit 9 can be changed accordingly. For example, the shift register 8 can be replaced by a memory of an addressing system. It can also be configured.

The drive circuit 5 outputs n from the latch circuit 9.
A first selection circuit 11A for sequentially selecting and outputting data signals in units of n from × m (384) data signals;
N for outputting a constant current through the output terminals DO1 to DO96 based on the output of the first selection circuit 11A.
(96) The first drive circuit 12A having a bit configuration is provided as a basic configuration. The drive circuit 5 includes, in addition to the basic configuration, a correction data storage circuit 10 for storing n × m (384) pieces of correction data corresponding to data correction, as needed, and a correction data storage circuit A second selector circuit 11B for correction data for sequentially selecting and outputting correction data signals in units of n from the n × m (384) correction data signals output from the selector 10; A second drive circuit 12B for correcting an n (96) bit configuration that outputs an output of a current value increased or decreased based on the output of the circuit 11B as a drive signal via the output terminals DO1 to DO96 can be provided. .

The storage circuit 10 stores, for example, S × M (384) correction data composed of a plurality of (S) bits (for example, a 3-bit configuration) in correspondence with the data signal. It can be constituted by a latch circuit having a × n × m bit configuration. Writing of correction data to each correction data storage circuit 10 is performed based on n × m unit signals supplied in parallel from the shift register 8.

Writing to the correction data storage circuit 10 can be performed in advance. That is, the operation of storing each bit of the correction data via the shift register 8 with only the storage circuit 10 in the write state can be performed a plurality of times (S = 3).

The drive circuit 12, as shown in FIG.
One output terminal DO is configured to include four current amplifiers 12a to 12d, each having a different current output, and the same number of output amplifiers as the number of output terminals DO. Four current amplifiers 12 a to 1 to which current is supplied from the current supply circuit 6
2d, by individually controlling its operating state,
The total output current can be changed within a range of about 3 to 5 mA based on 4 mA.

The selection circuit 11 selects n × m data or correction data stored in the latch circuit 9 or the correction data storage circuit 10 in order to perform time-division driving in units of n, and performs m times It is a circuit for taking out and is constituted by a plurality of logic gate circuits. The opening and closing of the gate of the selection circuit 11 is controlled by a divided timing signal generation circuit 14 which forms a part of the timing control circuit 7.

This division timing signal generation circuit 14
Time-division timing (selection timing of the selection circuit)
Is a circuit for generating division timing signals (DIV1 to DIV4) based on external signals DIVSEL1 and DIVSEL2 which are one of the control signals supplied from outside so as to define
It can be configured by combining logic gate circuits.
As described above, since the divided timing generating circuit 14 generates four divided timing signals (DIV1 to DIV4) based on the small number of external signals DIVSEL1 and DIVSEL1, the number of control signal terminals connected to the outside is reduced. The size of the IC can be reduced, and the number of external wires such as wire bond wires can be reduced.

Next, referring to FIG. 2, one output terminal DO
The data flow will be described focusing on 1. The data for one IC (384 on / off data) stored in the latch circuit 9 is connected to the division timing signals DIV1 to DIV4 by sequentially switching the division timing signals DIV1 to DIV4 to the H level. As a result of opening only the AND gate circuit, data is selectively output during that time. In the example shown in FIG. 2, the first to fourth data inside one IC is sequentially used for driving the drive circuit 12. Similarly, the correction data of the 3-bit configuration stored in the correction data storage circuit 10 is similarly selected as a result of the set of three AND gate circuits being opened by sequentially switching the division timing signals DIV1 to DIV4 to the H level. Is output. The output of the correction data storage circuit 10 is supplied to the drive circuit 12, and operates the three current amplifiers 12b to 12d selectively.

Next, the second driving section 3 will be described. The second drive unit 3 includes a set of output terminals C
A circuit for selectively switching one of D1 to CD4 to a predetermined potential, in this example, a ground potential VSS. By providing a timing synchronized with the division timing signals DIV1 to DIV4 to the common drive circuit 32, The output state of the terminals CD1 to CD4 is switched. Each common drive circuit 32 has a one-to-one
And the same output terminal CD of each terminal section 31 is selected at the same time. Each common drive circuit 32 has divided timing signals DIV1 to DIV1.
4, the output terminals CD1 to CD4 may be switched using another signal synchronized with the selection timing of the selection circuit 11.

FIG. 3 is a plan view of an essential part showing an example of the optical print head 20 provided with the driving IC 1 described above. This optical print head 20 is made of an insulating long substrate 2.
A plurality of, for example, L = 20 light emitting elements 22 are arranged in a line on the light emitting element 1, and the driving ICs 1 are arranged in a line adjacent to one side of the light emitting element 22 so as to correspond to the light emitting elements 22 on a one-to-one basis. ing. In this example, the driving IC 1 is arranged on one side of the light emitting element 22. However, when the driving IC 1 is arranged on both sides of the light emitting element 22, the light emitting element 22 and the driving IC 1 have a one-to-two correspondence. Just arrange them. A wiring 23 is provided between the light emitting element 22 and the driving IC 1 to connect them. As the wiring 23, a direct connection structure using a wire bond wire such as a gold wire or an indirect connection structure using a wire bond wire with a relay pattern interposed therebetween can be used. A structure in which connection is made using an agent can also be used.

A plurality of signal and power supply wiring patterns 24 are formed on the substrate 21 so as to extend along the direction in which the light emitting elements 22 are arranged. A wiring 25 similar to the wiring 23 is provided between the driving IC 1 and the wiring pattern 24.
Is provided.

The light emitting element 22 has a plurality of (m × n)
= 384) light-emitting portions 26 are arranged in a line along the longitudinal direction at a density (resolution) of, for example, 1200 DPI (Dot / Inch). Each of the plurality of light emitting units 26 is formed independently so as to be able to be driven in a time-division manner, and is divided into a plurality of m groups so as to be able to be driven in a time-division manner in groups. In this example, the numbers indicating the arrangement order of the light emitting units 26 are 4 such that the first, fifth, and ninth light emitting units 26 are in a first group, and the second, sixth, and tenth light units are in a second group.
4 illustrates a case where the data is divided into four groups based on the number of remainders when divided by.

The light emitting element 22 includes a common electrode 27-1 commonly connected to the light emitting units 26 belonging to the first group, and a common electrode 2 commonly connected to the light emitting units 26 belonging to the second group.
7-2, a common electrode 27-3, and a common electrode 27-4, four (M = 4) common electrodes 27 are provided along the longitudinal direction of the light emitting element, and the light emitting units 26 belonging to different groups are provided.
In this example, 96 (N = 96) individual electrodes 28 connected to four adjacent light emitting units 26 are arranged in the same direction.

As shown in FIG. 3, the driving IC 1 has a plurality of output terminals DO and a plurality of output terminals CD on a side facing the light emitting element 22. The output terminals CD are arranged such that terminal portions 31 each of which is a set of the output terminals CD1 to CD4 are dispersedly disposed at three positions at both ends and a central portion. The output terminal DO is
The output terminals DO are arranged between the terminal portions 31 in half. Each terminal section 31 has its output terminal CD1
CD4 is connected to common electrodes 27-1 to 27-4 of light emitting element 22.
Are connected using wire bond wires.

As described above, the output terminal CD of the driving IC 1
1 to CD4 and common electrodes 27-1 to 27- of the light emitting element 22
Since the connection between the four ICs is performed at a plurality of (g) locations, in this example, three locations, the current flowing through the driving IC 1 via the common electrode can be dispersed, in this example, three locations. Since the current is dispersed and the current value is reduced to about 1/3, the amount of voltage drop caused by the internal resistance of the driving IC, particularly, the internal resistance of the common drive circuit 32 can be reduced. The rate at which the voltage applied to the light emitting unit fluctuates with the fluctuation in the number of light emissions can be suppressed, and the fluctuation in the light emission amount can be suppressed. Further, by reducing the wiring distance of the common electrode 27 inside the light emitting element 22 to reduce the wiring resistance, the common electrode 2
7 can be suppressed from decreasing according to the distance from the wire bond point to the wire bonding point 7. Therefore, it is possible to provide an optical print head in which the light quantity fluctuation is suppressed.

An example of the circuit configuration of the optical print head according to this embodiment is as shown in FIG. 4, but other circuit configurations may be used.

Next, an embodiment in which the aforementioned basic embodiment is slightly modified will be described with reference to FIGS. FIGS. 5 to 7 are plan views of essential parts (the driving IC 1 and the light emitting element 22) necessary for explaining the difference from the basic embodiment shown in FIG.

First, FIG. 5 shows an embodiment which is substantially the same as the embodiment shown in FIG. 3 except that the structure of the light emitting element 22 is partially different. As shown in FIG.
As 2, a pad in which a pad electrode 27WB for wire bonding to a common electrode 27 (not shown) and an individual electrode 28 are arranged in a line is used. Here, the common electrode is the light emitting element 22
May be arranged separately from the pad electrode 27WB on the surface of the device, or may be arranged inside the element by forming a multilayer wiring. Then, a pad electrode portion is configured by setting four pad electrodes 27WB connected to the four common electrodes as one set,
This pad electrode portion is arranged to face the terminal portion 31 of the driving IC1. As described above, since the pad electrodes 27WB are arranged in one-to-one correspondence with the output terminals CD1 to CD4 of the driving IC 1, the wire bonding operation to the individual electrode 28 and the wire bonding operation to the common electrode are performed by the same device. Can be performed at the same time, and the assembling workability can be improved.

Although not shown in FIG. 3, the common drive circuit 32 of the driving IC has a structure as shown in FIG.
The driving ICs are distributed and arranged at both ends and the center of the driving IC corresponding to the arrangement of the terminal portions 31. In addition, the drive circuits 12 of the drive IC 1 are dispersedly arranged between the common drive circuits 32. As described above, since the common drive circuits 32 which are the main heat sources of the driving IC 1 are dispersedly arranged, the influence of the heat generated on the drive circuit 12 can be reduced. The drive circuit 12 is affected by variations in operation due to thermal unevenness (variation in drive current) and variations in operation due to stress generated between the substrate 21 and the drive IC due to thermal expansion (variation in drive current). It is suppressed by the above configuration.

As shown in FIG. 6, in addition to the configuration shown in FIG. 5, the driving IC 1 includes a terminal 31 and a common drive circuit 3.
2 may be arranged at both ends of the IC. In this case, the arrangement of the pad electrodes 27WB of the light emitting element 22 is also changed in accordance with the change in the arrangement of the terminal portions 32 of the IC. By doing so, the same effect as the embodiment shown in FIG. 5 can be obtained.

FIG. 7 shows an embodiment in which only the terminals 31 are dispersed. A block diagram of the driving IC 1 according to this embodiment is as shown in FIG. As shown in these drawings, this embodiment shows an example in which a common drive circuit 32 is commonly connected to a plurality of terminal portions 31. Here, since the driving IC 1 has the common drive circuit 32 disposed at the central portion in the longitudinal direction of the driving IC 1, the internal wiring length is reduced to about half as compared with the case where the driving IC 1 is disposed at one end of the driving IC 1. And the variation in the amount of light due to the internal wiring resistance can be reduced.

Since the number of the light emitting elements 22 is L (20), the number of the light emitting portions 26 of the entire head 20 is L × M × N.
= 20 × 4 × 96 = 7680.

Next, the operation of the optical print head 20 including the operation of the driving IC 1 will be briefly described below. The correction data to be stored in the storage circuit 10 is
In order to make the light amount of each light emitting unit 26 of the light emitting element 22 uniform, light amount correction data obtained in advance for each light emitting unit 26 is used, and these data are stored in the storage circuit 10. And

Data signals (7680) are sequentially supplied to the data input terminals SI1 to SI4 of the twentieth driving IC1 in r units, and the data signals are sequentially supplied in synchronization with the clock signal CLK1 to the multi-input shift register of each driving IC1. 8. Here, the data signals supplied to the data input terminals SI1 to SI4 are applied to the input terminal SI1 at 1, 5, 9
The second data and the second and sixth data are input to the input terminal SI2 in advance in a form corresponding to four groups of light emitting elements. One driving IC 1
Is completed, the data signal is supplied to the shift register 8 of the driving IC 1 located next via the output terminals SO1 to SO4. in this way,
Since multiple data signals are input, the data input time can be significantly reduced as compared with the case of one input.

When the data input for one line is completed, the load signal LOAD1 is held at the H level for a predetermined time,
The capture of n × m data signals held in the shift register 8 of each IC 1 is performed. At this time, the load signal L
Since the latch circuit 9 is selected (latched) at the time of the fall of OAD1, nx
The m data signals are simultaneously input to the latch circuit 9 and stored.

Immediately after the load signal LOAD1 switches from the H level to the L level, the external signals DIVSEL1,
2 are held at the L level, and only the division timing signal DIV1 output from the division timing generation circuit 14 is at the L level.
The level switches to the H level. Immediately after that, the external strobe signal (inverted STB) indicating the light emission timing becomes H level.
The level is maintained at the L level for a predetermined period from the level, and the light emitting element selectively emits light.

By changing the combination of the external signals DIVSEL1 and DIVSEL2, the division timing signal DIV2
Only the H level can be switched to the H level.
Only IV3 and DIV4 can be switched to H level.

By the switching of the division timings DIV1 to DIV4, the position of the data signal which the selection circuit 11 selects and outputs from the latch circuit 9 or the storage circuit 10 is sequentially switched. For example, the first, fifth,..., 7677th data is selected by the division timing DIV1, and the second, sixth,.
The 78th data is selected.

These data (to which 3-bit correction data is added as necessary) are supplied to the drive circuit 12. The drive circuit 12 has four current amplifiers 12a to 12a based on the data signal and the correction data added thereto.
12d is selectively operated, and its output current is output to an output terminal D.
It is supplied to each individual electrode 28 of the light emitting element 22 via O.

The current corresponding to the data signal and the correction data can be supplied to the individual electrodes 28 of all the light emitting elements 22, but only one quarter of the light emitting portions 26 are grounded via the common electrode 27. In this example, every four light emitting units 2
Only 6 selectively emits light during the L-level period of the strobe signal (STB inverted). Here, as shown in FIG. 1, the second drive unit 3 includes the common drive circuit 32 corresponding to the plurality of terminal units 31 so that the common drive circuit 3
2 can be reduced, and unnecessary voltage drop due to internal resistance can be reduced. Further, since the second drive section 3 includes a plurality of sets of the terminal sections 31 and disposes them in a distributed manner, the wiring resistance inside the IC can be reduced. Similarly, since the light emitting element 22 has the pad electrode portions dispersedly arranged at a plurality of locations, the wiring path and the resistance inside the light emitting element can be reduced.

As described above, one line of light is selectively emitted by time-division driving by switching of quarters, and by repeating this sequentially, exposure for one screen can be performed.

As described above, each of the driving ICs 1 for driving the light emitting element 22 corresponding to the in-element time-division driving incorporates the second driving section 3 which operates in synchronization with the timing in units of groups. Since the driving light emitting element 22 is driven in a time-division manner by the driving IC 1, the load can be distributed. Therefore, the maximum load applied to the second driving unit 3 for performing the time division driving can be determined based on the number of the light emitting units 26 belonging to one group of the corresponding light emitting elements 22. As a result, as compared with the case where a dedicated IC for time division driving (for selecting a common electrode) is used for the time division driving for all the light emitting elements as in the conventional dynamic driving method, the time division driving for the time division driving is performed. The load applied to the circuit can be significantly reduced.

The second driving unit 3 of the driving IC 1
The driving IC 1 can be constituted by a small circuit capable of controlling a small current, and the driving IC 1 is a conventional static type IC.
Therefore, the overall circuit configuration can be reduced in size.

In addition, although a time-division driving configuration is used, a data signal for one line can be input in a single processing operation, so that the data signal is repeated as many times as the number of divisions performed in the conventional circuit. The process of inputting a data signal becomes unnecessary. In particular, since the number of groups (m) and the number of data input terminals (r) are set to be the same, data can be input in advance by sorting data in units of groups.
Data input processing and the like can be easily executed. Further, even if the number of time divisions is increased, the timing for the time division (division timing signal) is generated using the supply lines of the control signals smaller than the number of divisions.
The number of IC terminals and the number of assembly operations can be reduced.

[0052]

As described above, according to the present invention, it is possible to reduce the difference in luminance between light emitting parts. Therefore,
An optical print head that suppresses printing unevenness can be provided. Further, it is possible to provide a driving IC and a light emitting element suitable for such an optical print head. Further, a versatile driving IC suitable for driving a light-emitting element corresponding to time-division driving can be provided. Further, the workability of assembling the optical print head can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a driving IC according to a basic embodiment of the present invention.

FIG. 2 is a circuit block diagram showing a main part of FIG.

FIG. 3 is a plan view of a main part of an optical print head according to a basic embodiment of the present invention.

FIG. 4 is a circuit block diagram of the optical print head of the embodiment.

FIG. 5 is a plan view of a main part of another embodiment.

FIG. 6 is a plan view of a main part of another embodiment.

FIG. 7 is a plan view of a main part of another embodiment.

FIG. 8 is a circuit block diagram of a driving IC according to another embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Driving IC 2 1st drive part 3 2nd drive part 4 Data signal storage circuit 5 Drive circuit 11 Selection circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C162 AE28 AF20 AF35 AF59 AH83 FA04 FA17 5F041 AA05 BB06 BB13 CB22 CB32 FF13

Claims (6)

[Claims] 1. A plurality of output terminals for driving an element, a first drive unit connected to each output terminal, a plurality of group selection terminals for selecting a plurality of groups (m), and each group In a driving IC including a second driving unit connected to a selection terminal, a plurality of sets of the same terminal unit as a terminal unit including terminals for selecting the plurality of groups are provided. Drive I
C. 2. The terminal according to claim 1, wherein said output terminal and said group selection terminal are arranged on the same side of a driving IC, and terminal parts of said group selection terminal are arranged in a distributed manner. Driving IC. 3. The driving IC according to claim 1, wherein the second driving section is constituted by a plurality of sets of circuits corresponding to the plurality of sets of terminal sections. 4. The driving IC according to claim 1, wherein said second driving section is constituted by one circuit common to said plurality of sets of terminal sections. 5. A light-emitting device comprising a pad electrode portion corresponding to a plurality of terminal portions of the driving IC according to any one of claims 1 to 4. 6. An optical print head comprising the driving IC according to claim 1. Description: