JP2001111352A - Frequency converting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the leakage of a local oscillation signal from the input side of the local oscillation signal to the input side of a high frequency signal. SOLUTION: This frequency converting circuit is provided with an FET 2 for local oscillation and an FET 1 for high frequencies serially connected between a power source and ground. An impedance element 11 is connected between the source of the FET 2 for local oscillation and the drain of the FET 1 for high frequencies.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency conversion circuit for converting a received high-frequency signal into an intermediate frequency signal in a mobile communication device, a broadcast receiver, or the like, and in particular, a local oscillation signal leaking to a high-frequency signal input terminal. This is related to technology for preventing phenomena.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional frequency conversion circuit using a depletion mode field effect transistor (hereinafter referred to as an FET). In this circuit, a high-frequency signal for reception (hereinafter, referred to as an RF signal) input to an input terminal 12 is applied to the gate of the FET 1 via an impedance matching circuit 8, and the input terminal 13
Is applied to the gate of the FET 2 via the impedance matching circuit 7.

When both signals are input as described above, the FET
The frequency at which the sum of the RF signal and the LO signal is obtained from the drain of the FET 2 or R
A frequency that is the absolute value of the difference component between the F signal and the LO signal is obtained. This is used as an intermediate frequency signal (hereinafter, referred to as an IF signal), and the IF signal is output to the output terminal 14 via the impedance matching circuit 9 adapted to the desired intermediate frequency, thereby performing the frequency conversion function.

Reference numerals 5 and 6 denote resistors for applying gate bias voltages to the FETs 1 and 2, respectively. 3 is FET1
The self-bias resistor connected between the source of the FET 1 and the ground potential determines the drain current of the FETs 1 and 2 when there is no signal, together with the resistors 5 and 6. Reference numeral 4 denotes a high-frequency bypass capacitor connected between the source of the FET 1 and the ground potential. The high-frequency bypass capacitor is set to have a capacitance capable of maintaining a low impedance with respect to the ground at any frequency of the RF signal, the LO signal, and the IF signal. Reference numeral 10 denotes a choke coil for applying the power supply voltage VDD to the drain of the FET 2.

Although the FETs 1 and 2 are shown as independent elements in FIG. 3, one element of a dual gate FET may be used.

[0006]

However, in the frequency conversion circuit of FIG. 3, the gate-source capacitance (hereinafter, referred to as Cgs) and the gate-drain capacitance (hereinafter, Cgd) existing in the elements of the FETs 1 and 2 are shown. )
There was a path for leaking the LO signal applied to the gate of FET2 to the gate of FET1. If the LO signal leaks to the gate of the FET1, an unnecessary signal may be radiated from the receiving antenna as a receiver, which may hinder the design of the receiver.

Therefore, in such a case, a band-pass filter for passing only the frequency band component of the RF signal and blocking the frequency component of the LO signal is inserted into the input path of the RF signal. The use of a bandpass filter poses a problem in a device in which miniaturization is prioritized, such as a mobile phone terminal, because the component mounting area increases.

Another problem when the band-pass filter is inserted is that the LO signal and its harmonic components outside the pass band leaked to the gate of the FET 1 are reflected there without passing through the band-pass filter and again. There is a problem applied to the gate of FET1.

As described above, unnecessary signals other than RF signals are
When the voltage is applied to the gate of T1, the unnecessary signal is also subjected to an amplifying operation and a frequency conversion operation. As a result, the performance is deteriorated in the frequency conversion of the RF signal which should be performed. In this case, specifically, the noise figure increases and the distortion characteristics deteriorate.

As described above, in the conventional frequency conversion circuit, the LO signal leaks between the gates of the FET2 and the FET1 irrespective of the use of the band-pass filter, thereby deteriorating the performance of the receiver. I was

In the case where such a frequency conversion circuit is formed into an integrated circuit, an LO signal amplifying circuit is added to the inside of the integrated circuit. There is a problem that the isolation characteristics of the amplifier are offset by the gain of the LO signal amplifying circuit, and further deteriorated.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to improve the isolation characteristics between the gate of an FET to which an LO signal is applied and the gate of an FET to which an RF signal is applied. To provide a frequency conversion circuit.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device comprising first and second field-effect transistors, wherein a high-frequency signal is applied to a gate of the first field-effect transistor. Together with the bias circuit,
A local oscillation signal is applied to the gate of the second field-effect transistor and another bias circuit is connected, and the drain of the second field-effect transistor outputs an intermediate frequency signal together with the application of a DC power supply. The source of the first field-effect transistor is grounded at a high frequency, and an impedance element is connected between the drain of the first field-effect transistor and the source of the second field-effect transistor.

In a second aspect based on the first aspect, the impedance element is a resistance element.

In a third aspect based on the first aspect, the impedance element is a third field-effect transistor, and the source and the drain of the third field-effect transistor are connected to the drain of the first field-effect transistor. The second field effect transistor was connected to the source.

[0016]

FIG. 1 is a circuit diagram of a frequency conversion circuit according to one embodiment of the present invention. 1 is the RF signal F
ET, 2 are LO signal FETs, 3 is a bias resistor, 4 is a high frequency bypass capacitor, 5, 6 are bias resistors,
7, 8, and 9 are impedance matching circuits, 10 is a choke coil for applying power, 12 is an RF signal input terminal, 13 is an LO signal input terminal, 14 is an IF signal output terminal, and 15 is an IF signal output terminal.
Are power supply terminals, which are the same as those shown in FIG.

In this embodiment, the drain of the FET 1 and F
An impedance element 11 is connected between the source of ET2 and the source of ET2 to improve the isolation between the gates of both FETs 1 and 2. The details will be described below.

FIG. 2 shows the connection relationship between the FETs 1 and 2 and the impedance element 11 by an equivalent circuit at the time of a small signal. In FIG. 2, G1, S1, and D1 correspond to the gate, source, and drain of the FET 1 in FIG. 1, respectively. Similarly, G2, S2, and D2 are F in FIG.
This corresponds to the gate, source, and drain of ET2. Cgd
1 and Cgd2 are the gate-drain capacitances of FETs 1 and 2, respectively, and Cgsl and Cgs2 are the gate and drain of FETs 1 and 2, respectively.
Source-to-source capacitances, Cdsl and Cds2 represent the drain-source capacitances of FETs 1 and 2, respectively, and Gdl and Gd2 represent the drain-source conductances of FETs 1 and 2, respectively. Zll is equivalent to the impedance element 11 shown in FIG.

The impedance Zds1 between D1 and S1 of the FET1 and the impedance Zgd1 between G1 and D1 are expressed by the following equations.
It can be represented by (1) and (2). In the following equation, the symbol “//” represents the parallel connection calculation of the preceding and following terms. Zds1 = (1 / Gd1) // (1 / jωCds1) (1) Zgd1 = 1 / jωCgd1 (2)

The impedance Zgs2 between G2 and S2 of the FET2 can be expressed by the following equation (3). Zgs2 = (1 / jωCgs2) // [(1 / jωCgd2) + {(1 / Gd2) // (1 / jωCds2)}] (3)

Here, if the voltage applied to G2 shown in FIG. 2 is Vlo and the voltage generated at G1 is Vrf,
The voltage ratio between lo and Vrf can be expressed by the following equation (4). Vrf / Vlo = Zds1 / (Zgs2 + Z11 + Zds1) (4)

Equation (4) means the isolation between the gates of the FETs 1 and 2 in FIG. 1. It can be seen that the addition of Z11 increases the ratio between Vrf and Vlo, that is, increases the isolation. .

Regarding the selection of the impedance value of Z11,
As compared with Zgs2, it is possible to further increase the isolation by increasing the value.

When the frequency conversion circuit shown in FIG. 1 is actually constructed and the isolation between the gates of the FETs 1 and 2 at a specific frequency is calculated, the RF signal frequency is 820 MHz, the LO
At a signal frequency of 690 MHz, the impedance element 1
In the conventional circuit where no 1 exists, the isolation was 22 dB at 690 MHz. By inserting a 200Ω resistor as Z11, the isolation was improved to 32 dB.

In the above-described embodiment, the impedance element 11 can be realized by using another FET by the internal resistance between the source and the drain. In this case, the resistance can be adjusted from outside. . Although the DC power supply VDD is supplied to the drain of the FET 2 via the choke coil 10, the power supply voltage is supplied to the drain of the FET 2 instead of using the inductor existing in the impedance matching circuit 9 without using the choke coil 10. Can also be supplied. Further, the frequency conversion circuit shown in FIG. 1 can be formed into an integrated circuit with all of the elements used, or can be formed into an integrated circuit with some elements as external elements.

[0026]

As described above, according to the present invention, the leakage of the local oscillation signal between the input of the local oscillation signal and the input of the high-frequency signal in the frequency conversion circuit can be improved with an increase in the number of elements. There is an advantage that a frequency conversion circuit suitable for the circuit can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a frequency conversion circuit according to one embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the circuit shown in FIG. 1 at the time of a small signal.

FIG. 3 is a circuit diagram of a conventional frequency conversion circuit.

[Explanation of symbols]

1: FET for high frequency signal, 2: FET for local oscillation signal,
3: Bias resistor, 4: High frequency bypass capacitor,
5, 6: bias resistor, 7, 8, 9: impedance matching circuit, 10: choke coil, 11: impedance element, 12: input terminal of high frequency signal, 13: input terminal of local oscillation signal, 14: input terminal of intermediate frequency signal Output terminal, 15:
Power supply terminal.

Claims (3)

[Claims] A first field-effect transistor, a high-frequency signal applied to a gate of the first field-effect transistor, a bias circuit connected to the first field-effect transistor, and a gate connected to the second field-effect transistor. The local oscillation signal is applied, and another bias circuit is connected.
The drain of the field effect transistor outputs an intermediate frequency signal together with the application of DC power, the source of the first field effect transistor is grounded at high frequency,
Wherein an impedance element is connected between the drain of the field-effect transistor and the source of the second field-effect transistor. 2. The frequency conversion circuit according to claim 1, wherein said impedance element is a resistance element. 3. The impedance element is a third field-effect transistor, and the source and drain of the third field-effect transistor are the same as the drain of the first field-effect transistor and the source of the second field-effect transistor. A frequency conversion circuit connected between the two.