JP2001111182A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent degradation in the electrical properties and reliability which are caused by locally narrowed wiring patterns, facilitate the arrangement design of the wiring patterns, reduce the consumption of etchant, reduce a time required for the disposal of effluents, and reduce the manufacturing cost. SOLUTION: The widths of conductor patterns 12a, 12b,... are partially widened so as to have the widths S of spacings 17 which separate the conductor patterns 12a, 12b,... from each other uniform.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, and more particularly, to a PGA (PGA) formed as a single wiring board or a multilayer wiring board obtained by laminating a plurality of such wiring boards.
The present invention relates to a wiring board which is incorporated in a communication device or the like as a BGA (Ball Grid Array) package.

[0002]

2. Description of the Related Art FIG. 5 is a plan view schematically showing a main part of a conventional wiring board of this type, and FIG. 6E is a sectional view taken along line AA in FIG. The insulating substrate 41 is formed in a substantially thin plate shape using a plastic material or the like, and a plurality of substantially bent conductor portions 43 having a width W are formed at predetermined positions on one main surface 41 a of the insulating substrate 41. ing. Land 44 to a predetermined location where the diameter has a substantially disk shape of D ₁ of the respective wire portion 43 is formed, the through hole 45 is extended from a substantially central portion having a substantially cylindrical shape passing through the insulating substrate 41 of the land 44 Has been established. The conductor pattern 42 includes the conductor 43 and the land 44. One end of the conductor pattern 42 is connected to the pad 46, respectively, while the other end of the conductor pattern 42 is led out of the insulating plate 41 as a lead for plating.

The conductor patterns 42 are separated from each other by a gap 47, and the width S of the gap 47 (the side end of one of the opposed conductor patterns 42 and the other conductor pattern 4)
Depends shortest distance) is disposed condition of the conductor pattern 42 between the second side _{edge, S 1, S 2, S} 3, ··· (S 1
<It is set to _{S 2 <S 3 <···)} . The lands 48 to the other main surface 41b side of the insulating substrate 41 in the through hole 45 bottom, the diameter was substantially disk shape of D ₂ (FIG. 6
(E)) is formed, and the land 48 is connected to a lower portion of the through hole 45. These insulating substrates 41,
The wiring board 40 includes the conductor pattern 42, the through hole 45, the gap 47, the land 48, and the like. In the wiring board 40 thus configured, a signal input to the land 48 is output to the pad 46 via the through hole 45 and the conductor pattern 42, while a signal input to the pad 46 is output to the conductor pattern 42, The signal is output to the land 48 via the through hole 45.

FIGS. 6A and 6B are schematic sectional views showing an example of a conventional method of manufacturing a wiring board (subtractive process) in the order of steps, wherein FIG. 6A shows a punching step, and FIGS. An etching resist forming step, (d) shows an etching step, and (e) shows a completed state after the etching resist removing step. First, a double-sided copper-clad laminate 50 in which a copper foil 51 is laminated on both main surfaces 41a and 41b of a plastic insulating substrate 41 is used. Is formed (a). This substrate is subjected to an electroless copper plating process, and electroless copper plating layers 53a and 53b are simultaneously formed on the surface of the copper foil 51 and the surface of the hole 52, respectively. Next, electrolytic copper plating is performed, and electrolytic copper plating layers 54a and 54b are simultaneously formed on the surfaces of the electroless copper plating layers 53a and 53b, respectively. Thereafter, a photosensitive dry film 55 is formed on the surface of the electrolytic copper plating layer 54a so as to cover the opening of the hole 52.
56 is attached (b). Next, light is applied to the photosensitive dry film 5 via two types (front and back) of masks (not shown).
After irradiating 5 and 56, respectively, a developing and rinsing process is performed to form etching resist films 55a, 55b,
56a is formed (c). Next, this is subjected to a wet etching process, so that the etching resist films 55a and 55
b, copper plating layers 54a, 53a not covered with 56a
Then, a portion of the copper foil 51 is dissolved and removed to form a void 47. Then, the etching resist film 55a and the insulating substrate 41
The conductive wire portion 43 including the copper plating portions 54c and 53c and the copper foil portion 51a is formed between them. A land 44 including the copper plating layer portions 54d and 53d and the copper foil portion 51b is formed between the etching resist film 55b and the insulating substrate 41, and between the etching resist film 56a and the insulating substrate 41. The copper plating layer portions 54e, 5
3e, a land 48 including the copper foil portion 51c is formed. In the hole 52, plating layers 53b, 54
A through-hole 45 including b and the like is formed (d). Thereafter, the etching resist films 55a, 55
When b and 56a are peeled off, a wiring board having a conductive wire portion 43, lands 44 and 48, through holes 45, and void portions 47 having a predetermined shape is formed on the insulating substrate 41 (e).

[0005]

FIG. 7 is a block diagram of FIG.
FIG. 2 is a schematic enlarged view showing a region in an enlarged manner, wherein a dashed line indicates a set position of the etching resist film, and a solid line indicates a conductor after the etching process. In the figure, 41 is an insulating substrate, 42 is a conductor pattern, 43 is a conductor, 44 is a land, 45 is a through hole, 47 is a gap, S is a gap 4
7 are respectively shown. In the above-described wiring board 40, as shown in FIG.
_.. , S ₂ , S ₃ ,...
It is over-etched compared to the shapes of 5a and 55b (FIG. 6), and the width thereof is likely to be reduced. As a result, the wiring board 40
There is a problem that a problem may arise in the electrical characteristics and reliability of the device. In addition, since there is a gap 47 having a relatively wide width S _{4 to} S ₇ , during the etching process, the copper plating layers 54 a, 53 a and the copper foil 51 not covered with the etching resist films 55 a, 55 b (FIG. 6C )) The amount of dissolution and removal of the part is large. As a result, there is a problem that the amount of the etching solution per the wiring substrate 40 is increased, and it takes time to remove impurities in the used etching solution, so that the waste liquid processing cost is easily increased. In addition, the conductor patterns 42 are regularly arranged, and if this arrangement is broken, there is a problem that the design may be troublesome.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and can prevent overetching of a conductor pattern and improve electrical characteristics and reliability without making the layout design of the conductor pattern difficult. It is an object of the present invention to provide a wiring substrate capable of reducing the amount of etching solution used and speeding up waste liquid treatment, and reducing the etching treatment cost and waste liquid treatment cost.

[0007]

Means for Solving the Problems and Their Effects
The etching rate of the copper plating layers 54a, 53a and the copper foil 51 (FIG. 6C) that are not covered with the etching resist films 55a, 55b is such that the width S of the gap 47 is small.
It is relatively slow because it is mainly controlled by the dissolution and diffusion rate of the plating component in the etching solution. On the other hand, the void 47
Is wide, the circulation state of the etching solution is good, the etching rate is high, and the etching is liable to be over-etched beyond the side walls of the portions covered with the etching resist films 55a and 55b. The present inventors have completed the present invention based on the above findings.

In order to achieve the above object, a wiring board (1) according to the present invention provides a wiring board having a plurality of conductor patterns formed on a main surface of an insulating substrate and a gap separating these conductor patterns. The substrate is characterized in that the width of the conductor pattern is set to be partially wide so that the width of the gap is made uniform. According to the above-mentioned wiring board (1), the width of the conductor pattern is set to be partially wide so that the width of the gap is made uniform.
The conductor pattern can be easily etched uniformly, and the width of the conductor pattern can be prevented from being locally reduced by over-etching, so that electrical characteristics and reliability can be improved. Further, since the etching removal amount can be reduced, the amount of the etching solution used can be reduced, and the waste liquid treatment can be facilitated. As a result, the manufacturing cost can be reduced.

A wiring board (2) according to the present invention is a wiring board comprising: a plurality of conductor patterns formed on a main surface of an insulating substrate; and a gap separating the conductor patterns. A feature is that a dummy pattern for uniforming the width is formed between the conductor patterns. According to the above-described wiring board (2), since the dummy pattern for uniforming the gap width is formed between the conductor patterns, the width of the conductor pattern is maintained at a predetermined value. The gap width can be made uniform, and the dummy pattern can be used as a ground, so that electrical characteristics and reliability can be further improved. In addition, the layout design of the conductor pattern can be facilitated, the amount of use of the etchant can be reduced, and the waste liquid treatment can be facilitated. As a result, the manufacturing cost can be further reduced.

The wiring board (3) according to the present invention is a wiring board comprising: a plurality of conductor patterns formed on a main surface of an insulating substrate; and a gap separating the conductor patterns. The width of the conductor pattern is set to be partially large so that the width is uniform, and a dummy pattern is formed between the conductor patterns. According to the above-described wiring board (3), the width of the conductor pattern is set to be partially large so that the width of the gap is uniform, and the dummy pattern is formed between the conductor patterns. Wiring board (2)
The same effect as described above can be obtained, and the electrical characteristics can be further improved by continuously setting the dummy patterns.

Further, in the wiring board (4) according to the present invention, in any of the wiring boards (1) to (3), the width ratio between the wide portion and the narrow portion of the void is set to 2 or less. It is characterized by having. According to the above-described wiring board (4), since the width dimension ratio between the wide portion and the narrow portion of the gap is set to 2 or less, it is possible to prevent the conductor pattern from being locally over-etched and thinned. It can be reliably prevented.

Further, in the wiring board (5) according to the present invention, in any of the wiring boards (1) to (3), the gap width is set in a range of 0.05 to 0.10 mm. It is characterized by: According to the above-mentioned wiring board (5), since the gap width is set in the range of 0.05 to 0.10 mm, it is ensured that the conductor pattern is locally overetched and thinned. In addition to this, it is possible to surely reduce the etching removal amount.

[0013]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an embodiment of a wiring board according to the present invention. Note that components having the same functions as those of the conventional example are denoted by the same reference numerals. FIG. 1 is a plan view schematically showing a main part of a wiring board according to the embodiment (1), and FIG. 2E is a sectional view taken along line AA in FIG. As shown in FIGS. 5 and 6, the insulating substrate 41 is formed in a substantially thin plate shape using a plastic material, and a predetermined width W or a predetermined width W is formed at a predetermined position on one main surface 41a of the insulating substrate 41. Conducting wire portions 13a, 13b having a substantially wider band width than
・ A plurality of are formed. As shown by a chain line, the conductor portion 13a, 13b, at a predetermined location within ... it is formed lands 14 which diameter has a substantially disk shape of D _1,
A substantially cylindrical through hole 15 penetrating the insulating substrate 41 extends from a substantially central portion of the land 14. The conductor patterns 12a, 12b,... Include these conductor portions 13a, 13b,. Similar to the one shown in FIG.
Are connected to the pads 46, respectively, while the other ends of the conductor patterns 12a, 12b,... Are led out of the insulating plate 41 as lead wires for plating.

The conductor patterns 12a, 12b,... Are separated from each other via a gap 17, and the width S of the gap 17 is set within a range of 0.05 to 0.10 mm. The dimensional ratio between the wide part and the narrow part is set to 2 or less. The other principal surface 41b side of the insulating substrate 41 in the through hole 15 bottom is formed with a land 18 having a diameter and a generally circular disk shape D ₂ (FIG. 2 (e)), the land 18 is a through hole 15 is connected to the lower part. These insulating substrate 41, conductor patterns 12a, 1
2b,..., The through-hole 15, the gap 17, the land 18, and the like constitute the wiring board 10. In the wiring board 10 configured as described above, the signal input to the land 18 is transmitted to the through hole 15, the conductor pattern 12 a,
2b,... Are output to the pad 46 side, while the signal input to the pad 46 is
, 12b,..., are output to the lands 18 via the through holes 15.

FIG. 2 is a schematic sectional view showing an example (subtractive process) of a method of manufacturing a wiring board according to the embodiment (1) in the order of steps.
(B) and (c) show a plating and etching resist forming step, (d) shows an etching step, and (e) shows a completed state after the etching resist removing step. First, a double-sided copper-clad laminate 20 in which a copper foil 21 is laminated on both main surfaces 41a and 41b of an insulating substrate 41 made of plastic is used in substantially the same manner as shown in FIG. A hole 52 having a predetermined shape is formed by using (a). Similar to the case shown in FIG. 6, the substrate is subjected to an electroless copper plating process, and the electroless copper plating layers 23a and 23b are simultaneously formed on the surface of the copper foil 21 and the surface in the hole 52, respectively. Next, electrolytic copper plating is performed to form electrolytic copper plating layers 24a and 24b on the surfaces of the electroless copper plating layers 23a and 23b, respectively. After this, the hole 52
The photosensitive dry films 25 and 26 are attached to the surface of the electrolytic copper plating layer 24a so as to cover the openings (b) (b).

Next, two types newly designed and manufactured (for front and back)
After irradiating the photosensitive dry films 25 and 26 with light through masks (not shown), the photosensitive dry films 25 and 26 are subjected to development and rinsing treatments, so that etching resist films 25a to 25
c, 26a are formed. Then, the gap between the etching resist films 25a to 25c is set to S (c).
Next, this is subjected to a wet etching process, and portions of the copper plating layers 24a, 23a and the copper foil 21 which are not covered with the etching resist films 25a to 25c, 26a are dissolved and removed to form the voids 17. At this time, any of an immersion type, a spray type, and a jet type is used as the etching device. Then, the etching resist film 25 is formed.
a between the copper plating layer portions 24 c and 23
c, the conductive wire portion 13a including the copper foil portion 21a is formed, and the copper plating layer portions 24d and 23d, the copper foil portion 2 are provided between the etching resist film 25b and the insulating substrate 41.
The conductor portion 13b including 1b is formed. Further, a land 14 including the copper plating layers 24e and 23e and the copper foil 21c is formed between the etching resist film 25c and the insulating substrate 41, and between the etching resist film 26a and the insulating substrate 41. Copper plating layer 2
A land 18 including 4f, 23f and the copper foil portion 21d is formed. In the hole 52, the plating layer 23 is formed.
Through holes 15 including b, 24b and the like are formed (d). After this, the etching resist film 25a
, 25a and 26a are peeled off, and the conductors 13a, 13b,...
8, a wiring board having through holes 15 and voids 17 is formed (e).

As apparent from the above description, in the wiring board 10 according to the embodiment (1), the widths of the conductor patterns 12a, 12b,. The conductor pattern 12
are easy to be uniformly etched, and the conductor patterns 12a, 12b,.
..The width of the area can be prevented from becoming thin locally,
Electrical characteristics and reliability can be improved. Further, since the etching removal amount can be reduced, the amount of the etching solution used can be reduced, and the waste liquid treatment can be facilitated. As a result, the manufacturing cost can be reduced.

Since the dimensional ratio between the wide portion and the narrow portion of the gap 17 is set to 2 or less, the conductor patterns 12a, 12b,... Can be reliably prevented.

The width of the gap 17 is 0.05 to 0.1.
0 mm, the conductor pattern 1
.. Can be reliably prevented from being locally over-etched and thinned, and the etching removal amount can be surely reduced.

FIG. 3 is a plan view schematically showing a main part of a wiring board according to the embodiment (2). In the same manner as shown in FIG. 5, reference numeral 41 denotes an insulating substrate, and reference numeral 42 denotes a conductor. Reference numeral 43 denotes a conductor, 44 denotes a land, 45 denotes a through hole, and 46 denotes a pad. Void 4 shown in FIG.
A dummy pattern 39 is formed in each of the elements 7, and a predetermined dummy pattern 39 is grounded. The dummy pattern 39 and the conductor pattern 42 are separated from each other via a gap 37, and the width S of the gap 37 is set in a range of 0.05 to 0.10 mm, and a portion having a large width S is set. The dimensional ratio between the and the narrow portion is set to 2 or less. Other structures and manufacturing methods are substantially the same as those shown in FIGS. 5 and 6, and therefore, detailed description of the structures and manufacturing methods is omitted here. These voids 37, dummy patterns 39, insulating substrate 41, conductor patterns 42, through holes 45, voids 4
The wiring board 30 is configured to include 7 and the like.

As is clear from the above description, in the wiring board 30 according to the embodiment (2), the dummy pattern 39 for making the width S of the gap 47 uniform is formed by the conductor pattern 4.
Since it is formed between the two, the width S of the void portion 47 can be made uniform while the width of the conductor pattern 42 is maintained at the predetermined value W, and the dummy pattern 39 can also be used as a ground. Thus, electrical characteristics and reliability can be further improved. Further, the layout design of the conductor pattern 42 can be facilitated, the amount of use of the etchant can be reduced, and the waste liquid treatment can be facilitated. As a result, the manufacturing cost can be further reduced.

Further, since the dimensional ratio between the wide portion and the narrow portion of the gap 37 is set to 2 or less, the conductor pattern 42 is reliably prevented from being locally over-etched and thinned. be able to.

The width of the gap 37 is 0.05 to 0.1.
0 mm, the conductor pattern 4
2 can be reliably prevented from being locally over-etched and thinned, and the etching removal amount can be reliably reduced.

FIG. 4 is a plan view schematically showing a main part of the wiring board according to the embodiment (3). In FIG.
Shows an insulating substrate substantially similar to that shown in FIG. At a predetermined location on one main surface 41a of the insulating substrate 41, a plurality of substantially streamline-shaped conductor portions 63 having a predetermined width W or a width wider than this are formed. As shown by the dashed line,
The predetermined portion of the conductor portion 63 is formed with a land 64 having a diameter and a generally circular disk shape D _1, the through hole 65 from a substantially central portion having a substantially cylindrical shape passing through the insulating substrate 41 of the land 64 Is extended. The conductor pattern 62 includes the conductor portion 63 and the land 64.
On the other hand, the dummy patterns 69 are continuously formed in a substantially elongated peninsula shape between the conductor patterns 62, and the ends of the dummy patterns 69 are guided to the outside of the insulating substrate 41,
All the dummy patterns 69 are grounded. The conductor patterns 62 are separated from each other, and the conductor pattern 62 and the dummy pattern 69 are separated from each other via a gap 67. The width S of the gap 67 is 0.05 to 0.1.
It is set within the range of 0 mm, and the dimensional ratio between the wide portion and the narrow portion of the width S is set to 2 or less. Other configurations and manufacturing methods are substantially the same as those shown in FIGS. 1 to 3, and thus detailed description of the configurations and manufacturing methods will be omitted. These insulating substrate 41, dummy pattern 69, conductor pattern 62, through hole 6
5, the wiring board 60 includes the void 67 and the like.

As is clear from the above description, in the wiring board 60 according to the embodiment (3), the width of the conductor pattern 62 is set to be partially wide so that the width S of the gap 67 is made uniform. In addition, since the dummy pattern 69 is formed between the conductor patterns 62, substantially the same effect as that of the wiring board (2) can be obtained, and the dummy pattern 69 can be obtained.
, The electrical characteristics can be further improved.

Further, since the dimensional ratio between the wide portion and the narrow portion of the gap 67 is set to 2 or less, the conductor pattern 62 is reliably prevented from being locally over-etched and thinned. be able to.

The width of the gap 67 is 0.05 to 0.1.
0 mm, the conductor pattern 6
2 can be reliably prevented from being locally over-etched and thinned, and the etching removal amount can be reliably reduced.

In the wiring boards 10, 30, and 60 according to the embodiments (1) to (3), the case where the insulating substrate 41 is made of plastic has been described, but the insulating substrate 41 is not limited to plastic. Instead, ceramics or the like may be used in another embodiment.

Further, in the wiring boards 10, 30, and 60 according to the embodiments (1) to (3), the case of manufacturing by the subtractive process has been described. However, the wiring board is not limited to the subtractive process. Instead, in another embodiment, it may be manufactured by, for example, a semi-additive process.

In the wiring substrates 10, 30, and 60 according to the embodiments (1) to (3), the etching resist film 2
When forming 5a to 25c, the photosensitive dry film 2
Although the case of using Nos. 5 and 26 has been described, in another embodiment, a resist paste may be pattern-printed.

In the wiring boards 10, 30, and 60 according to the embodiments (1) to (3), the lands 14, 44, and 64 are provided.
Although the case where the through holes 15, 45, 65 are formed has been described, the through holes 15, 45, 65 need not be formed.

In the wiring boards 10, 30, and 60 according to the embodiments (1) to (3), the conductor patterns 12a, 1
, 42, 62 are one main surface 41 of the insulating substrate 41
Although a case where the insulating substrate 41 is formed is described above, in another embodiment, the insulating substrate 41 may be formed also on the other main surface 41b side.

The wiring boards 10, 30, and 60 may be used not only as a single body but also as a multilayer wiring board by laminating a plurality of them. A pin or a solder ball is connected to a land 48 of the single or multilayer wiring board. PGA
It may be used as a package or a BGA package.

[Brief description of the drawings]

FIG. 1 is a plan view schematically showing an embodiment (1) of a wiring board according to the present invention.

FIG. 2 is a schematic cross-sectional view showing an example (subtractive process) of a method of manufacturing a wiring board according to Embodiment (1) in the order of steps, wherein (a) is a punching step, and (b) is plating. (C) shows an etching step, and (d) shows a completed state after the etching resist removing step (a cross-sectional view along line AA in FIG. 1).

FIG. 3 is a plan view schematically showing a main part of a wiring board according to a second embodiment.

FIG. 4 is a plan view schematically showing a main part of a wiring board according to a third embodiment.

FIG. 5 is a plan view schematically showing a main part of a conventional wiring board.

6A and 6B are schematic cross-sectional views showing an example (subtractive process) of a conventional method of manufacturing a wiring board in the order of steps, wherein FIG. 6A is a punching step, FIG. 6B is a plating and etching resist forming step, (C) shows an etching step,
(D) shows a completed state (cross-sectional view taken along line AA in FIG. 5) after the etching resist removing step.

7 is a schematic enlarged view showing a region B in FIG. 5 in an enlarged manner, wherein a dashed line indicates a set position of the etching resist film, and a solid line indicates a conductor after the etching process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Wiring board 12a, 12b, ... Conductor pattern 17 Void S S Void width 41 Insulating substrate 41a One principal surface

Claims (5)

[Claims] 1. In a wiring board having a plurality of conductor patterns formed on a main surface of an insulating substrate and a gap separating the conductor patterns, the conductor is formed such that the width of the gap is made uniform. A wiring board, wherein a pattern width is set to be partially wide. 2. In a wiring board having a plurality of conductor patterns formed on a main surface of an insulating substrate and a gap separating the conductor patterns, a dummy pattern for equalizing the width of the gap is provided. Is formed between the conductor patterns. 3. In a wiring board comprising a plurality of conductor patterns formed on a main surface of an insulating substrate and a gap separating the conductor patterns, the conductors are formed such that the width of the gap is made uniform. A wiring board, wherein a pattern width is partially widened and a dummy pattern is formed between the conductor patterns. 4. The wiring board according to claim 1, wherein a width dimension ratio between a wide portion and a narrow portion of the gap is set to 2 or less. 5. The gap width is 0.05 to 0.10 mm.
It is set in the range of, The claim 1 characterized by the above-mentioned.
5. The wiring board according to any one of the above items 4.