JP2001102940A - Address data generation circuit and method for multistage interleaving - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale and to downsize a device by reducing the memory capacity in an address data generation circuit for multistage interleaving. SOLUTION: Respective stages including a final stage, an intermediate stage, and a 1st stage each equipped with a holding circuit which holds an interleaving pattern as a minimum unit and arithmetic circuits for multiple stages find interleaving patterns sequentially in steps to find the address data of an interleaving pattern corresponding to desirable data to be addressed finally. The clocks of access circuits of the holding circuits which holds the interleaving patterns of the respective stages and respective arithmetic circuits are synchronized to generate the patterns without storing the arithmetic results of the respective stages in a storage means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-stage interleave (MIL) address data generating circuit and an address data generating method.

[0002] In the technology of wireless communication devices, multi-stage interleaving (MIL) is known.
g) and W-CDMA (Wideband-
CodeDivision Multiple Access (IP) systems are attracting attention. In such systems, the minimum interleaving pattern (pre-defined interleaving pattern: sometimes referred to as PIP) is changed to IP (interleaving pattern: I).
(Abbreviated as P) has been proposed.

[0003] It is desired to improve the generation of address data using such a W-CDMA MIL or turbo MIL.

[0004]

2. Description of the Related Art FIG. 18 is an explanatory diagram of a multi-stage interleave (MIL). MIL is adopted in W-CDMA (a standard proposed by ARIB (Effective Radio Utilization Promotion Center of the Association of Radio Industries and Businesses)), which is one of the standards for wireless communication devices. In this example, A. As shown in FIG. 7, this is a case of 16-bit data consisting of bit positions of 0, 1, 2,..., 15, and this data is arranged from the top row to the bottom row every 4 bits from the top. Thereby, B. of FIG. 16 = 4 (rows) × 4 (columns) as shown in
Is configured. This A. Are replaced by 2 × 2 block interleaving. That is, the column at each bit position of “0, 1, 2, 3” in the uppermost row is arranged in two rows of a row of “0, 1” and a row of “2, 3”. When read in the order of the first column and the next column, "0, 2, 1,
3 ”. Similar conversion is performed by B.S. Is performed for each row of D. Is obtained. This D. The rows of the second row are replaced with the third row.
When the line is replaced, The sequence as shown in FIG. This E. By reading the bits of the first column from the top of the array in the order from top to bottom, and then similarly reading out the bits in the order of the second to fourth columns, The interleaved data shown in FIG. Thus, multi-stage (multi-stage) interleaving is performed. This makes it possible to increase the discrete distance as compared with a simple block interleave.

FIG. 19 shows an interface for a data length of L bits.
3 shows a leave pattern tree. This is the final stage
(Final Stage) Z stage, one data size
Z N^ZBit PIP (minimum unit interleaved pattern)
) And another data size M^ZA bit of a PIP
, N^(Z-1)A bit IP is generated, and the next stage (Z-
Data size N^(Z-1)Bit IP and
Another data size M^{(Z-1 )}Generate IP with bit PIP
To achieve. Thus N¹Generate IP up to bits
N-bit IP and M in the first stage¹
Generates IP with data length L bits using bit IP
You.

The above operation is based on the following equation.

[0007] For N ^(Z-1) = N ^Z × M ^Z , A (i): the i-th element in the PIP list of N ^Z B (i): the i-th element in the PIP list of M ^Z (i): Defined as the i-th element in the created IP list of N ^(Z-1) , and C (i) is obtained by the following equation. Here, i% ^NZ represents a remainder when i is divided by ^NZ , and i / N ^Z represents a quotient when i is divided by ^NZ . If the result of this operation is equal to or greater than ^NZ-1 , the operation is canceled.

C (i) = ^MZ × A (i% ^Nz ) + B (i /
^{N Z) (i = 0 ~N} Z × M Z -1) Figure 20 shows the PIP list of MIL proposed as one idea of the W-CDMA system. An interleave pattern is determined for each index (PIP of the smallest unit) as shown in the figure.

FIG. 21 shows an MIL address generation pattern having a data length of L bits. This is an address data generation pattern for generating an interleave pattern used for mobile communication, and differs according to usage conditions of mobile communication.
That is, the type of physical channel (perch channel used for broadcast from the base station, the type of common physical channel that is a control channel in a cell that is a communication area, and the individual physical channel that transmits voice and data) and the transmission direction It depends on a certain link (Link), and furthermore, the symbol rate (ksps: kilo symbol per second, downlink 1
The symbol (corresponding to 2 bits) uniquely determines the number of data bits per frame; L (bits) MIL address data generation pattern (combination of PIPs).

[0010] In the case of a normal MIL, an encoder uses a convolutional encoder and a decoder uses a convolutional encoder.
Uses a Viterbi decoder. However, for data for which desired quality is desired to be kept good, a turbo code and a decoder are used while keeping the data length longer. MIL for turbo in it
Use In the case of turbo MIL, error detection and correction can be performed even when the data length is long, using a turbo encoder and a turbo decoder.

FIG. 22 is a pattern tree of the turbo MIL for the data bit length L.
An L-bit IP is obtained by an address data generation pattern combining the basic PIP called No. 7 and this pattern differs depending on the type of channel. That is, in the final stage (Final stage: Z = the number of final stages) of the branch 1 based on the pattern tree of the turbo MIL, a PIP of _one data size N ₁ ^Z bits and a PIP of another data size M ₁ ^Z are used. Generates an IP with
Data size N _{1 in the} next stage (Z-1 stage)
^An IP is generated from the ^Z-1 bit IP and another data size M ₁ ^Z-1 bit PIP. Note that the PIP pattern is stored in the ROM in advance and is obtained by reading it out. FIG. 23 shows the PIP used for the turbo MIL.

Thus, the IP is generated up to the first stage.
Similarly, in the processing of branches 2 to 7, the first state
Generating a total of seven types of IPs before processing₁ ¹,
M₇ ¹).

[0013] The formula for calculating the turbo MILIP is as follows:
l) From the stage to the second stage, the following formula is used.

C (i) = M · A (i% N) + B (i / N) (Equation 1) where M is the number of elements in column PIP, N is the number of elements in row IP (PIP), and A (i ) Is the ith element of row IP (PIP), B
(i) represents the i-th element of column IP (PIP), and C (i) represents the i-th element in the calculated upper stage row IP.

Similarly, in the first stage, the final IP is calculated according to the following equation.

C (i) = MAA (i% N) + _{Bi% N} (i / N) (Equation 2) where M is the number of elements in column IP, and N is the number of elements in row PIP (T7) ( = 7), A (i) is the ith element of row PIP (T7), Bi%
N (i) represents the i-th element in the column IP of the i% N-th branch, and C (i) represents the i-th element of the calculated final IP. The branch number is counted from 0.

FIG. 24 shows a 348-bit turbo MIL pattern tree and an address data generation pattern.
A. As shown in (3), a 348-bit IP pattern is obtained through three stages of a final stage, a second stage, and a first stage. FIG. Is an example of a 384-bit address data generation pattern of turbo MIL, and is a DCH (Dedicated Channel).
Used for channels. In the case of 348 bits, in the final stage and the second stage, the branch 1 generates a P10 address of "10" bits at T7 and [4 * 3], multiplies it by "5", and "50" Generate a PIP address pattern. In the second branch, an address pattern of “50” is generated by a combination of “8 * 7”, and similarly, in a third branch, an address pattern of “50” is generated by a combination of “5 * 11”.
B. The pattern shown in FIG.

Such a 348-bit turbo MILI
A specific example of the P calculation (up to the second stage) will be described below. This example is shown in FIG. In the example of the last stage of branch 1 in the 348-bit turbo MIL shown in FIG. 7, the values of the parameters are as follows.

M = 3, N = 4, A = {1,3,0,2}, B = {1,2,0} When the IP is calculated, a part thereof is as follows.

C (0) = 3 * A (0% 4) + B (0/4) = 3 * 1 + 1 = 4 C (1) = 3 * A (1% 4) + B (1/4) = 3 * 3 +1 = 10 C (2) = 3 * A (2% 4) + B (2/4) = 3 * 0 +1 = 1 C (3) = 3 * A (3% 4) + B (3/4) = 3 * 2 + 1 = 7 C (4) = 3 * A (4% 4) + B (4/4) = 3 * 1 + 2 = 5 C (5) = 3 * A (5% 4) + B (5 / 4) = 3 * 3 + 2 = 11 C (6) = 3 * A (6% 4) + B (6/4) = 3 * 0 + 2 = 2 C (7) = 3 * A (7% 4) + B ( 7/4) = 3 * 2 + 2 = 8 C (8) = 3 * A (8% 4) + B (8/4) = 3 * 1 + 0 = 3 C (9) = 3 * A (9% 4) + B (9/4) = 3 * 3 + 0 = 9 C (10) = 3 * A (10% 4) + B (10/4) = 3 * 0 + 0 = 0 C (11) = 3 * A (11% 4) + B (11/4) = 3 * 2 + 0 = 6 In the above, since IP is 10 bits, C (1) and C (5)
Is deleted. Therefore, the calculated IP is as follows.

C = {4,1,7,5,2,8,3,9,0,6} Next, a specific example of the first stage IP calculation in the 348-bit turbo MIL will be described. However, the parameters M, N, B0, B1, B2,... B6 are as follows.

[0022]

(Equation 1)

When IP is calculated, C (0), C (1), C (2)
・ C (16) ・ ・ becomes as follows,

[0024]

(Equation 2)

The final IP calculated as described above is as follows.

C = ｛220,50,250,113,317,187,43,205,7
8,283,139,334,150,0,...｝ A conventional memory configuration and an address updating method (part 1) for executing the above-described 348-bit turbo MILIP calculation specific example (up to the second stage) will be described with reference to FIG.

According to the specific example of the calculation up to the second stage, when the element A (i) in the row PIP makes one cycle, the column PIP
The element B (i) has been updated. As shown in the initial state of FIG. 25, each PIP element in the row and column has its address register placed at the head of each PIP address at the start of operation. In this example, the row PIP is addressed by the X0 register and the column PIP is addressed by the X1 register. From row PIP element to X0
The element indicated by the register is extracted, and X1 is obtained from the column PIP element.
The element indicated by the register is taken out, and 1 bit of IP is calculated. Each time the IP1 bit is calculated, the address (X0) of the row PIP is updated by one. IP is calculated sequentially, and FIG.
5 represents the state after the calculation of 3 bits, and the IP is calculated in the same manner. If the last element of the row PIP is used for the IP calculation, the row P is calculated as shown in FIG.
When the IP address returns to the top, one column PIP address is updated. Thus, the IP obtained at each stage
Are all calculated.

Looking at a specific example of the calculation up to the first stage, the elements A (i) of the row PIP are taken out from the head in order, and the column IP is used while moving the elements of each branch from the head in order. FIG. 26 shows a conventional memory configuration and an address updating method (part 2).

At the start of the operation of the first stage, an address register is arranged at the head of the row PIP and the column IP of the branch # 1 as shown in FIG. 26, and the row PIP is addressed by the X0 register and the column IP is addressed by the X1 register. . Row P
Extract the element indicated by the X0 register from the IP element,
The element indicated by the X1 register is extracted from the P element,
Calculate the bits. Each time IP1 bit is calculated, row I
The address (X0) of P is updated by one, and the address of column IP is moved to the next branch. The row PIP cyclically updates the address, and when the address of the row PIP returns to the top, moves the address of the row IP to the unused element at the top of the branch # 1. By repeating such operations, the calculated IP
Is the end result.

The configuration for generating the address data of the turbo MIL may be conventionally realized by hardware or may be realized by a program using a DSP (Digital Signal Processor), each of which will be described below.

FIG. 27 and FIG. 28 show hardware configurations (part 1) and (part 2) of conventional turbo MIL address data generation. In this example, a 348-bit turbo MIL is realized. A 7-ary ring counter indicating one branch, 81 is a final stage processing block, 82 is a second stage processing block, and 83 is a first stage processing block.

First, by inputting 12 clocks (MCLK10) as the final stage processing, 12-bit IP is generated by the 4-bit PIPROM and the 3-bit PIPROM, and the calculated value 10 or more is canceled. As a result, 10-bit address data is held in the 10-bit IPRAM. Address data for 10-bit data in the final stage processing is provided in the RAM (provided in the second stage processing block). Next, as the second stage branch 1 processing, 50-bit IP is generated by the 10-bit PIPRAM and the 5-bit PIPROM by inputting 50 clocks (MCLK1), and held in the 50-bit PIPRAM1. As the second stage branch 2 process, 56 clocks of the clock (MCLK2) are input, so that the 8-bit PIPRAM and 7
A 56-bit IP is generated with the bit PIPROM, and the calculated value of 50 or more is canceled. As a result, 50-bit IPRAM2 holds 50-bit address data. Thereafter, similarly, by inputting the respective clocks (MCLK3 to 7) to the branches 3 to 7 of the second stage, the 50-bit RAMs 3 to 7 hold the address data of 50 bits respectively.

Thereafter, as a process of the first stage, the clock (MCLK20) is input to the 7-ary ring counter, so that the clock (MCLK) is sequentially and cyclically input from Q1 to Q7 to the RAM1 to RAM7. As a result, 50-bit IP is output from each of the RAM1 to RAM7 and the 7-bit PIP output in synchronization with the clock (MCLK20), and the value and the 7-bit PIP output in synchronization with the clock (MCLK20) are output. And 348 bits of address data are output until 350 clocks (MCLK20) are output.

FIG. 29 shows a turbo MIL using a conventional DSP.
FIG. 30 shows a processing flow of address data generation.
3 shows a block configuration of P.

In FIG. 30, reference numeral 90 denotes a DSP core unit;
Reference numeral 1 denotes a control unit for performing overall control; 92, an address generation unit including address registers X0 to Xn; 93, a data operation unit; 94, a bus interface (I / F);
Reference numeral 5 denotes a ROM in which an interleave pattern (PIP) of each basic unit is stored; 96, a RAM in which operation result data (an address indicating the PIP and an interleave pattern (IP)) obtained by an intermediate operation are stored; A ROM in which a program for controlling the ROM 91 is stored;
A data register 98 temporarily holds data.

In this example, as in FIG. 27 and FIG.
This is an example of implementing a 48-bit turbo MIL. First, the processing of the IP calculation formula (1) for one stage of the final stage (Z = maximum) of the branch 1 (Y = 1) is performed (S1 to S3 in FIG. 29). The processing of this IP calculation formula (1) (S
Details of 3) are shown in FIG. 31. The address registers (X0 and X1) of the row PIP and column PIP are initialized (S30 in FIG. 31), the parameters of A and B are updated, and the IP of C is updated. The calculation of the calculation formula (S31), the determination and update of the address register, the check of the calculated length of C, and the like are performed, and the C that satisfies the condition is held in the memory (RAM) (S31).
32 to S35), the operation for each address is performed in order, and a predetermined number of IP operations are performed. When the processing of one stage is completed, the same processing is performed for the next stage (Z = Z-1), and the same processing is performed for the branch 1 to branch 6 in the first stage (S2 to S6 in FIG. 29).
7) is performed and when the branch 7 is reached, the first stage IP
The processing of the calculation formula (2) is performed.

The details of the processing of the first stage IP calculation formula (2) are shown in FIG. 32, in which the initial setting to the row PIP address register (X0 in the initial setting in FIG. 26) and the column IP
Initial setting to the address register is performed (S8 in FIG. 32).
0), A, B parameter setting and C by equation (2)
Is calculated (S81), and when C is equal to or smaller than the set value, the IP is output and a predetermined number of IPs are calculated.

As described above, the arithmetic processing up to the second stage of the branches 1 to 7 is performed using the two address registers X0 and X1, and the 50-bit IP up to the second stage of each branch is calculated. Are stored in the RAM. Next, as a process of the first stage, address registers X0 to X8
, The IP operation is sequentially performed from the 7-bit PIP and the 50-bit IP of each branch, and when the operation value is 348 or more, the operation is canceled and the operation processing with the IP of the next branch is performed. Is repeated 350 times,
Generate a 348-bit IP. This is the address data after interleaving. Each address data obtained corresponding to each data in this way is stored in the memory (R
AM), and data is written to that address. By reading the memory from the beginning, data according to the interleave pattern is generated.

[0039]

As described above, a hardware configuration for generating address data of a multi-stage interleave (MIL) circuit in a wireless device and a turbo MIL circuit used in a turbo encoder / decoder, and D
In the processing of the program by the SP, the calculation result is held for each stage, so that a large-capacity RAM is required. Specifically, a 348-bit turbo MIL
In the example of (1), a data holding RAM for 350 bits is required even if the data holding RAM in the final stage and the second stage processing is shared.

The increase in the circuit scale due to the increase in the RAM capacity is unavoidable, and the volume of the device is increased, so that the demand for the recent miniaturization of portable mobile terminal devices can be met. There was a problem that can not be.

According to the present invention, in the configuration of the MIL address data generation circuit in the wireless communication device and the address data generation of the turbo MIL circuit used in the turbo encoder / decoder, the circuit scale is reduced by reducing the memory capacity. It is intended to reduce the size of the device.

[0042]

FIG. 1 shows the principle configuration of the present invention, and particularly shows the principle configuration when the present invention is realized by hardware.

FIG. 1 shows address data of a predetermined number of bits (for example, 348 bits) of a multi-stage interleave in an example comprising three stages of a lowermost (final) stage, an intermediate (second) stage, and a first stage. This is an example of generating.

In FIG. 1, reference numeral 1 denotes a final (lowest) stage, 2 denotes a first branch unit 2-1, and a second branch unit 2-
2,..., An intermediate (second) stage having a configuration corresponding to each of the seven branches of the seventh branch unit 2-7, 3 is the first stage, and 4 is a predetermined number of branches (when the interleave bit is 348 bits). Is a branch counter for designating 7 branches), and 5 is an OR circuit. 10a and 10b of the lowermost stage 1 are counters for generating numerical values representing the addresses of different set rows and columns in response to clocks, and 11a and 11b are the counters 10a and 1b, respectively.
A holding circuit (indicated by a PIPROM) for holding an address of a corresponding PIP (minimum unit interleave pattern) using the count value of 0b as an address;
Numerals 0a and 20b denote counters for generating numerical values representing the set row and column addresses in accordance with the clock.
a and 21b are the counters 20 corresponding to each branch.
A holding circuit (indicated by PIPROM) that holds the address of the corresponding PIP using the values of a and 20b as addresses. A holding circuit (indicated by PIPROM) 30 for cyclically generating a predetermined number of address data assigned to the first stage 3 in accordance with the count value of a counter containing a clock input, 31 of the first stage 3; Is a plurality of branches (2-1 to 2-7) of the intermediate stage 2.
Is an adder for arithmetically adding the operation result from the first stage 3 and the output from the holding circuit in the first stage 3.

The counters 10a, 10 of each stage
b, 20a and 20b are counters 10a and 20b, respectively.
A predetermined number of clocks (not shown) in which a is set are cyclically counted, and the corresponding counters 10b and 20b count with output generated in each cycle. The counters 10a, 10b, 20a, and 20b can be replaced by address registers whose addresses are updated by clocks.

In the present invention, a counter (address register) is assigned to all the interleaving patterns (PIP) holding circuits of the minimum unit, and the addresses are held until an operation is output. All the PIPROMs are cyclically addressed, and the last ( Column PIPROM in stage 1
Is updated by one when the address of the row PIPROM returns to the head, and the address of the column PIPROM is updated when the counter becomes 0 in the intermediate stage (second stage 2). In each stage, only one IP is calculated and the value is held in the data register. Further, it grasps all the branch / stage numbers being processed and manages the transition to the next branch / stage. Thus, the processing from the final stage 1 to the first stage 3 can be performed by one routine, and only one bit of IP is required during the process. It can be reduced to only data registers.

In the final stage 1, the row and column P
The counters 10a and 10b are arranged (set) so as to represent the head element of the IP, and the address is updated cyclically by addressing the row PIP.
Is updated, and the column PIP is also cyclically addressed. Only one data is calculated at a time, and the result is held in a register. The IP of the upper stage is calculated using the IP, and the updated address register holds the state.

In the operation, when the branch 1 is first designated by the branch counter 4, the final stage 1 is driven, and outputs from the PIPROMs 11a and 11b are generated in accordance with the values of the counters 10a and 10b at that time. Then, a predetermined operation is performed on both outputs to generate an output of the first branch unit 2-1. This output is held in a data register not shown. At this time, intermediate stage 2
Is also driven, and the result obtained by adding its output and the output from the final stage 1 (output of the data register) is held in a data register (not shown) through the OR circuit 5, and The output is input to the first stage 3. In the first stage 3, the operation result (output of the data register) from the first branch unit 2-1 and the output from the PIPROM 30 in the first stage 3 are arithmetically added by an adder 31 to perform multistage interleaving. 1-bit address data is generated. Subsequently, a predetermined number of bits of address data of the first branch unit 2-1 are sequentially generated in synchronization with the clock.

The branch counter 4 includes a first branch unit 2-
When the clock of a predetermined number of bits corresponding to 1 is counted, an output for driving the second branch unit 2-2 is generated, and the second branch unit 2-2 of the intermediate stage 2 is driven. In the second branch unit 2-2, internal counters 20a and 20b sequentially count clocks sequentially in the same manner as the counters 10a and 10b, and generate addresses corresponding to the respective count values from the corresponding PIPROMs 21a and 21b. Then, a predetermined operation is performed on both outputs to generate an output of the second branch, which is held in a data register (not shown). The second of this intermediate stage 2
The output of the branch unit 2-2 is input to the first stage 3 through the OR circuit 5, and the PIPROM in the first stage 3
The output from 30 and the operation result from the second branch unit 2-2 are arithmetically added by an adder 31 to generate address data corresponding to a fixed number of bits set in the intermediate stage 2.

After the second branch section 2-2, the third branch section 2-3 to the seventh branch section 2-7 sequentially generate address data corresponding to the set number of interleave bits.

As described above, in the present invention, the processing in each stage is executed in synchronization with the clock cycle, and the data holding between the stages is reduced to one data in the data register, thereby drastically reducing the holding area. Can, memory (RAM)
Can be reduced. Also, when software processing is performed by a digital signal processor, the capacity of a memory (RAM) can be reduced according to the same principle.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 and FIG. 3 show configurations (part 1) and (part 2) of an embodiment using hardware. In this embodiment, the clocks are synchronized from the first stage to the last stage to reduce the need to store data in each branch and intermediate stage.

Reference numerals 1, 2, 3, 4, 5 in FIGS.
1 corresponds to each unit of the same reference numerals in FIG. 1 (names are partially different), 1 is a final (lowest) stage processing unit, and 2 is a first stage processing unit.
A second (intermediate) stage processing unit having a configuration corresponding to each of the seven branches of the branch unit 2-1, the second branch unit 2-2,..., The seventh branch unit 2-7, and the first stage processing unit 3 Reference numeral 4 denotes a 7-ary ring counter (corresponding to the branch counter in FIG. 1) for generating an output designating branch numbers 1 to 7, 5 denotes an OR circuit, and 6 denotes a control device for controlling the whole.

The counters 10a and 10b of the final stage processing unit 1 generate numerical values representing the addresses of the rows and columns for performing the four counts of 0 to 3 and the three counts of 0 to 2 according to the clock. 11a and 11b are 4-bit PIPROMs that output the addresses of the corresponding PIPs using the count values of the counters 10a and 10b as addresses.
And a 3-bit PIPROM, 12 is a multiplier for multiplying a fixed numerical value "3", 13 is an adder, and 14 is for canceling (not outputting) the calculated value if the calculated value is 10 or more.
This is a regulating circuit that issues a clock retransmission request to the forward ring counter 4 and outputs the value if the calculated value is 0 to 9.
In the first branch section 2-1 of the second stage processing section 2, reference numeral 20b denotes a counter for counting five counts from 0 to 4, 21b denotes a 5-bit PIPROM, 22 denotes a multiplier for multiplying "5", and 23 Is an adder. In the second branch unit 2-2 of the second stage processing unit 2, 20a,
20b is a row / column counter for performing 8 counts of 0 to 7 and 7 counts of 0 to 6, respectively, 21a, 21
b is an 8-bit and 7-bit PIPROM, 22
Is a multiplier for multiplying "11", 23 is an adder, 24 is a regulating circuit which cancels the calculated value if it is 50 or more, makes a clock retransmission request to the 7-ary ring counter 4, and passes the clock in the case of 0-49. It is. Similarly, the third branch unit 2-3 to the seventh branch unit 2-7 of the second stage processing unit 2 include 20a, 20b, 21a, 21b,
Each of the circuits 22 to 24 is provided.

In the first stage processing unit 3, reference numeral 30 denotes a 7-bit PIP driven by a clock (indicated by MCLK).
ROM, 31 is an adder, 32 is a 7-bit PIPROM3
A multiplier 33 that multiplies the output of 0 by “50” cancels the output of the adder 31 if it is 348 or more,
In the case of 347, it is a regulating circuit that allows passage. Further, in the 7-ary ring counter 4, 40 is driven by the clock retransmission request signal to change the clock to the final stage processing unit 1,
A clock retransmitting unit for retransmitting to each unit of the second stage processing unit 2 and the first stage processing unit 3. The counter 10
a, 10b, 20a, and 20b can be replaced by an address register whose address is updated by a clock.

The operation of the embodiment shown in FIGS. 2 and 3 will be described.

The clock (MCLK) is supplied to the hex ring counter 4.
, Clocks are sequentially and cyclically output from the outputs Q to Q7 to the respective counters.
By inputting the first clock as the clock (MCLK), one clock is output from the output terminal Q1 to the counter 10a of the final stage processing unit 1.
The OM 11a and the 3-bit PIPROM 11b determine the first element of the 10-bit IP obtained in the final stage, and the value thereof is compared with the 5-bit PIPROM 21 of the second stage processing unit 2.
b and 50 obtained by the second stage processing unit 2 of branch 1
The first element of the bit IP is determined. Further, the first element of the 348-bit IP obtained by the first stage processing unit 3 is obtained by the operation of this value and the 7-bit PIPROM 30. that time,
If the value output from the operation result of the 4-bit PIPROM and the 3-bit PIPROM is 10 or more, the value is canceled, and the clock retransmitting unit 4 of the 7-bit ring counter 4
The retransmission request signal is output to 0. 7 received retransmission request signal
The ring counter 4 retransmits the clock from the output terminal Q1 to the branch 1.

Similarly, the operation result of 4-bit PIPROM 11a and 3-bit PIPROM 11b and 5-bit PIPR
If the result of the operation with the OM 21b is 50 bits or more, the value is cancelled, and a request signal is output to the clock retransmitting unit 40 of the seven ring counter 4.

If the value obtained by the first stage processing unit 3 is 348 or more, the value is canceled.

Next, by inputting the second clock as the clock (MCLK), the second branch unit 2-2 is reset to 0 from Q2.
, The first element of the 50-bit IP obtained in the second stage with two branches is obtained from the 8-bit PIPROM 21a and the 7-bit PIPROM 21b.
348-bit I by calculation with 7-bit PIPROM 30
The second element of P is determined. The 8-bit PIPROM 21a and the 7-bit PIPROM2 of the second stage processing unit 2
If the value output by the operation result of 1b is 50 or more, the value is canceled and a request signal is further output to the clock retransmitting unit 40 of the seven-ary ring counter 4. Upon receiving the request signal, the seven-ary ring counter 4 retransmits the clock from Q2 to the branch 2. Also, the first stage processing unit 3
If the value obtained in is equal to or greater than 348, the value is canceled.

Similarly, by inputting the third to seventh clocks of the clock (MCLK), the third to seventh elements of the 348-bit IP obtained by the first stage processing unit 3 are obtained.

By repeating the above operation, 434 clocks (MCLK) are input and 348 clocks are input.
Bit address data is output.

Next, an embodiment will be described by using software. An embodiment of this software is a DSP (Digital Signal Proccesser:
Signal processing device).

FIG. 4 shows a control block for the turbo MIL of the DSP. In FIG. 4, reference numeral 60 denotes a data holding unit composed of a ROM for holding tree structure data 60a corresponding to each bit length and PIP data 60b corresponding to each bit length.
1 is an interleave data length input unit, 62 is an acquired data selection unit, 63 is an operation control unit, 64 is an IP operation unit including each unit of 64a to 64d, 64a is a PIP address register update unit, and 64b is an IP operation number counter update unit. , 64c are processing stage / branch updating units, and 64d is a calculated IP deletion determining unit. Further, 65 is a storage unit including 65a to 65d, 65a is a storage unit for PIP data address, 65b is a storage unit for the IP operation counter, 65c is a storage unit for the stage / branch number during processing, 65d is tree structure data,
66 is an IP calculation result output unit. Note that the DSP is basically the same as the configuration shown in FIG.

FIG. 5 shows the interrelationship of the interleave operation control operation. FIG. 5 shows the interrelationship of each part of the control operation in the configuration shown in FIG. Is a memory (ROM), d is an IP operation of the DSP core, e is an operation of the DSP data register, f is an operation of the memory (RAM), and the operation control is described in the order of numbers 1) to 6) in FIG. I do. In FIG. 5, a solid line with an arrow indicates a data flow, and a dotted line indicates a control relationship.

1) First, an interleave data length is input from the interleave data length input unit 61 of FIG. 4 for initialization. When this input is input to the arithmetic control unit 63 via the acquired data selecting unit 62 in FIG. 4, the arithmetic control unit 63 determines a control parameter from the interleave length (b in FIG. 5).
That is, the tree structure is determined, and the initial setting of the necessary address register for the PIP, the IP counter of the second stage, and the counter of the branch number are performed. Each parameter is shown in FIG.
Is stored in each of the sections 65a to 65d in the storage section 65 of FIG.

2) Further, the arithmetic control unit 63 in FIG.
Determine the PIP required for the current process from the stage number,
When the data address of the memory (60 in FIG. 4) necessary for the IP operation is designated from the PIP address register, the element list of each PIP data is read from the corresponding memory (ROM) (c in FIG. 5), and the DSP data register Loaded into

3) At the same time as the IP calculation, the parameters such as the PIP address register and the PIP counter are updated. In addition, the stage to be processed next is specified in consideration of the OK / NG determination result of the IP operation.

4) The stage / stage number is designated by the arithmetic control unit 63, and the IP arithmetic unit 64 of the DSP core determines the input / output destination of the arithmetic expression and data (d in FIG. 5).

5) IP operation results up to the second stage (IP
The calculation progress) is held in the DSP data register (FIG. 5E). This IP operation result is used for the operation of the next stage.

6) Only the IP operation result of the first stage is written into the memory (RAM) (f in FIG. 5).

FIG. 6 is a processing flow of an embodiment of turbo MIL address data generation, which is executed by a DSP program, and the control operation shown by the block in FIG. 5 is realized by this processing flow.

First, each parameter is defined as follows.

Y: branch number X^Z _{Y (N)}: N PI of Z stage in branch Y
Address pointing to P element X^Z _{Y (M)}: M PI of Z stage in branch Y
Address indicating P element Stage (Y): number of stages of branch Y M^Z _Y, N^Z _Y: Row / column support of Z stage of branch Y
Is Cnt_{Y (z)}: Number of times of data output of Z stage of branch Y
Und L: Interleave data length In FIG. 6, first, initial value setting (S1 in FIG. 6) is performed.
Address of each PIP to the first DSP, each branch
(Y) The number of stages (Z = Stage (Y)) is set (see FIG. 6).
S2), the next stage (Z) being processed is the last of the branch
(Lowest) stage Stage (Y) is determined (S
3). In the case of the last stage, the row PIP
Load (from ROM to data register) process
= * (X^Z _{Y ( N)}), And the row PIP address register X
^Z _{Y (N)}To update. Further, a column PIP loading process is performed,
B = * (X^Z _{Y (M)}) Is calculated and IP calculation is performed. This IP
Equation 1 of the calculation is generalized as described above, and C = M^Z _Y
× A + B. Then, X of the above PIP address^Z
_{Y (N)}Is the head of the row PIP (S5 in FIG. 6),
If it is not the head, the process proceeds to S10, and if it is the head, the column PI
X of P address^Z _{Y (M)}Is updated (S6), and the process proceeds to S10.
Run. In S10, the stage number Z is decremented by 1 and
Set C.

In the above S3, if the final stage is not
In this case, a column PIP loading process is performed, and B = *
(X^Z _{Y (M)}) And output counter Cnt_{Y (Z)}Is updated,
The IP calculation is performed by the same equation 1 as in the above S4 (S4 in FIG. 6).
7). Next, the output counter Cnt_{Y (Z)}= 0
(S8 in FIG. 6), if not 0, the process proceeds to S10, where 0
In the case, X in the column PIP address register^Z _{Y (M)}Update
(S9), and the process of S10 is performed. Continue to S10
And the value of C, which is the operation result,
The value (L_Y ^Z)
Is determined (S11 in FIG. 6).
Return to S2 without using the result.
It is determined whether the stage number is Z = 1 (first stage) (FIG. 6)
S12). At this time, if Z is not 1, return to S7
If Z = 1, PIPT7 (PI of the first stage)
P) and B = * (X_T7) To set T7
Less register X _T7Was updated and FIG. 19 described above was explained.
The IP is calculated by the equation 2 (S13 in FIG. 6). Continued
Therefore, C is a value specified for the first stage (L¹)Than
It is determined whether it is small (S14 in FIG. 6).
Is updated to the next branch (Y) without using the value of
5) Return to S2, and output the value of C if smaller.
(S16). Then, the number of outputs of C is L¹Reach
It is determined whether or not the operation has been completed.
Is returned to, but the processing is terminated when it has been reached.

FIGS. 7 to 14 show a specific example of the generation of the address of the 348-bit turbo MIL, and are specific examples in which the processing flow shown in FIG. 6 is applied to the case of the 348-bit turbo MIL.

The configurations shown in FIGS. 7 to 14 include the branch 1
4-bit and 3-bit P of the final stage of (Branch♯1)
An IPROM (indicated simply as PIP in the figure, the same applies to other PIPs) is provided, and an address register X is provided for each.
0 and X1 are arranged (set) at the head of each element, a 5-bit PIPROM for the second stage of the branch 1 is provided with an address register X2, and a decimal counter for updating the address of the column PIP for the second stage. A data register for holding the result of the last stage is provided. Further first
T7 PIPROM is for address register X
15 are arranged. Also, an 8-bit PIPROM and a 7-bit PIPROM are provided for the branch 2, and address registers X3 and X4 are arranged respectively. The PIPROMs and address registers (X5 to X12) of the branches 3 to 6 are not shown, and the branch 7 is a 2-bit PIPROM and a 4-bit PIPR as shown in FIG.
OM are provided, and address registers X13, X
14 are arranged.

FIG. 7 shows an initial state of a specific example of address generation of a 348-bit turbo MIL.
Are set so that X0 to X15 point to the head of each element, and the decimal counter is initialized to zero. FIG. 8 shows the state of the IP operation of the final stage of the branch 1 in the specific example. The operation is started from the lower stage (final stage) of the branch 1 from the initial setting state of FIG. 7, and the first IP is a 4-bit PIPROM. "1" and 3 of
3 × 1 + 1 = 4 is output from “1” of the bit PIPROM, held in the data register, and represents a state where the address of the address register X0 of the row PIPROM is updated by one.

FIG. 9 shows the state of the IP operation in the second stage of the branch 1 of the specific example. The operation result obtained in FIG. 8 is held in the data register.
From element "0" of column PIPROM of the second stage
The value is held in the data register by the calculation of × 4 + 0 = 20. After performing the IP operation, the value of the decimal counter is updated by one.

Next, FIG. 10 shows the state of the IP operation of the first stage of the branch 1 of the specific example. When the processing of the second stage including the state of FIG.
IP is calculated using (T7) and the value “20” of the data register. The value "4" is extracted from T7, and when IP is calculated, C (0) = 50 × 4 + 20 = 220. Since this value becomes the first IP for performing interleaving, this value is held in a memory (RAM). Also, one address of T7 is updated.

Since the IP has been calculated from the branch 1, the operation is continued from the final (lowest) stage of the next branch 2 (Branch # 2). When the IP operation of the branch 2 is completed, the operation moves to the next branch 3. IP for each branch in the following order
Perform the operation.

FIG. 11 shows the state of the branch 7 in the specific example at the end of the IP operation. When the IP operation of the seventh bit (branch 7) of the 348-bit IP is completed, the address register and the decimal counter are in a state as shown in FIG. Since it is the last branch, it returns to the first branch (branch 1) and repeats the same operation.

FIG. 12 shows a case where the operation result of the last stage of the branch 1 in the specific example is discarded (NG).

After the state shown in FIG. 11, the operation returns to the first branch 1 and the IP operation is similarly performed.
From the OM value “3” and the 3-bit PIPROM value “1”, 3 × 3 + 1 = 10, but the output IP of the final (lowest) stage is 10 bits and the value range is 0-9. The data is discarded, and the stage IP is calculated again. When the IP calculation is completed, the calculated IP
The address register is updated irrespective of K / NG (in the case of the intermediate stage, the counter and the column PIP address are updated).

FIG. 13 shows a case where the operation result of the final stage of the branch 1 in the specific example is good (OK). The above IP
When the IP is recalculated following the discard of, the value of the 4-bit PIP is “0” and the value of the 3-bit PIP is “1”.
0 + 1 = 1, and this value is held in the data register.

FIG. 14 shows an IP calculation state of the second stage and the first stage of the branch 1 of the specific example. In this case, 8
205 is obtained as the IP of the bit.

A turbo encoder and turbo decoder for W-CDMA can be configured using the turbo address data generation circuit according to the present invention. FIGS. 15 and 16 show examples of the configuration.

FIG. 15 shows the configuration of a turbo encoder used for W-CDMA, and FIG. 16 shows the configuration of a turbo decoder used for W-CDMA.

In FIG. 15, 70 is a turbo interleaver, 71 is a first encoder (ENCODER1), 72 is a turbo MIL address data generation circuit, and 73 is a second encoder (ENCODER1).
CODER2). In FIG. 16, reference numeral 74 denotes a first decoder (DECODER1); 75, a turbo interleaver;
Is a second decoder (DECODER2), 77 is a turbo MIL address data generation circuit, and 78 is a turbo deinterleaver.

This turbo coder is an example of performing turbo coding with a coding rate of 1/3 and a code length of 3. For input data x (1 bit) to be coded, a ya bit output directly and a , The output yb bits encoded by the first encoder (ENCODE1) 71 and the interleaved data generated by the turbo interleaver 70 with the address generated by the turbo MIL address data generation circuit 72, ENCODER2) Output yc encoded by 73
A bit is generated, and three bits are generated for one bit input.

The turbo decoder shown in FIG.
This is an example of decoding turbo-coded data having a code length of 3 and a code length of 3. Three bits (ya, yb, yc) generated by the encoder shown in FIG. 15 are separated and supplied to each circuit. That is, ya, yb and the output of the turbo deinterleaver 78 are supplied to the first decoder 74, and the decoded output is interleaved by the turbo interleaver 75 in accordance with the address of the turbo MIL address data generation circuit 77, and Supplied to the decoder 76 together with the yc bits,
The decoded output is input to the turbo deinterleaver 78. The turbo deinterleaver 78 is deinterleaved (returned to the original order) with an address specified by the turbo MIL address data generation circuit 77, and the data x
(1 bit) is output.

FIG. 17 shows the configuration of an embodiment of the radio communication apparatus. The W-CDMA using the turbo encoder and the turbo decoder using the address data generation technique according to the present invention shown in FIGS. 1 shows an embodiment of a wireless communication device.

In FIG. 17, reference numeral 41 denotes an antenna (AN
T), a receiving unit 42 receives a signal from QPSK (4
A demodulator (DEM) 43 for performing despreading processing of phase phase modulation and RAKE (finger synthesizing processing for combining a plurality of signals generated by reflection from a building or the like), and 43 is a channel code / decoding unit (CH-CODEC unit). ) And 44 are a data separating / combining unit, 45 is a higher-level application unit, 46 is a modulator that spreads and modulates four-phase, and 47 is a transmitter.
The channel coding / decoding unit 43 includes a slot synthesizer 43a,
MIL decoder 43b, turbo decoder 43c, Viterbi decoder 43d, CRC checker 43e, MIL address data generation circuit 43f, CRC adder 43g, turbo encoder 43h, convolutional encoder 43i, MIL encoder 43
j, a slot decomposer 43k.

The received signal is demodulated into a baseband signal by a receiving section 41, despread and RAKE-combined by a demodulation (DEM) section, and input to a channel coding / decoding section 43. The data input to the channel encoder / decoder 43 synthesizes time slots in the channel by a slot synthesizer 43a.
It is deinterleaved by the MIL decoder 43b. At this time,
The MIL address data generation circuit 43f needs to generate MIL address data. If the bit length of the code unit is equal to or more than 320 bits / code unit, it is input to the turbo decoder 43c, where the MIL deinterleave process for turbo is performed. At that time, MIL for turbo
Must be generated. The turbo-decoded data is subjected to a CRC check, and is applied to the upper application unit 45 after data separation. The turbo decoder has the configuration shown in FIG.

The data from the upper application unit 45 is input to the channel encoding / decoding unit 43,
After the addition, if the data length of the code unit is 320 bits / code unit or more, it is input to the turbo encoder 43h,
The MIL interleave processing for turbo is performed therein. At that time, it is necessary to generate the address data of the turbo MIL. Further, the turbo-coded data is interleaved for a channel, decomposed by a slot decomposer 43k, and then subjected to a four-phase shift (Q
A PSK) spreader 46b and a four-phase phase shift (QPSK) modulator 46a respectively perform processing.
Modulated into a signal. At this time, MIL address data is generated. The turbo encoder 43h in FIG.
Is provided.

[0096]

By applying the present invention to the address data generation circuit of the MIL or turbo MIL,
Since it is not necessary to hold the operation result in each stage in the RAM, it is possible to significantly reduce the memory.

That is, in both the case where the present invention is realized by hardware and the case where the present invention is realized by software processing of a DSP, the processing from the final stage to the first stage can be performed by one routine, and the progress in the middle is IP1.
Since only the bits are required, the memory area conventionally required in large quantities can be reduced to only one word of memory or the data register of the DSP.

[Brief description of the drawings]

FIG. 1 is a diagram showing a principle configuration of the present invention.

FIG. 2 is a diagram illustrating a configuration (part 1) of an embodiment using hardware;

FIG. 3 is a diagram illustrating a configuration (part 2) of an embodiment using hardware;

FIG. 4 is a diagram showing a control block for turbo MIL of the DSP.

FIG. 5 is a diagram showing a mutual relationship between interleave operation control operations.

FIG. 6 is a diagram showing a processing flow of an embodiment of turbo MIL address data generation.

FIG. 7 is a diagram illustrating an initial state of a specific example of address generation of a 348-bit turbo MIL.

FIG. 8 is a diagram showing a state of an IP operation in a final stage of a branch 1 of the specific example.

FIG. 9 is a diagram showing a state of an IP operation in a second stage of branch 1 of the specific example.

FIG. 10 is a diagram showing a state of an IP operation in a first stage of a branch 1 of the specific example.

FIG. 11 is a diagram showing a state at the time of completion of an IP operation of a branch 7 of the specific example.

FIG. 12 is a diagram illustrating a case where the operation result of the final stage of branch 1 in the specific example is discarded (NG).

FIG. 13 is a diagram illustrating a case where the operation result of the final stage of branch 1 of the specific example is good (OK).

FIG. 14 is a diagram illustrating an IP calculation state of a second stage and a first stage of a branch 1 of a specific example.

FIG. 15 is a diagram illustrating a configuration of a turbo encoder used for W-CDMA.

FIG. 16 is a diagram illustrating a configuration of a turbo decoder used for W-CDMA.

FIG. 17 is a diagram illustrating a configuration of an embodiment of a wireless communication device.

FIG. 18 is an explanatory diagram of multi-stage interleaving (MIL).

FIG. 19 is a diagram showing an interleave pattern tree for a data length of L bits.

FIG. 20 is a diagram showing a PIP list of MIL proposed as a proposal of the W-CDMA system.

FIG. 21 is a diagram illustrating an MIL address generation pattern having a data length of L bits.

FIG. 22 is a diagram showing a pattern tree of a turbo MIL for a data bit length L.

FIG. 23 is a diagram showing a PIP used for a turbo MIL.

FIG. 24 is a diagram showing a pattern tree of a 348-bit turbo MIL and an address data generation pattern.

FIG. 25 is a diagram showing a conventional memory configuration and an address updating method (part 1).

FIG. 26 is a diagram showing a conventional memory configuration and an address updating method (2).

FIG. 27 is a diagram showing a hardware configuration (part 1) of conventional turbo MIL address data generation.

FIG. 28 is a diagram showing a hardware configuration (part 2) of conventional turbo MIL address data generation.

FIG. 29 is a diagram showing a processing flow of turbo MIL address data generation by a conventional DSP.

FIG. 30 is a diagram showing a block configuration of a DSP.

FIG. 31 is a diagram showing details of processing of an IP calculation equation (1).

FIG. 32 is a diagram showing details of the processing of the first stage IP calculation formula (2).

[Explanation of symbols]

 1 Last (lowest) stage 10a, 10b Counter 11a, 11b PIPROM 2 Intermediate stage 2-1 First branch 2-2 Second branch 2-7 Seventh branch 20a, 20b Counter 21a, 21b PIPROM 3 First Stage 30 PIPROM 31 adder 4 branch counter 5 OR circuit

Continued on the front page F term (reference) 5B001 AA04 AC05 AD06 AE04 5J065 AA03 AB01 AC02 AD04 AD10 AF03 AG06 AH06 AH17 5K022 EE01

Claims (4)

[Claims] 1. A multi-stage interleave address generation circuit, wherein each of a plurality of stages including a final stage, an intermediate stage and a first stage is provided with a holding circuit for holding an interleave pattern of a minimum unit. And a plurality of stages of arithmetic circuits for finally obtaining address data of an interleave pattern corresponding to the data to be addressed, and synchronizing the clocks of the access circuits of the holding circuit holding the interleave pattern of each stage with the clocks of the respective arithmetic circuits. A multi-stage interleave address data generation circuit, wherein an operation result at each stage is generated without being stored in storage means. 2. The method according to claim 1, wherein clocks of respective counters for driving a circuit for generating an interleave pattern of a minimum unit of the operation circuit of each stage are synchronized, and a cycle of one clock is changed from a last stage to a first stage. An address data generation circuit for multi-stage interleaving, wherein the address data generation circuit is larger than a processing delay of an arithmetic circuit. 3. The method according to claim 2, wherein when the calculation result in the final stage and the intermediate stage is larger than a predetermined value, the next value is calculated by retransmitting the clock immediately after that. Address data generation circuit for multi-stage interleaving. 4. A multi-stage interleaving address data generating method using a digital signal processor having a holding circuit for holding a minimum unit interleave pattern corresponding to a plurality of stages and a plurality of address registers, respectively, The interleave pattern of the minimum unit is sequentially interleaved and held from the head address, and the plurality of address registers are individually assigned to each of the holding circuits so as to address each of the holding circuits. A multistage interleaving address data generating method, which eliminates the necessity of holding the operation result in each stage in a memory by accessing each of said holding circuits.