JP4318980B2 - Encoding processing device and decoding processing device of radio communication device - Google Patents

Description

  The present invention relates to an encoding processing device and a decoding processing device of a wireless communication apparatus using W-CDMA (wideband code division multiple access).

  One of the techniques for speeding up the encoding / decoding process at the time of data transmission / reception in the conventional W-CDMA wireless communication apparatus is a rate matching / dematching process disclosed in Patent Document 1, for example. According to this technique, it is possible to determine a bit to be inserted (repetition) or deleted (puncture) for each data block obtained by dividing processing data into a plurality of pieces.

  A rate matching method for inserting or deleting bits so as to conform to a desired data transfer rate is specified in Subclause 4.2.7 of 3GPP TS25.212, which is one of the specifications of 3GPP (3rd Generation Partnership Project). ing. The rate matching pattern determination algorithm specified in Subclause 4.2.7.5 of 3GPP TS25.212 is sequentially applied to each serial input bit, thereby specifying whether or not each bit should be inserted or deleted. On the other hand, the technique disclosed in Patent Document 1 determines a bit to be inserted or deleted for each of a plurality of data blocks by an algorithm derived from the rate matching pattern determination algorithm. At the same time, the rate matching / dematching process is executed in parallel. Thereby, high-speed rate matching / dematching processing can be realized.

Japanese Patent Laid-Open No. 2002-199048

  The encoding process and the decoding process at the time of data transmission / reception in the W-CDMA wireless communication apparatus are required to be accelerated as the data transfer rate increases. Since the rate matching / dematching device disclosed in Patent Document 1 is configured as described above, the processing of only the rate matching / dematching unit can be speeded up, but the first interleaving / first matching is possible. Processing such as deinterleaving cannot be accelerated.

  The present invention has been made to solve the above-described problems, and a first object thereof is wireless communication that is compliant with W-CDMA and can further speed up encoding processing and decoding processing. An encoding processing device and a decoding processing device of the apparatus are obtained.

  The encoding processing device of the wireless communication device according to the present invention extracts the same number of bits as the number of a plurality of wireless frames created simultaneously from the data bit stream to be transmitted, and the same number of these bits as the number of the wireless frames. A parallel processing unit that regularly distributes to a plurality of columns, a parameter calculation unit that calculates basic parameters for rate matching, and a bit number in the data bitstream assigned to each bit distributed to the columns Based on the basic parameters, a repetition / deletion determination unit that determines bits to be repeated or deleted among the plurality of bits distributed to the column, and the data bitstream for each bit distributed to the column Cumulative to calculate the cumulative number of repeated / deleted bits, which is the total number of the previous bit to be repeated or deleted and the bit concerned Of the plurality of bits distributed to the column by the reverse / delete bit number calculation unit, the bit determined to be repeated or deleted by the repetition / deletion determination unit is repeated or deleted. And redistributing a plurality of bits into a plurality of columns based on the cumulative repetition / deletion bit number, replacing at least two bits of the plurality of columns obtained by the redistribution, and redistributing the plurality of bits. And a rate matching / first interleaving unit for storing the bits of the exchanged column in the plurality of radio frames, respectively.

In the present invention, the parallel processing unit extracts from the data bit stream to be transmitted the same number of bits as the number of a plurality of radio frames created at the same time, and rules these bits into a plurality of columns having the same number as the number of radio frames. To distribute. The parameter calculation unit calculates basic parameters e _ini , e _plus , and e _minus for rate matching. Furthermore, the repetition / deletion determination unit is configured to _execute a plurality of distributions distributed to the column based on the bit number m in the data bit stream assigned to each bit distributed to the column and the basic parameters e _ini , e _plus , e _minus . Determine which bits of the bits are to be repeated or deleted. Furthermore, the cumulative repetition / deletion bit number calculation unit calculates, for each bit distributed to the column, the cumulative repetition / deletion bit number D that is the total number of the preceding bits to be repeated or deleted in the data bitstream and the relevant bits. calculate. The rate matching / first interleaving unit repeats or deletes bits determined to be repeated or deleted by the repetition / deletion determination unit among a plurality of bits distributed to the columns by the parallel processing unit, and performs cumulative repetition. / Redistributed / replaced columns by redistributing a plurality of bits to a plurality of columns again based on the number D of deleted bits and replacing at least two bits of the plurality of columns obtained by the redistribution with each other Are stored in a plurality of radio frames. In this way, by redistributing a plurality of bits into a plurality of columns based on the cumulative repetition / deletion bit number D, the bit redistribution can be completed at a high speed, and the plurality of bits obtained by the redistribution can be obtained. The first interleaving is completed only by exchanging bits in at least two of the columns. Therefore, it is possible to complete the bit redistribution and the first interleaving at a higher speed than in the case of the bit redistribution and the first interleaving based on the bit itself obtained by the rate matching. In addition, since the parallel processing unit performs rate matching on the bits distributed or parallelized to a plurality of columns and performs the first interleaving by exchanging the columns, the first interleaving result corresponds to a plurality of radio frames. Therefore, it is not necessary to perform the radio frame division again. As described above, there is an effect that the encoding process can be further speeded up while complying with W-CDMA.

Hereinafter, various embodiments according to the present invention will be described.
Embodiment 1 FIG.
FIG. 1 is a diagram illustrating an outline of an encoding process when downlink data is transmitted in a wireless communication system using W-CDMA. In step ST10, a CRC (Cyclic Redundancy Check) code is added to the transport block transferred from the upper application. In step ST11, the transport block to which the CRC code is added is encoded by convolution encoding or turbo encoding processing. The encoded transport block, that is, the data block is subjected to bit repetition (repetition) or deletion (puncture) so as to obtain a desired data transfer rate in the rate matching process of step ST12. In step ST13, the rate-matched data block undergoes a first interleaving process, and a bit order rearrangement process is executed. The first interleaved data block is divided into radio frames having a time length of 10 ms in step ST14.

  In step ST15, transport channel multiplexing is performed. Here, radio frames of a plurality of transport channels are multiplexed. The multiplexed radio frame is subjected to the second interleaving process in step ST16, and is mapped to the physical channel in step ST17. The mapped data is spread and modulated by QPSK (quadri-phase shit keying) in step ST18, converted from a baseband signal to an RF (high frequency) signal in step ST19, and then transmitted from the antenna.

  FIG. 2 is a diagram illustrating an overview of a decoding process when uplink data is received in a wireless communication system based on W-CDMA. The RF signal received by the antenna is converted into a baseband signal in step ST20, and the baseband signal is despread by QPSK demodulation and decoded in step ST21. The decoded physical channel data is combined with the multiplexed radio frame of the transport channel in step ST22 and subjected to the second deinterleaving process in step ST23. Next, transport channel division is performed in step ST24. Here, the multiplexed radio frame is divided into radio frames of a plurality of transport channels.

  The radio frame of each transport channel is subjected to rate dematching processing in which bits are repeated or deleted in step ST25. The rate-dematched radio frames are combined in step ST26. Here, the transport block is assembled from the radio frame. The transport block is first deinterleaved in step ST27. The transport block subjected to the first deinterleaving process is decoded by Viterbi decoding or turbo decoding process in step ST28, and transferred to the upper application after CRC check in step ST29.

  A coding processing apparatus of a wireless communication apparatus according to Embodiment 1 of the present invention is provided in a base station of a wireless communication system using W-CDMA, and performs rate matching (step ST12) for downlink data transmission and first interleaving in FIG. (Step ST13) and radio frame division (step ST14). More specifically, when convolutional coding is performed in the previous stage, the first embodiment is applied regardless of whether bit repetition or bit deletion is used in rate matching, and turbo coding is performed in the previous stage. If so, the first embodiment is applied when bit repetition is used in rate matching. FIG. 3 is a functional block diagram showing the coding processing apparatus according to Embodiment 1 of the present invention. Illustration of other components of the wireless communication device is omitted.

As shown in FIG. 3, the encoding processing apparatus includes a parameter calculation unit 30, a parallelization processing unit 31, a D (= e _plus number) calculation unit (repetition / deletion determination unit) 32, an output position control unit (rate matching). First interleaving unit) 33, an initial position calculation unit 34, and a storage device 35 are provided. The parameter calculation unit 30 is actually a CPU (central processing unit) or a DSP (digital signal processor) of the wireless communication apparatus, and operates according to a program. The parallel processing unit 31, the D calculation unit 32, the output position control unit 33, and the initial position calculation unit 34 are each part of an FPGA (field programmable gate array) or LSI (large scale integration). The storage device 35 is a random access memory (RAM).

The parameter calculation unit 30 calculates e _ini , e _plus , and e _minus that are parameters necessary for the rate matching process. These parameters are specified in Subclause 4.2.7 of 3GPP TS25.212 described above, e _ini is an initial value of variable e of the rate matching pattern determination algorithm, e _plus is an increment of variable e, e _minus is a decrement of the variable e. The parameter calculation unit 30 calculates these parameters based on the data rate and the like in accordance with the same specification.

According to Subclause 4.2.7.5 of 3GPP TS25.212, the rate matching pattern determination algorithm using parameters e _ini , e _plus , and e _minus is as shown in FIG. 4. An algorithm (hereinafter referred to as “variable calculation / iteration / deletion determination algorithm”) further developed from the illustrated rate matching pattern determination algorithm is used. In FIG. 4, X _i is the number of bits input to the rate matching process, and corresponds to a variable k described later in this specification. Further, m is a bit number assigned to each bit in the input bit stream.

After calculating these parameters e _ini , e _plus , e _minus , the parameter calculation unit 30 notifies the D (= e _plus number) calculation unit 32 of the parameters e _ini , e _plus , e _minus .

  Further, the known number k of input bits and the number of first interleaved columns (equal to the number of radio frames created simultaneously in this embodiment) n are a parallel processing unit 31, a D calculation unit 32, and an output position control unit. 33 is notified in advance. The number n of radio frames created at the same time is the number of radio frames transmitted during a transmission time interval (TTI), which is one cycle at the time of transmission, and is a value of 2, 4, or 8. Since the time length of one radio frame is 10 ms, as defined in Subclause 4.2.5.2 of 3GPP TS25.212, n = 2 when TTI = 20 ms, n = 4 when TTI = 40 ms, and TTI = If 80 ms, n = 8.

  The parallel processing unit 31 includes input bits S (0), S (1), which are transmission targets encoded by a convolutional encoder or a turbo encoder (not shown) in step ST11 of FIG. ... S (k-1) stream is input. The parallel processing unit 31 generates the first interleaved column number n (in this embodiment, simultaneously from the input bits S (0), S (1),... S (k−1) according to the input order. Bits S (i), S (i + 1),..., S (i + n-1) are taken out, and these bits are distributed to n columns at a time, ie, n in parallel. Bits S (i), S (i + 1),..., S (i + n−1) are supplied to the output position control unit 33 in parallel. i is 0, n, 2n, 3n,. . . Is an arbitrary integer.

  The output position control unit 33 collectively performs rate matching and first interleaving based on information supplied from the D calculation unit 32 and the initial position calculation unit 34. This collective processing will be described in detail later.

The D calculation unit 32 uses the parameters e _ini , e _plus , and e _minus to determine a bit to be repeated or deleted by rate matching using a variable calculation / iteration / deletion determination algorithm. According to the variable calculation / iteration / deletion determination algorithm, the cumulative repetition / deletion bit number D can be obtained simultaneously with determination of bits to be repeated or deleted. The cumulative iteration / deletion bit number D indicates the number of times the parameter e _plus is incremented when the variable calculation / repetition / deletion decision algorithm is applied to each bit. This cumulative repetition / deletion bit number D is, for each bit, the number of preceding bits that have been repeated or deleted in the bitstream and, if that bit is repeated or deleted, the number of bits (one). As the total number is shown, it helps to properly redistribute each bit into the same number of columns as the number of bits increases or decreases. The D calculation unit 32 supplies the output position control unit 33 with a repetition / deletion instruction designating a bit to be repeated or deleted by rate matching and a cumulative repetition / deletion bit number D (= e _plus number).

The output position control unit 33 repeats or deletes any of the n bits based on the repetition / deletion instruction, and lowers or raises each bit as necessary based on the cumulative repetition / deletion bit number D. That is, a plurality of bits are newly redistributed into n columns with repetition or deletion. Further, the output position control unit 33 outputs a maximum of n bits out of the rate-matched bits to the storage device 35 at a time. The storage device 35 is provided with _n storage units 35 _{0 to} 35 _n−1 . These storage units 35 _{0 to} 35 _n-1 correspond to n radio frames created simultaneously (referred to as frame 0 to frame n-1 for convenience), and the storage units 35 _{0 to} 35 _n-1 Each of the bits can store at least a number of bits corresponding to the length of the radio frame, and by storing the bits in the storage device 35, the bits are consequently stored in a plurality of radio frames. . When outputting bits to the storage device 35, the output position control unit 33 performs first interleaving by exchanging at least two predetermined columns among the columns obtained by rate matching.

As the rate matching is performed, the number of bits processed by the output position control unit 33 increases or decreases, so that the position of the output sequence changes. Therefore, the output position control unit 33 determines the position of the output sequence from which the maximum n bits to be subjected to rate matching processing next are redistributed, for example, the last bit (for example, S (i + n−1) of the previous rate matching processing result. )) Notifies the initial position calculation unit 34 of the final bit position information indicating the value of the redistributed output sequence. Based on the value of the output sequence of the last bit indicated in the final bit position information, the initial position calculation unit 34 sets a value that specifies the output sequence of the first bit of the next n bits (for example, S (i)). The initial position information F _ini indicating this value is returned to the output position control unit 33. Based on the initial position information F _ini , the output position control unit 33 redistributes n bits to be processed next to a plurality of columns starting from the initial column indicated in the initial position information F _ini . In this way, the output position control unit 33 redistributes the bits smoothly and at high speed.

  The basic principle of the operation of the encoding processing device of the wireless communication device according to the first embodiment will be described with reference to FIG. 5 and FIG. FIG. 5 shows an example of processing in which bits are deleted (punctured) in the rate matching processing. In this example, the number of first interleaved columns n (= the number of radio frames created simultaneously) is 4, the number of bits input to the parallel processing unit 31 at a time (number of input bits k) is 16, and rate matching processing Assume that the number of bits to be deleted is 5. The parallel processing unit 31 sets the serially input bits S (0), S (1), S (2),..., S (15) to the number n of the first interleaved columns according to the input order. Parallelize to columns (column 0 to column 3).

  The D calculation unit 32 obtains bits to be deleted by a variable calculation / iteration / deletion determination algorithm. According to the puncture pattern in FIG. 5 (which bit is to be deleted is specified by the deletion instruction from the D calculation unit 32), the bits S (1), S (4), S (7), S (10), S (13) is deleted. The output position control unit 33 deletes the bit specified by the puncture pattern and moves up each bit as necessary based on the cumulative repetition / deletion bit number D (to the bit position where it becomes blank). Then, the remaining bits having the youngest subsequent numbers are substituted) to rearrange the bit data. For example, for bit S (3), 1 bit (bit S (1)) has been deleted by the rate matching process so far, so the output position (output string) is raised by 1 bit, and 1 bit from the original string 3 It will be output to the position of row 2 that has been raised. In addition, since the bit S (9) has been deleted by the rate matching process so far (bits S (1), S (4), S (7)), the output position is advanced by 3 bits, It is output to the position of column 2 that is 3 bits higher than the original column 1.

More precisely, the output position controller 33 performs rate matching on n bits at a time, that is, one row of parallelized data. That is, first, for row 0 (bits S (0), S (1), S (2), S (3)), bit S (1) is deleted and bits S (0), S ( 2) Redistribute S (3) to columns 0-2. The output position control unit 33 notifies the initial position calculation unit 34 of the final bit position information indicating the value of the column 2 of the last bit S (3), and the initial position indicating the column 3 of the first bit of the next n bits. Information F _ini is received from the initial position calculation unit 34. Thereafter, the output position control unit 33 deletes bits S (4) and S (7) for row 1 (bits S (4), S (5), S (6), and S (7)). , Bits S (5), S (6) are redistributed into columns 3, 0.

Here, the initial position information F _ini will be specifically described. As described above, the initial position calculation unit 34 is notified of the final bit position information indicating the position of the last bit string of the immediately preceding rate matching processing result in the output position control unit 33. The initial position calculation unit 34 adds the value of the last bit string +1 indicated in the last bit position information, and divides the addition result by the number of first interleaved columns (the number of radio frames created simultaneously) n. (Modulo calculation result) is stored as initial position information F _ini . For example, if the number of columns of the first interleave n = 4 and the last bit position of the previous row is column 3, (3 + 1) mod 4 = 0 is the initial position information F _ini . Here, mod indicates a modulo operation. If the last bit position of the previous time is column 1, (1 + 1) mod 4 = 2 is the initial position information F _ini .

The output position control unit 33 outputs the bits of each column obtained by the rearrangement to the storage units 35 _{0 to} 35 _n−1 of the storage device 35. At the time of this output, predetermined columns (for example, column 1 and column 2) are exchanged (first interleaving). For example, with first interleaving, column 0 bits are distributed to radio frame 0, column 1 bits are distributed to frame 2, column 2 bits are distributed to frame 1, and column 3 bits are distributed to frame 3. Is done.

  FIG. 6 shows an example of processing in which bits are repeated (repetition) in rate matching processing. Also in this example, the number of first interleaved columns n (= the number of radio frames created simultaneously) is 4, the number of bits input to the parallel processing unit 31 (the number of input bits k) is 16, and the rate matching process Suppose the number of bits to be repeated at 5 is 5. The parallel processing unit 31 sets the serially input bits S (0), S (1), S (2),..., S (15) to the number n of the first interleaved columns according to the input order. Parallelize to columns (column 0 to column 3).

  The D calculation unit 32 obtains a bit to be repeated by a variable calculation / iteration / deletion determination algorithm. According to the repetition pattern of FIG. 6 (which bit is to be repeated is specified by the repetition instruction from the D calculation unit 32), the bits S (1), S (4), S (7), S (10) , S (13) is repeated. The output position control unit 33 repeats the bits specified in this repetition pattern and lowers each bit as necessary based on the cumulative repetition / deletion bit number D, thereby arranging the bit data. Change. For example, for bit S (3), 1 bit (bit S (1)) has been repeated in the rate matching process so far, so the output position (output string) is lowered by 1 bit, and 1 bit from the original string 3 It will be output to the position of row 0 that has been lowered. Also, since the bit S (9) has been repeated 3 bits (bits S (1), S (4), S (7)) in the rate matching process so far, the output position is lowered by 3 bits, It is output to the position of column 0 which is 3 bits lower than the original column 1.

More precisely, the output position control unit 33 performs rate matching on n bits at a time, that is, one row of parallelized data. That is, first, bit S (1) is added to row 0 (bits S (0), S (1), S (2), S (3)), and bits S (0), S ( 1) Redistribute S (1), S (2), S (3) to columns 0-3 and column 0 of the next row. The output position control unit 33 notifies the initial position calculation unit 34 of the final bit position information indicating the value of the column 0 of the last bit S (3), and the initial position indicating the column 1 of the first bit of the next n bits. Information F _ini is received from the initial position calculation unit 34. Thereafter, the output position control unit 33 repeats bits S (4) and S (7) for row 1 (bits S (4), S (5), S (6), and S (7)). , Bits S (4), S (4), S (5), S (6), S (7), S (7) are redistributed into columns 1-3 and columns 0-2 of the next row.

The output position control unit 33 outputs the bits of each column obtained by the rearrangement to the storage units 35 _{0 to} 35 _n−1 of the storage device 35. Similarly to the above, at the time of this output, a predetermined column (for example, column 1 and column 2) is exchanged (first interleaving).

  It should be noted that the replacement of the columns may conform to 3GPP TS25.212 Subclause 4.2.5.2. Specifically, if TTI = 20 ms, that is, n = 2, columns 0 and 1 are stored in radio frames 0 and 1, respectively. If TTI = 40 ms, that is, n = 4 (illustrated example), columns 0, 1, 2, and 3 are stored in radio frames 0, 2, 1, and 3, respectively. If TTI = 80 ms, that is, n = 8, columns 0, 1, 2, 3, 4, 5, 6, and 7 are stored in radio frames 0, 4, 2, 6, 1, 5, 3, and 7, respectively.

  Next, details of a variable calculation / iteration / deletion determination algorithm used in the rate matching process to determine a rate matching pattern and obtain the cumulative repetition / deletion bit number D will be described. FIG. 7 is a flowchart showing a variable calculation / iteration / deletion determination algorithm. This algorithm is executed for each bit by the D calculating unit 32, and is started while designating the input bit number m. The input bit number m is the same as the input bit number m having an initial value of 1 used in the rate matching pattern determination algorithm of Subclause 4.2.7.5 of 3GPP TS25.212. As shown in FIGS. 5 and 6, in the case of a bit stream having 0 as an initial value, a value obtained by adding 1 to the illustrated bit number is the input bit number m. For example, in the case of the illustrated bit S (3), the input bit number m = 4.

First, in step ST30, an initial value 0 is substituted for the cumulative repetition / deletion bit number D. Next, in step ST31, it is determined whether or not e _ini −m · e _minus + D · e _plus is positive. If this determination result is negative, in step ST32, the cumulative repetition / deletion bit number D is incremented by 1, and the determination in step ST31 is tried again. If the determination result of step ST31 is affirmative, the process proceeds to step ST33. D at the time when the process proceeds from step ST31 to step ST33 is the determined cumulative repetition / deletion bit number D (= e _plus number) for that bit, and the number of preceding bits that have been repeated or deleted, When a bit is repeated or deleted, the total number of bits (one) is indicated. The D calculation unit 32 holds the cumulative repetition / deletion bit number D at this time.

The steps after step ST33 are executed to determine whether the input bit is a bit to be repeated or deleted. In step ST33, it is determined whether or not the formula (1) is satisfied.
e _plus −e _minus <e _ini −m · e _minus + D · e _plus ≦ e _plus . . . (1)
If this determination result is negative, it is determined that the bit is not reversed or not deleted (step ST35).

If the determination result of step ST33 is affirmative, the process proceeds to step ST34. In step ST34, it is determined whether or not the formula (2) is satisfied.
m ≧ [e _ini / e _minus ] -1. . . (2)
Here, [e _ini / e _minus], if the quotient e _ini / e _minus is an integer and the quotient e _ini / e _minus, the quotient e _ini / e _minus is the quotient e _ini / e _minus be an integer An integer rounded up to the nearest whole number. If the determination result in step ST34 is negative, it is determined that the bit is not reversed or not deleted (step ST35).

  Only when both the determination formulas of step ST33 and step ST34 are satisfied, the bit is determined to be opposite width or deleted (step ST36). The variable calculation / iteration / deletion determination algorithm shown in the figure is obtained by modifying the rate matching pattern determination algorithm defined in Subclause 4.2.7.5 of 3GPP TS25.212 shown in FIG. The determination result through ST33 to ST36 is exactly the same as the determination result by the rate matching pattern determination algorithm of 3GPP TS25.212.

FIG. 8 is a block diagram illustrating a specific circuit example of the D calculation unit 32 of FIG. As shown in FIG. 8, the D calculation unit 32 includes n D (= e _plus number) calculation units 39 _{0 to} 39 _n−1 , n iteration / deletion determination units 40 ₀ to 40 _n−1 , and A final bit D (= e _plus number) storage unit 41 is provided. D calculation units 39 _{0 to} 39 _n-1 and repetition / deletion determination units 400 ₀ to 40 _n-1 are provided for each of columns ₀ to _n-1 , and subscripts ₀ to _n-1 are respectively provided. Corresponds to columns 0 to n-1.

Each of the D calculation units 39 _{0 to} 39 _n-1 executes a procedure corresponding to step ST30 to step ST32 in the variable calculation / iteration / deletion determination algorithm of the flowchart of FIG. / The deletion bit number D (= e _plus number) is notified to the output position control unit 33 (D (i), D (i−1),... D (i + n−1)). After the cumulative iteration / deletion bit number D is calculated by the D calculation units 39 _{0 to} 39 _n−1 , the iteration / deletion determination units 400 ₀ to 40 _n-1 are steps ST33 to ST among the variable calculation / iteration / deletion determination algorithms. The procedure corresponding to ST36 is executed for the corresponding column, and if it is concluded that it should be repeated or deleted, an iteration / deletion instruction is supplied to the output position control unit 33.

By having n D calculation units 39 _{0 to} 39 _n−1 and n iteration / deletion determination units 40 ₀ to 40 _n−1 , the D calculation unit 32 can perform one line (n pieces) in FIGS. The variable calculation / iteration / deletion decision algorithm can be applied to the same bit). For example, for row 0 of FIG. 5 and FIG. 6, the cumulative repetition / puncture bits number D of bits S (0) is calculated by D calculation unit 39 _0, whether or not to repeat or delete bits S a (0) There is determined in an iterative / deletion determining unit 40 _0, cumulative repetition / puncture bits number D of bits S (1) is calculated by D calculation unit 39 _1, whether or not to repeat or delete bits S (1) is Determined by the iteration / deletion determination unit 40 ₁ , the cumulative iteration / deletion bit number D for the bit S (3) is calculated by the D calculation unit 39 _n−1 , and whether or not the bit S (3) should be repeated or deleted. Is determined by the repetition / deletion determination unit 40 _n−1 .

The value of D set as an initial value in the calculation procedure of the cumulative repetition / deletion bit number D executed by the D calculation units 39 _{0 to} 39 _n-1 is the first row, row 0 (bits S (0), S ( When calculating for 1), S (2), S (3)), D = 0 is used as in step ST30 of FIG. When calculating the subsequent rows, it is preferable to set the cumulative repetition / deletion bit number D for the last bit of the row calculated immediately before as an initial value. For this purpose, the last bit D storage 41 is used. Since the cumulative repetition / deletion bit number D increases as the input bit number increases, the number of calculation processes in step ST31 and step ST32 can be reduced by using the cumulative repetition / deletion bit number D in the immediately preceding row. For example, when calculating for row 1 (bits S (4), S (5), S (6), S (7)), cumulative iteration / deletion at the time of calculating the last bit S (3) of row 0 The number of bits D is set as an initial value.

The last bit D storage unit 41 is supplied with the value of the cumulative repetition / deletion bit number D of the last bit of the last row calculated from the D calculation unit 39 _n−1 and stored therein. This cumulative repetition / deletion bit number D is loaded into each of the D calculation units 39 _{0 to} 39 _n-1 as an initial value of D in the calculation of the variable calculation / repetition / deletion determination algorithm for the next row.

As described above, the D calculation unit 32 notifies the output position control unit 33 of the cumulative repetition / deletion bit number D for each column and the repetition / deletion instruction designating the bits to be repeated or deleted. However, the cumulative repetition / deletion bit numbers D (i), D (i−1),... D (i + n−1) notified from the D calculation unit 32 to the output position control unit 33 are the D calculation units 39 _{0 to} 39. _This is a remainder (modulo calculation result) obtained by dividing D calculated by _n−1 by the number of first interleaved columns (the number of radio frames created simultaneously) n. For example, if the number of columns of the first interleave is n = 4 and D calculated by the D calculating unit is 3, 3mod 4 = 3 is notified to the output position control unit 33 as the cumulative repetition / deletion bit number D. If D calculated by the D calculating unit is 5, 5mod 4 = 1 is notified to the output position control unit 33 as the cumulative repetition / deletion bit number D.

9 and 10 are block diagrams illustrating specific circuit examples of the output position control unit 33 in FIG. As shown in FIGS. 9 and 10, the output position control unit 33 includes n adders 33A _{0 to} 33 _n−1 , n output position calculation units 36 _{0 to} 36 _n−1 , and n write controls. Units (redistribution control units) 37 _{0 to} 37 _n-1 and a bit storage output unit 38. Adders 33A _{0 to} 33 _n-1 , output position calculation units 36 _{0 to} 36 _n-1 , and write control units 37 _{0 to} 37 _n-1 are provided for each of columns _{0 to n-1.} Subscripts 0 to n-1 correspond to columns 0 to n-1, respectively.

  FIGS. 11 and 12 are the same as FIGS. 9 and 10, and the number of first interleaved columns (the number of radio frames created simultaneously) n = 4 and bits S (i) and S in the rate matching process. (I + 3) shows the flow of processing to be deleted. FIGS. 13 and 14 are the same diagrams as FIGS. 9 and 10, and the number of first interleaved columns (the number of radio frames created simultaneously) n = 4, and bit S (i) is obtained by rate matching processing. , S (i + 3) shows a process flow in which it is repeated. Hereinafter, a specific operation of the output position control unit 33 will be described with reference to FIGS. 9 to 14.

Bits S (i), S (i + 1),..., S (i + n−1) supplied from the parallel processing unit 31 are given to the write control units 37 _{0 to} 37 _n−1 . The initial position information F _ini is supplied from the initial position calculation unit 34 to the adders 33A _{0 to} 33 _n−1 . For the first to the n bits of the row to be supplied to the output position control unit 33 in one TTI bitstream, the initial position information F _ini 0, the next lines, the initial position information F _ini is An output string (output position) of the first bit among n bits is shown.

The adders 33A _{0 to} 33 _n−1 add the column number value C to the initial position information F _ini . The addition result is loaded to the output position calculation units 36 _{0 to} 36 _n−1 as position information F (i), F (i + 1),..., F (i + n−1) of each bit.
Column number values C (0), C (1),..., C (n−1) are set as follows according to the number of columns (= number of radio frames) n of the first interleave.
When n = 2, C (0) = 0, C (1) = 1.
When n = 4, C (0) = 0, C (1) = 1, C (2) = 2, C (3) = 3.
When n = 8, C (0) = 0, C (1) = 1, C (2) = 2, C (3) = 3, C (4) = 4, C (5) = 5, C (6) = 6, C (7) = 7.
Thus, the column number value C indicates the output position (output string) of each bit when there is no bit to be repeated or deleted and the initial position information F _ini is 0. That is, in Embodiment 1, the column number value C is the column number of each bit before rate matching.

Position information F (i), F (i + 1),..., F (i + n−1) are loaded into the output position calculation units 36 _{0 to} 36 _n−1 , respectively. Further, the cumulative repetition / deletion bit number D (= e _plus number) corresponding to each column is loaded into the output position calculation units 36 _{0 to} 36 _n−1 (D (i), D (i + 1),... ., D (i + n-1)). Each of the output position calculation units 36 _{0 to} 36 _n−1 calculates the output position as follows based on the position information F loaded therein and the cumulative repetition / deletion bit number D. The output position calculated by the output position calculation units 36 _{0 to} 36 _n-1 is an output string to which the bit should be distributed in consideration of the preceding bit by the rate matching process and repetition or deletion of the bit. Columns 0 to 3n-1 assigned to the bit storage unit 38A of the bit storage output unit 38.

When rate matching is a bit deletion, output position bits S (i) is the output position calculating unit 36 ₀ is calculated by F (i) -D (i) . Output position bits S (i + 1) is the output position calculation unit 36 _1, obtained by F (i + 1) -D ( i + 1). Output position bits S (i + 2) is the output position calculation portion 36 _2, obtained by F (i + 2) -D ( i + 2). Similarly, the output position of the bit S (i + n−1) is obtained by F (i + n−1) −D (i + n−1) by the output position calculation unit 36 _n−1 .

As an example of bit deletion, as shown in FIGS. 11 and 12, n = 4, initial position information F _ini = 3, D (i) = 1, D (i + 1) = 1, D (i + 2) = 1, D (i + 3) = in the case of 2, the output position calculating unit 36 ₀ is calculated as 2 output position bits S (i). Similar cases, the output position calculation unit 36 ₁ calculates the 3 output position bits S (i + 1), the output position calculation unit 36 ₂ calculates four output position bits S (i + 2), an output position calculation unit 36 ₃ is calculated as 4 output position bits S (i + 3).

When rate matching is a bit repetition, the output position of the bit S (i) is the output position calculating unit 36 ₀ is calculated by F (i) + D (i ). Output position bits S (i + 1) is the output position calculation unit 36 _1, obtained by F (i + 1) + D (i + 1). Output position bits S (i + 2) is the output position calculation portion 36 _2, obtained by F (i + 2) + D (i + 2). Similarly, the output position of the bit S (i + n−1) is obtained by F (i + n−1) + D (i + n−1) by the output position calculation unit 36 _n−1 .

As an example of bit repetition, as shown in FIGS. 13 and 14, n = 4, initial position information F _ini = 1, D (i) = 1, D (i + 1) = 1, D (i + 2) = 1, D (i + 3) = in the case of 2, the output position calculating unit 36 ₀ is calculated as 2 output position bits S (i). Similar cases, the output position calculation unit 36 ₁ calculates the 3 output position bits S (i + 1), the output position calculation unit 36 ₂ calculates four output position bits S (i + 2), an output position calculation unit 36 ₃ calculates the output position bits S (i + 3) and 6.

After calculating the output position of each bit by the output position calculation units 36 _{0 to} 36 _n−1 , the write control units 37 _{0 to} 37 _n−1 perform the bits S (i), S (i + 1),..., S (i + n− 1) is written to the bit storage output unit 38. The bit storage output unit 38 has 3n bit storage units 38A for storing each of the bits in column 0 to column 3n-1, and 3n for reading out the stored bits from each bit storage unit 38A. Data output units 38B. Each bit storage unit 38A is assigned an address designating one of the columns 0 to 3n-1.

In the bit storage output unit 38, when the rate matching is bit repetition, the number of output bits of the output position control unit 33 is the number of storage units 35 _{0 to} 35 _n−1 provided for each radio frame created simultaneously. Since the number exceeds n, the buffer is provided to match the bit writing to the storage device 35. The bit storage units 38A of the columns n to 2n-1 correspond to the columns 0 to n-1, respectively, and when the bit storage units 38A of the columns 0 to n-1 are filled with the preceding bits, the columns 0 to n- Store the bits to be redistributed to one. The bit storage units 38A of the columns 2n to 3n-1 also correspond to the columns 0 to n-1, respectively, and the bit storage units 38A of the columns 0 to n-1 in the preceding bits are also the bit storage units 38A of the columns n to 2n-1. Stores the bits to be redistributed in columns 0 to n−1. When the rate matching process is bit deletion, bits may be output from the write control units 37 _{0 to} 37 _n-1 to the storage device 35 without going through the bit storage output unit 38.

The write control units 37 _{0 to} 37 _n−1 convert the bits S (i), S (i + 1),..., S (i + n−1) to the output sequence calculated by the output position calculation units 36 _{0 to} 36 _n−1. Distribution and writing to the corresponding bit storage unit 38A. The write control units 37 _{0 to} 37 _n-1 are notified of repetition / deletion instructions from the D calculation unit 32, and the write control units 37 _{0 to} 37 _n-1 distribute and write bits to the bit storage unit 38A. Sometimes, a process corresponding to the rate matching process is executed according to the repeat / delete instruction. When the rate matching process is bit deletion, the write control units 37 _{0 to} 37 _n-1 do not write bits to be deleted to the bit storage unit 38A.

As an example of bit deletion, as shown in FIGS. 11 and 12, when the D calculation unit 32 instructs to delete bits S (i) and S (i + 3), output position calculation units 36 ₀ , 36 ₃ calculates the output positions of the bits S (i) and S (i + 3) as 2 and 4, respectively, the write control units 37 ₀ and 37 ₃ corresponding to the bits S (i) and S (i + 3) S (i) and S (i + 3) are discarded without being written in the bit storage unit 38A for columns 2 and 4. On the other hand, the write control units 37 ₁ and 37 ₂ write the bits S (i + 1) and S (i + 2) into the bit storage units 38A for the columns 3 and 4 according to the calculation results of the output position calculation units 36 ₁ and 36 ₂ . In this case, as can be seen from the initial position information F _ini being 3, since the last bit of the row calculated immediately before is written in the bit storage unit 38A for column 2, the write control unit 37 _0. Since the bit S (i) is not written to the bit storage unit 38A for the column 2, the consistency of the column in the bit storage output unit 38 is maintained. Also, the bit storage unit 38A for row 4, bit S (i + 2) but is written by the write controller 37 ₃ is not write bit S a (i + 3) in the bit storage unit 38A for row 4 , To avoid inappropriate collisions. As is apparent from the above, when the rate matching process is bit deletion, the output sequence of the bits to be deleted and the subsequent bits are advanced by the increment of the cumulative repetition / deletion bit number D.

When the rate matching processing is bit repetition, the write control units 37 _{0 to} 37 _n-1 have the bit storage unit 38 A of the output position (address) obtained by the output position calculation unit 36 and the address obtained by subtracting 1 from the address. The same bit is written twice in two places of the bit storage unit 38A. For example, as shown in FIGS. 13 and 14, when the D calculation unit 32 instructs the repetition of bits S (i), the writing control unit 37 _0, in accordance with the calculated result of the output position calculating unit 36 ₀ Not only the bit S (i) is written in the bit storage unit 38A for the column 2, but also the bit S (i) is written in the bit storage unit 38A for the column 1 subtracted from the column 2. In this case, as can be seen from the fact that the initial position information F _ini is 1, since the last bit of the row calculated immediately before is written in the bit storage unit 38A for the column 0, the write control unit 37 _0. Writes the bit S (i) to the bit storage unit 38A for the columns 1 and 2, so that the integrity of the columns in the bit storage output unit 38 is maintained.

On the other hand, the write control units 37 ₁ and 37 ₂ write the bits S (i + 1) and S (i + 2) into the bit storage units 38A for the columns 3 and 4 according to the calculation results of the output position calculation units 36 ₁ and 36 ₂ . Further, since the D calculation unit 32 instructs the repetition of bits S (i + 3), the write controller 37 _3, bits in the bit storage unit 38A for row 6 in accordance with the calculated result of the output position calculating unit 36 ₃ S In addition to writing (i + 3), the bit S (i + 3) is also written to the bit storage unit 38A for column 5 which is 1 subtracted from column 6. Also in this case, the consistency of the columns in the bit storage output unit 38 is maintained. As is apparent from the above, when the rate matching process is bit repetition, the output sequence of the bits to be repeated and the subsequent bits are eventually lowered by the increment of the cumulative repetition / deletion bit number D.

Whether the rate matching process is bit repetition or bit deletion, the bit storage output unit 38 notifies the initial position calculation unit 34 of the final bit position information described above according to the contents of the bit storage unit 38A. For example, in the case of FIGS. 11 and 12, the bit storage output unit 38 notifies the initial position calculation unit 34 of the final bit position information indicating the column 4, and the initial position calculation unit 34 sets the next initial position information F _ini as the next initial position information F _ini. (4 + 1) mod 4 = 1 is calculated. 13 and FIG. 14, the bit storage output unit 38 notifies the initial position calculation unit 34 of the final bit position information indicating the column 6, and the initial position calculation unit 34 sets (6 + 1) as the next initial position information F _ini. ) Mod 4 = 3 is calculated.

The contents of the initial position calculation unit 34 are reset every time one TTI expires, and the initial position information F _ini for the calculation of the first bit thereafter becomes zero.

After completing the bit writing to the bit storage unit 38A of the bit storage output unit 38, the data output unit 38B transmits bits to the storage units 35 _{0 to} 35 _n-1 provided for each number of radio frames created simultaneously in the storage device 35. Perform writing. First, when the first clock pulse after completion of bit writing to the bit storage unit 38A is supplied to the bit storage output unit 38, the data output unit 38B for columns 0 to n-1 corresponds to the corresponding bit storage unit 38A. N bits are read out and written to the storage units 35 _{0 to} 35 _n−1 . At this time, the columns are exchanged by the first interleaving and written in the storage units 35 _{0 to} 35 _n−1 . For example, if the first number of columns interleaved n = 4 (= number of radio frames is created at the same time), bits of the column 0 of bit storage unit 38A in the storage unit 35 ₀ of frame 0 of the storage device 35, frame 1 bits of the column 2 in the storage unit 35 ₁ of the bits of the column 1 in the storage unit 35 ₂ of the frame 2, to write the bits of the column 3 in the storage unit 35 ₃ of the frame 3, in this example columns 1 and 2 Exchanged. After reading the bits, the contents of the bit storage unit 38A are erased.

When the next clock pulse is supplied to the bit storage output unit 38, n bits in the columns _{n to 2n-1} are transferred from the bit storage unit 38A to the storage units 35 _{0 to} 35 _n-1 . For the replacement of the column, for example, in the case of the first interleave sequence number n = 4 in as shown, the storage unit 35 ₀ of frame 0 of the storage device 35 of column 4 of bit storage unit 38A bits, the frame 1 bits of the storage unit 35 ₁ column 6, bits of the column 5 in the storage unit 35 ₂ of the frame 2, the storage unit 35 ₃ of the frame 3 writes the bits of the column 7. In this example, columns 1 and 2 corresponding to columns 5 and 6 are exchanged. When the next clock pulse is supplied to the bit storage output unit 38, n bits in the columns 2n to 3n _-1 are transferred from the bit storage unit 38A to the storage units 35 _{0 to} 35 _n-1 .

FIG. 15 is an operation timing chart of processing in which bits S (i) and S (i + 3) in the 4 bits shown in FIGS. 11 and 12 are deleted. Time T in the figure indicates the rising time of the clock pulse. For the input bits S (i), S (i + 1), and S (i + 2), the D calculation unit 32 calculates the cumulative repetition / deletion bit numbers D (i), D (i + 1), and D (i + 2) at times T0 to T2. It is calculated and it is determined whether or not the bit should be deleted. Further, at time T2 to T3, the output position calculation units 36 _{0 to} 36 ₂ calculate the output positions of the bits S (i), S (i + 1), and S (i + 2), and the output position calculation units 36 _{0 to} 36 ₂ calculate them. results and write controller 37 _{0-37 2} according deletion instruction from the D calculation unit 32 makes the bit write or disposal of the bit storage unit 38A of the bit storage output unit 38 (discard exactly bit S (i) Then, the bit S (i + 1) is written in the bit storage unit 38A in the column 3 and the bit S (i + 2) is written in the bit storage unit 38A in the column 4).

For the input bit S (i + 3), at time T0 to T3, the D calculation unit 32 calculates the cumulative repetition / deletion bit number D (i + 3), and determines whether or not the bit should be deleted. Moreover, the output position calculation unit ₃₆₃ at time T3~T4 calculates the output position bits S (i + 3), the output position calculation portion 36 ₃ of the calculation result and the D-calculation unit 32 writes the control unit 37 ₃ according to the deletion instruction from Writes or discards bits in the bit storage unit 38A of the bit storage output unit 38 (precisely, discards the bit S (i + 3)). Compared to the input bits S (i), S (i + 1), and S (i + 2), the processing time of the input bit S (i + 3) is delayed because of the cumulative repetition / deletion bit number D for the input bit S (i + 3). (I + 3) is 2, which is larger than the number of cumulative repetition / deletion bits D (i), D (i + 1), D (i + 2) for the input bits S (i), S (i + 1), S (i + 2) This is because the processing cycle becomes longer (see FIGS. 11, 12, and 7).

In this way, after all the rate matching processing results of the input bits S (i) to S (i + 3) are stored in the bit storage unit 38A, at the time T4 to T5, in the bit storage output unit 38, the columns 0 to The data output unit 38B for the column n-1 reads the bits of the columns 0 to n-1 from the bit storage unit 38A, and the storage units 35 _{0 to} 35 _n-1 provided for each number of radio frames created simultaneously. Write to (output). Similarly, if bits are stored in any of the bit storage units 38A for the columns n to 2n-1 of the bit storage output unit 38, at time T5 to T6, for the columns n to 2n-1. Data output unit 38B reads the bits of column n to column 2n-1 from bit storage unit 38A and writes them to storage units 35 _{0 to} 35 _n-1 . If a bit is stored in any of the bit storage units 38A for the columns 2n to 3n-1 of the bit storage output unit 38, at time T6 to T7, the data output unit for the columns 2n to 3n-1 38B reads the bits of the columns 2n to 3n-1 from the bit storage unit 38A and writes them to the storage units 35 _{0 to} 35 _n-1 .

FIG. 16 is an operation timing chart of processing in which bits S (i) and S (i + 3) in the 4 bits shown in FIGS. 13 and 14 are repeated. For the input bits S (i), S (i + 1), and S (i + 2), the D calculation unit 32 calculates the cumulative repetition / deletion bit numbers D (i), D (i + 1), and D (i + 2) at times T0 to T2. Calculate and determine if the bit should be repeated. Further, at time T2 to T3, the output position calculation units 36 _{0 to} 36 ₂ calculate the output positions of the bits S (i), S (i + 1), and S (i + 2), and the output position calculation units 36 _{0 to} 36 ₂ calculate them. result in accordance with the write controller 37 _{0-37 2} is the writing of bits into the bit storage unit 38A of the bit storage output unit 38 (to be exact bit S (i) the column 2 of the bit storage unit 38A, bit S (i + 1 ) Is written to the bit storage unit 38A of column 3 and bit S (i + 2) is written to the bit storage unit 38A of column 4).

For bit S (i + 3), D calculation unit 32 calculates cumulative repetition / deletion bit number D (i + 3) at times T0 to T3, and determines whether or not the bit should be repeated. Moreover, the output position calculation unit ₃₆₃ at time T3~T4 calculates the output position bits S (i + 3), the write controller 37 ₃ in accordance with the calculated result of the output position calculating unit 36 _3-bit storage output unit 38 columns 6 The bit is written into the bit storage unit 38A. Compared to the input bits S (i), S (i + 1), and S (i + 2), the processing time of the input bit S (i + 3) is delayed because of the cumulative repetition / deletion bit number D for the input bit S (i + 3). (I + 3) is 2, which is larger than the number of cumulative repetition / deletion bits D (i), D (i + 1), D (i + 2) for the input bits S (i), S (i + 1), S (i + 2) This is because the processing cycle becomes longer (see FIGS. 13, 14 and 7).

Because according to the repeat instruction from D calculator 32-bit S (i) is the bit to be repeated, at a time T3 to T4, the write controller 37 ₀ 1 from the calculated result of the output position calculating unit 36 ₀ subtracting performs output position calculation, the write control unit 37 ₀ in accordance with the output position calculation result is written to bits S (i) in the bit storage unit 38A of the column 1. Since bit S (i + 3) is also a bit to be repeated, at a time T4 to T5, the write controller 37 ₃ performs an output position calculation subtracting 1 from the calculation result of the output position calculating unit _363, the output position calculation results write controller 37 ₃ according to the write bit S (i + 3) in the bit storage unit 38A of the column 5.

In this way, after all the rate matching processing results of the input bits S (i) to S (i + 3) are stored in the bit storage unit 38A, at time T5 to T6, in the bit storage output unit 38, the columns 0 to The data output unit 38B for the column n-1 reads the bits of the columns 0 to n-1 from the bit storage unit 38A, and the storage units 35 _{0 to} 35 _n-1 provided for each number of radio frames created simultaneously. Write to (output). Similarly, if a bit is stored in any of the bit storage units 38A for the columns n to 2n-1 of the bit storage output unit 38, the column n to the column 2n-1 at time T6 to T7. The data output unit 38B reads out the bits of column n to column 2n-1 from the bit storage unit 38A and writes them to the storage units 35 _{0 to} 35 _n-1 . If bits are stored in any of the bit storage units 38A for the columns 2n to 3n-1 of the bit storage output unit 38, at time T7 to T8, the data output unit for the columns 2n to 3n-1 38B reads the bits in the columns 2n to 3n-1 from the bit storage unit 38A and writes them to the storage units 35 _{0 to} 35 _n-1 .

As described above, according to the first embodiment, the parallel processing unit 31 extracts, from the data bit stream to be transmitted, the same number of bits as the number of a plurality of radio frames created at the same time, and these bits are wirelessly transmitted. Distribute regularly to the same number of columns as the number of frames. The parameter calculation unit 30 calculates rate matching basic parameters e _ini , e _plus , and e _minus . Further, the D calculation unit 32, based on the bit number m in the data bit stream assigned to each bit distributed to the column and the basic parameters e _ini , e _plus , e _minus , a plurality of bits distributed to the column Of the bits to be repeated or deleted. Furthermore, for each bit distributed to the column, the D calculation unit 32 determines the number of preceding bits to be repeated or deleted in the data bit stream and the number of bits when the bit is repeated or deleted. The cumulative repetition / deletion bit number D, which is the total number, is calculated. The output position control unit 33 functions as a rate matching / first interleaving unit, and among the plurality of bits distributed to the columns by the parallel processing unit 31, the bits determined to be repeated or deleted by the D calculation unit 32 Are repeated or deleted, and a plurality of bits are newly redistributed into a plurality of columns based on the cumulative repetition / deletion bit number D, and at least two bits of the plurality of columns obtained by the redistribution are replaced with each other. The bits of the redistributed and permuted columns are each stored in a plurality of radio frames. In this way, by redistributing a plurality of bits into a plurality of columns based on the cumulative repetition / deletion bit number D, the bit redistribution can be completed at a high speed, and the plurality of bits obtained by the redistribution can be obtained. The first interleaving is completed only by exchanging bits in at least two of the columns. Therefore, it is possible to complete the bit redistribution and the first interleaving at a higher speed than in the case of the bit redistribution and the first interleaving based on the bit itself obtained by the rate matching. In addition, since the parallel processing unit 31 performs rate matching on the bits distributed to the plurality of columns, that is, parallelized bits, and performs the first interleaving by exchanging the columns, the first interleaving result corresponds to the plurality of radio frames. Therefore, it is not necessary to perform the radio frame division again. As described above, it is possible to further speed up the encoding process while complying with W-CDMA.

The D calculation unit 32 also includes a plurality of repetition / deletion determination units 40 ₀ to 40 for determining in parallel whether or not each of the plurality of bits distributed to the columns by the parallelization processing unit 31 should be repeated or deleted. _{with n-1} . Further, the D calculation unit 32 calculates the cumulative repetition / deletion bit number D (i), D (i−1),... D (i + n−1) for each of the plurality of bits distributed to the columns by the parallel processing unit 31. D calculation units 39 _{0 to} 39 _n-1 for calculating in parallel are provided. The output position control unit 33 serving as a rate matching / first interleaving unit, for each of a plurality of bits distributed to the columns by the parallel processing unit 31, corresponds to the corresponding cumulative repetition / deletion bit numbers D (i) and D (i −1),... D (i + n−1), a plurality of output position calculation units 36 _{0 to} 36 _n−1 that calculate columns to be redistributed, and a plurality of distributions distributed to the columns by the parallel processing unit 31 Are repeated or deleted when it is determined that they should be repeated or deleted by the corresponding repetition / deletion determination units 40 ₀ to 40 _n−1 , and output position calculation units 36 _{0 to} 36 _n- a plurality of write control unit 37 ₀ to 37 _n-1 to redistribute to the calculated column _1. According to this configuration, the parallelized bits are rate-matched at the same time, and the bit is further redistributed into columns in consideration of the cumulative repetition / deletion bit number D for each bit. It is possible to increase the speed.

The output position control unit 33 serving as a rate matching / first interleaving unit includes a plurality of bit storage units 38A larger than the number of columns, and a data output unit 38B that reads bits from each bit storage unit 38A and stores them in a radio frame. Each of the output position calculation units 36 _{0 to} 36 _n-1 calculates the position of the bit storage unit 38A where each bit is to be stored, and each of the write control units 37 _{0 to} 37 _n-1 The bits are repeated or deleted, and each bit is stored in the bit storage unit 38A at the position calculated by the output position calculation units 36 _{0 to} 36 _n−1 , and the data output unit 38B determines the number of radio frames at a time. The same number of bits are read from the bit storage unit 38A, and at least two of these bits are exchanged and stored in a plurality of radio frames. When the rate matching processing is bit repetition, bits exceeding the number n of columns are output from the write control units 37 _{0 to} 37 _n−1, but these bits are stored in a plurality of bit storage units 38A having a number larger than the number of columns. By doing so, overflow can be prevented.

  Furthermore, the encoding processing device of the wireless communication device may be configured to perform the first bit among the plurality of bits to be redistributed next based on the column in which the last bit among the plurality of bits redistributed immediately before is redistributed. The output position control unit 33 redistributes a plurality of bits to be redistributed to a plurality of columns starting from the initial column. Therefore, the bits can be redistributed smoothly and at high speed.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. A decoding processing device of a wireless communication apparatus according to Embodiment 2 of the present invention is provided in a base station of a wireless communication system based on W-CDMA, and performs rate dematching (step ST25) for uplink data reception in FIG. This is applied to combining (step ST26) and first deinterleaving (step ST27). FIG. 17 is a functional block diagram showing a decoding processing apparatus according to Embodiment 2 of the present invention. Illustration of other components of the wireless communication device is omitted.

As shown in FIG. 17, the decoding processing apparatus includes a parameter calculation unit 130, a parallelization processing unit 131, a D (= e _plus number) calculation unit (iteration / deletion determination unit) 132, an output position control unit (rate data). A matching unit) 133, an initial position calculation unit 134, a storage device 135, and a column data reading order control unit (first deinterleave / radio frame combining unit) 150. The parameter calculation unit 130 is actually a CPU or DSP of the wireless communication apparatus, and operates according to a program. The parallel processing unit 131, the D calculation unit 132, the output position control unit 133, the initial position calculation unit 134, and the column data reading order control unit 150 are each part of an FPGA or an LSI. The storage device 135 is a RAM.

  The parameter calculation unit 130, the parallelization processing unit 131, the D calculation unit 132, the output position control unit 133, the initial position calculation unit 134, and the storage device 135 are the same as the parameter calculation unit 30, the parallelization processing unit 31, D of the first embodiment. Each of the calculation unit 32, the output position control unit 33, the initial position calculation unit 34, and the storage device 35 has an equivalent or similar function.

The parameter calculation unit 130 calculates e _ini , e _plus , and e _minus that are parameters necessary for the rate dematching process. The parameter calculation unit 130 calculates these parameters based on the data rate and the like according to Subclause 4.2.7 of 3GPP TS25.212. The calculated parameters e _ini, e _plus, e _minus the parameter e _ini used for rate matching processing of the data transmission, e _plus, becomes e _minus the same value.

After calculating these parameters e _ini , e _plus , e _minus , the parameter calculation unit 130 notifies the D (= e _plus number) calculation unit 132 of the parameters e _ini , e _plus , e _minus .

  Also, the known number k of input bits, the number of first deinterleaved columns (in this embodiment, equal to the number of radio frames received in the same reception cycle) n are the parallel processing unit 131, D calculation unit 132, and The output position control unit 133 is notified in advance. The number n of radio frames received in the same reception cycle is the number of radio frames transmitted during a transmission time interval (TTI) that is one cycle at the time of transmission. It is. Since the time length of one radio frame is 10 ms, as defined in Subclause 4.2.5.2 of 3GPP TS25.212, n = 2 when TTI = 20 ms, n = 4 when TTI = 40 ms, and TTI = If 80 ms, n = 8.

  The parallelization processing unit 131 receives a stream of input bits to be received that are transport channel divided in step ST24 of FIG. The parallel processing unit 131 receives the first deinterleaved column number n (in this embodiment, the same reception cycle from the input bits A (0), A (1),... A (k−1) according to the input order. , A (i + 1),..., A (i + n−1), and distribute these bits to n columns at the same time, ie, parallelize them. N bits A (i), A (i + 1),..., A (i + n−1) are supplied to the output position control unit 133 in parallel. i is 0, n, 2n, 3n,. . . Is an arbitrary integer.

  The output position control unit 133 performs rate dematching processing based on information supplied from the D calculation unit 132 and the initial position calculation unit 134. This rate dematching is almost the same as the rate matching process of the first embodiment.

The D calculation unit 132 should be iterated or deleted by rate _dematching using the parameters e _ini , e _plus , e _minus and the variable calculation / iteration / deletion determination algorithm shown in FIG. 7 and described above with reference to the first embodiment. Determine the bit. Further, the D calculation unit 132 obtains the cumulative repetition / deletion bit number D simultaneously with the determination of the bits to be repeated or deleted by the variable calculation / iteration / deletion determination algorithm. The cumulative iteration / deletion bit number D indicates the number of times the parameter e _plus is incremented when the variable calculation / repetition / deletion decision algorithm is applied to each bit. This cumulative repetition / deletion bit number D indicates, for each bit, the number of preceding bits that have been repeated or deleted, and the total number of bits (one) when the bit is repeated or deleted. So it helps to redistribute each bit to the same number of columns as the number of bits increases or decreases. The D calculation unit 132 supplies the output position control unit 133 with a repetition / deletion instruction specifying a bit to be repeated or deleted by rate dematching and a cumulative repetition / deletion bit number D (= e _plus number).

The output position control unit 133 repeats or deletes any of the n bits based on the repetition / deletion instruction, and lowers or raises each bit as necessary based on the cumulative repetition / deletion bit number D. That is, a plurality of bits are newly redistributed into n columns with repetition or deletion. Further, the output position control unit 133 outputs a maximum of n bits among the bits subjected to rate dematching in this manner to the storage device 135 at a time. The storage device 135 is provided with _n storage units 135 _{0 to} 135 _n−1 . These storage units 135 _{0 to} 135 _n-1 correspond to n columns in which bits are redistributed by rate dematching, and each of the storage units 135 _{0 to} 135 _n-1 has a length of a radio frame. It is possible to store more bits than the corresponding number of bits, and it is possible to store the number of bits repeatedly increased from all bits constituting the n radio frames received in the same reception cycle in the entire storage device 135. Can be stored. When outputting bits to the storage device 135, the output position control unit 133 stores the bits in the storage units 135 _{0 to} 135 _n−1 to which the same column numbers as the column numbers obtained by rate dematching are given.

As the rate dematching is performed, the number of bits processed by the output position control unit 133 increases or decreases, and the position of the output sequence changes. Therefore, the output position control unit 133 determines the position of the output sequence from which the maximum n bits to be rate dematched next are redistributed to determine the last bit (for example, A (i + n) of the previous rate dematching result. -1)) notifies the initial position calculation unit 134 of the final bit position information indicating the value of the redistributed output sequence. Based on the value of the output sequence of the last bit indicated in the final bit position information, the initial position calculation unit 134 obtains a value that specifies the output sequence of the first bit (for example, A (i)) of the next n bits. The initial position information F _ini indicating this value is returned to the output position control unit 133. Based on the initial position information F _ini , the output position control unit 133 redistributes n bits to be processed next to a plurality of columns starting from the initial column indicated in the initial position information F _ini . In this way, the output position control unit 133 smoothly redistributes bits.

After all bits obtained (increased / decreased) by the rate dematching process from all bits constituting n radio frames received in the same reception cycle are stored in the storage device 135, the column data reading order control unit 150 , All bits are read from the storage units 135 _{0 to} 135 _{n−1 of} the storage device 135 and combined. As a result, radio frame combination is performed. At the time of this reading, the column data reading order control unit 150 performs the first interleaving by exchanging a predetermined column among the columns obtained by rate matching.

  The basic principle of the operation of the decoding processing apparatus of the wireless communication apparatus according to the second embodiment will be described with reference to FIGS. 18 to 21 show examples of processing in which bits are deleted (punctured) by rate dematching processing, and show processing of radio frames 0 to 3, respectively. In this example, the number n of first deinterleaved columns (= the number of radio frames received in the same reception cycle) is 4, the number of bits per radio frame is 16, and is input to the parallel processing unit 131 at a time. Assume that the number of bits (number of input bits k) is 4 × 16 = 64, and the number of bits to be deleted in the rate dematching process per radio frame is 5. Radio frames 0 to 3 are four radio frames received in the same reception cycle.

  Hereinafter, bits A0 (0), A0 (1), A0 (2),..., A0 (15) in the order of input of the radio frame 0 bits, bits A1 (0), A1 in the order of input of the radio frame 1 (1), A1 (2),..., A1 (15), bits of the radio frame 2 are input in the order of input bits A2 (0), A2 (1), A2 (2),. The bits of the wireless frame 3 are assumed to be bits A3 (0), A3 (1), A3 (2),..., A3 (15) in the order of input. This decoding processing device advances rate dematching processing in the order of radio frames 0, 1, 2, and 3.

  First, as shown in FIG. 18, the parallel processing unit 131 inputs the bits A0 (0), A0 (1), A0 (2),. According to the order, the first deinterleaved column number n is parallelized to 4 columns (column 0 to column 3).

  The D calculation unit 132 obtains a bit to be deleted by a variable calculation / iteration / deletion determination algorithm. According to the puncture pattern in FIG. 18 (which bit is to be deleted is specified by the deletion instruction from the D calculation unit 132), the bits A0 (1), A0 (4), A0 (7), A0 (10), A0 (13) is deleted. The output position control unit 133 deletes the bit specified by the puncture pattern and rearranges the bit data by moving up each bit as necessary based on the cumulative repetition / deletion bit number D. I do. For example, for bit A0 (3), 1 bit (bit A0 (1)) has been deleted by the rate dematching process so far, so the output position (output column) is raised by 1 bit, and the original column 3 to 1 The data is output to the position of column 2 where the bit is advanced. In addition, since the bit A0 (9) has been deleted by the rate dematching process so far (bits A0 (1), A0 (4), A0 (7)), the output position is advanced by 3 bits. The data is output to the position of column 2 that is 3 bits higher than the original column 1.

More precisely, the output position control unit 133 performs rate dematching on n bits at a time, that is, one row of parallelized data. That is, first, for row 0 (bits A0 (0), A0 (1), A0 (2), A0 (3)), bit A0 (1) is deleted and bits A0 (0), A0 ( 2) Redistribute A0 (3) to columns 0-2. The output position control unit 133 notifies the initial position calculation unit 134 of the final bit position information indicating the value of the column 2 of the last bit A0 (3), and the initial position indicating the column 3 of the first bit of the next n bits. Information F _ini is received from the initial position calculation unit 134. Thereafter, the output position control unit 133 deletes bits A0 (4) and A0 (7) for row 1 (bits A0 (4), A0 (5), A0 (6), A0 (7)). , Bits A0 (5), A0 (6) are redistributed into columns 3, 0. The initial position information F _ini is the same as that described in connection with the first embodiment.

The output position control unit 133 outputs the bits of each column obtained by rearrangement, that is, rate dematching, from the radio frame 0 to the storage units 135 _{0 to} 135 _n−1 of the storage device 135. When outputting bits to the storage device 135, the output position control unit 133 stores the bits in the storage units 135 _{0 to} 135 _n−1 to which the same column numbers as the column numbers obtained by rate dematching are given. That is, the first deinterleaving is not performed at this stage.

Further, as shown in FIG. 19, the parallel processing unit 131 receives bits A1 (0), A1 (1), A1 (2),..., A1 (15) input serially in the wireless frame 1. In accordance with the input order, parallelization is performed on four columns (column 0 to column 3), which is the number n of columns of the first deinterleave. The D calculation unit 132 obtains bits to be deleted by a variable calculation / iteration / deletion determination algorithm. According to the puncture pattern of FIG. 19, the bits A1 (2), A1 (5), A1 (7), A1 (9), A1 (12) are deleted. The output position control unit 133 deletes the bit specified by the puncture pattern, and _raises each bit as necessary based on the cumulative repetition / deletion bit number D and the initial position information F _ini. Sort the bit data. For example, the output position (output column) of the last bit A0 (15) of the radio frame 0 is the column 2 because the bit A1 (0) is output to the column 3 position. Bit A1 (10) has the output position (output string) of the last bit A0 (15) of radio frame 0 as column 2, and further 4 bits (bit A1 (2), Since A1 (5), A1 (7), and A1 (9)) are deleted, the output position is advanced by 1 bit, and output to the position of column 1 that is 1 bit higher than the original column 2. Become. Subsequent to the bit obtained by rate dematching from the radio frame 0, the output position control unit 133 transmits the bit obtained by rate dematching from the radio frame 1 to each of the storage units 135 _{0 to} 135 _n−1 of the storage device 135. Output.

As shown in FIG. 20, the same processing is executed for the bits A2 (0), A2 (1), A2 (2),..., A2 (15) of the radio frame 2, and further as shown in FIG. In addition, the same processing is executed for the bits A3 (0), A3 (1), A3 (2),..., A3 (15) of the wireless frame 2. In this way, all bits obtained (reduced) by the rate dematching process from all the bits constituting n radio frames (four radio frames 0 to 3 in the illustrated example) received in the same reception cycle are stored. After being stored in the device 135, the column data reading order control unit 150 reads all the bits from the storage units 135 _{0 to} 135 _n−1 of the storage device 135 and combines them. As a result, radio frame combination is performed. At the time of this reading, the column data reading order control unit 150 performs the first deinterleaving by exchanging at least two predetermined columns among the columns obtained by rate matching.

For example, as shown in FIG. 21, first, the bit A0 of column 0 from the storage unit 135 ₀ column 0 (0), A0 (6 ), A0 (12), A1 (1), A1 (8), A1 (14) , A2 (3), A2 (9), A2 (15), A3 (5), A3 (11) are read out by the column data reading order control unit 150. Next, bits A0 (3), A0 (9), A0 (15), A1 (4), A1 (11), A2 (0), A2 (6), A2 (12), A3 (2) in column 2 ), A3 (8), A3 (13) are read by the column data reading order control unit 150. Further, the bits A0 (2), A0 (8), A0 (14), A1 (3), A1 (10), A1 (15), A2 (4), A2 (10), A3 (1) in column 1 , A3 (7), A3 (12), and finally bits A0 (5), A0 (11), A1 (0), A1 (6), A1 (13), A2 (2), A2 (7 in column 3 ), A2 (13), A3 (4), A3 (9), and A3 (15) are read out by the column data reading order control unit 150. In this way, rate dematching, first deinterleaving and radio frame combining are completed.

  22 to 25 show examples of processing in which bits are repeated (repetition) in rate dematching processing, and show processing of radio frames 0 to 3, respectively. Also in this example, the number of first de-interleaved columns n (= the number of radio frames received in the same reception cycle) is 4, the number of bits per radio frame is 16, and is input to the parallel processing unit 131 at a time. Assume that the number of bits (number of input bits k) is 4 × 16 = 64 and the number of bits to be repeated in the rate dematching process per radio frame is 5.

  First, as shown in FIG. 22, the parallel processing unit 131 inputs the bits A0 (0), A0 (1), A0 (2),..., A0 (15) input serially of the wireless frame 0. According to the order, the first deinterleaved column number n is parallelized to 4 columns (column 0 to column 3).

  The D calculation unit 132 obtains a bit to be repeated by a variable calculation / iteration / deletion determination algorithm. According to the repetition pattern of FIG. 22 (which bit is to be repeated is specified by the repetition instruction from the D calculation unit 132), bits A0 (1), A0 (4), A0 (7), A0 (10). , A0 (13) is repeated. The output position control unit 133 repeats the bits specified by this repetition pattern, and lowers each bit as necessary based on the cumulative repetition / deletion bit number D, thereby arranging the bit data. Change. For example, for bit A0 (3), 1 bit (bit A0 (1)) has been repeated in the rate dematching process so far, so the output position (output column) is lowered by 1 bit, and the original column 3 to 1 It is output to the position of column 0 where the bit is lowered. Since bit A0 (9) has been repeated 3 bits (bits A0 (1), A0 (4), A0 (7)) in the rate dematching process so far, the output position is lowered by 3 bits. , The data is output to the position of column 0, which is 3 bits lower than the original column 1.

More precisely, the output position control unit 133 performs rate dematching on n bits at a time, that is, one row of parallelized data. That is, first, bit S (1) is added to row 0 (bits S (0), S (1), S (2), S (3)), and bits S (0), S ( 1) Redistribute S (1), S (2), S (3) to columns 0-3 and column 0 of the next row. The output position control unit 133 notifies the initial position calculation unit 134 of the final bit position information indicating the value of the column 0 of the final bit S (3), and the initial position indicating the column 1 of the first bit of the next n bits. Information F _ini is received from the initial position calculation unit 134. Thereafter, the output position control unit 133 repeats bits S (4) and S (7) for row 1 (bits S (4), S (5), S (6), and S (7)). , Bits S (4), S (4), S (5), S (6), S (7), S (7) are redistributed into columns 1-3 and columns 0-2 of the next row.

The output position control unit 133 outputs the bits of each column obtained by rearrangement, that is, rate dematching, from the radio frame 0 to the storage units 135 _{0 to} 135 _n−1 of the storage device 135. When outputting bits to the storage device 135, the output position control unit 133 stores the bits in the storage units 135 _{0 to} 135 _n−1 to which the same column numbers as the column numbers obtained by rate dematching are given. That is, the first deinterleaving is not performed at this stage.

Further, as shown in FIG. 23, the parallel processing unit 131 converts the bits A1 (0), A1 (1), A1 (2),... In accordance with the input order, parallelization is performed on four columns (column 0 to column 3), which is the number n of columns of the first deinterleave. The D calculation unit 132 obtains a bit to be repeated by a variable calculation / iteration / deletion determination algorithm. According to the repetition pattern of FIG. 23, bits A1 (2), A1 (5), A1 (7), A1 (9), and A1 (12) are repeated. The output position control unit 133 repeats the bits specified by the repetition pattern, and lowers each bit as necessary based on the cumulative repetition / deletion bit number D and the initial position information F _ini. This sorts the bit data. For example, since the output position (output column) of the last bit A0 (15) of the radio frame 0 is the column 0, the bit A1 (0) is output to the column 1 position. Further, the output position (output string) of the last bit A0 (15) of the radio frame 0 is the column 0, and the bit A1 (10) is 4 bits (bit A1 (2), Since A1 (5), A1 (7), and A1 (9)) are repeated, the output position is lowered by 1 bit and output to the position of column 3 that is 1 bit lower than the original column 2. Become. Subsequent to the bit obtained by rate dematching from the radio frame 0, the output position control unit 133 transmits the bit obtained by rate dematching from the radio frame 1 to each of the storage units 135 _{0 to} 135 _n−1 of the storage device 135. Output.

As shown in FIG. 24, the same processing is executed for the bits A2 (0), A2 (1), A2 (2),..., A2 (15) of the radio frame 2, and further as shown in FIG. In addition, the same processing is executed for the bits A3 (0), A3 (1), A3 (2),..., A3 (15) of the wireless frame 2. In this way, all bits obtained (increased) by rate dematching processing from all bits constituting n radio frames (four radio frames 0 to 3 in the illustrated example) received in the same reception cycle are stored. After being stored in the device 135, the column data reading order control unit 150 reads all the bits from the storage units 135 _{0 to} 135 _n−1 of the storage device 135 and combines them. As a result, radio frame combination is performed. At the time of this reading, the column data reading order control unit 150 performs the first deinterleaving by exchanging at least two predetermined columns among the columns obtained by rate matching.

For example, as shown in FIG. 25, first, the bit A0 of column 0 from the storage unit 135 ₀ column 0 (0), A0 (3 ), A0 (6), A0 (9), A0 (12), A0 (15) , A1 (2), A1 (5), A1 (8), A1 (11), A1 (14), A2 (1), A2 (5), A2 (8), A2 (11), A2 (14) , A3 (0), A3 (3), A3 (6), A3 (10), A3 (13) are read out by the column data reading order control unit 150. Next, bits A0 (1), A0 (4), A0 (7), A0 (10), A0 (13), A1 (1), A1 (4), A1 (7), A1 (9) in column 2 ), A1 (12), A2 (0), A2 (3), A2 (6), A2 (9), A2 (12), A2 (15), A3 (2), A3 (5), A3 (8) ), A3 (11), A3 (14) are read by the column data reading order control unit 150. Furthermore, bits A0 (1), A0 (4), A0 (7), A0 (10), A0 (13), A1 (0), A1 (3), A1 (6), A1 (9) in column 1 , A1 (12), A1 (15), A2 (2), A2 (5), A2 (8), A2 (11), A2 (14), A3 (1), A3 (4), A3 (7) , A3 (10), A3 (14), and finally bits A0 (2), A0 (5), A0 (8), A0 (11), A0 (14), A1 (2), A1 (5) in column 3 ), A1 (7), A1 (10), A1 (13), A2 (1), A2 (4), A2 (7), A2 (10), A2 (13), A3 (0), A3 (3 ), A3 (6), A3 (9), A3 (12), A3 (15) are read out by the column data reading order control unit 150. In this way, rate dematching, first deinterleaving and radio frame combining are completed.

Similar to the D calculation unit 32 of the first embodiment, the D calculation unit 132 uses the parameters e _ini , e _plus , and e _minus and performs rate dematching by the variable calculation / iteration / deletion determination algorithm shown in FIG. At the same time as determining the bits to be repeated or deleted, the cumulative repetition / deletion bit number D is obtained. Similarly to the D calculation unit 32 of the first embodiment, the D calculation unit 132 has n D (= e _plus number) calculation units 39 _{0 to} 39 _n−1 , n pieces as shown in FIG. It includes a repetition / deletion determination unit 40 ₀ to 40 _n−1 , and a D (= e _plus number) storage unit 41 for the last bit. These functions are as described above in connection with the first embodiment. Accordingly, each of the D calculation units 39 _{0 to} 39 _n-1 executes the procedure corresponding to step ST30 to step ST32 in the variable calculation / iteration / deletion determination algorithm for the corresponding column, and cumulative iteration / deletion of each column. The number of bits D (i), D (i−1),... D (i + n−1) is calculated and notified to the output position control unit 133. The iteration / deletion determination units 40 ₀ to 40 _n-1 execute the procedure corresponding to step ST33 to step ST36 in the variable calculation / iteration / deletion determination algorithm for the corresponding columns, and repeat or delete the bits of each column. In the case of a conclusion that it should be, an iteration / deletion instruction is supplied to the output position control unit 133. By having n D calculation units 39 _{0 to} 39 _n-1 and n iteration / deletion determination units 40 ₀ to 40 _n−1 , the D calculation unit 132 can display one line (n pieces) in FIGS. The variable calculation / iteration / deletion decision algorithm can be applied to the same bit).

Similar to the output position control unit 33 of the first embodiment, the output position control unit 133 includes n adders 33A _{0 to} 33 _n−1 and n output position calculation units as shown in FIGS. 36 _{0 to} 36 _n−1 , n write control units (redistribution control units) 37 _{0 to} 37 _n−1 , and a bit storage output unit 38. These operate in substantially the same manner as described above with reference to FIGS. That is, the output position calculation units 36 _{0 to} 36 _n−1 respectively correspond to the number of cumulative repetition / deletion bits D (i) and D (i−) corresponding to each of the plurality of bits distributed to the columns by the parallel processing unit 131. 1),... D (i + n-1) is calculated to calculate a column to be redistributed. Then, the write control units 37 _{0 to} 37 _n-1 repeat or delete each of the plurality of bits distributed to the columns by the parallel processing unit 131 by the corresponding repetition / deletion determination units 40 ₀ to 40 _n-1 . When it is determined that it should be, it is repeated or deleted, and redistributed to the columns calculated by the output position calculation units 36 _{0 to} 36 _n−1 .

Also in this embodiment, regardless of whether the rate dematching process is bit repetition or bit deletion, the bit storage output unit 38 uses the final bit position information described above as the initial position calculation unit 134 according to the contents of the bit storage unit 38A. Notify Similar to the initial position calculation unit 34 of the first embodiment, the initial position calculation unit 134 performs modulo calculation based on the final bit position information and calculates the next initial position information F _ini . The content of the initial position calculation unit 134 is reset every time one TTI expires, and the initial position information F _ini for the calculation of the first bit thereafter becomes zero. In other words, during one TTI (during the processing of n radio frames), the initial position calculation unit 134 continues to calculate the initial position information F _ini that is effectively used. Therefore, the first bit of the next radio frame is output to the next column after the last bit output column of the rearranged radio frame. For example, the first bit A1 (0) of the radio frame 1 in FIG. 19 is output to the column 3 next to the output column 2 of the last bit A0 (15) of the radio frame 1.

Unlike Embodiment 1, the output position control unit 133 does not perform the first deinterleaving when outputting bits to the storage units 135 _{0 to} 135 _n−1 of the storage device 135. In the bit storage output unit 38, when the first clock pulse after completion of the bit writing to the bit storage unit 38A is supplied to the bit storage output unit 38, the data output unit 38B for the columns 0 to n-1 corresponds. N bits are read out from the bit storage unit 38A to be written and written into the storage units 135 _{0 to} 135 _n−1 . At this time, the columns for the first interleaving are not exchanged. For example, when the number of the first interleaving columns (= the number of radio frames created at the same time) n = 4, the storage of the column 0 in the storage device 135 is performed. bits of the column 0 of the parts 135 ₀ bit storage unit 38A, the column bit storage unit 135 ₁ column 1 in the 1 bit in column 2 in the storage unit 135 ₂ of the column 2, the storage unit 135 ₃ columns 3 Write the column 3 bit. After reading the bits, the contents of the bit storage unit 38A are erased.

When the next clock pulse is supplied to the bit storage output unit 38, n bits in the columns _{n to 2n-1} are transferred from the bit storage unit 38A to the storage units 135 _{0 to} 135 _n-1 . For example, in the case of the first interleave sequence number n = 4, and the storage unit 135 ₀ of column 0 of the storage device 135 of column 4 of bit storage unit 38A bits, column 5 in the storage unit 135 ₁ of the column 1 bits, bits of the column 6 in the storage unit 135 ₂ of the column 2, the storage unit 135 ₃ columns 3 writes the bits of the column 7. When the next clock pulse is supplied to the bit storage output unit 38, n bits in the columns 2n to 3n _-1 are transferred from the bit storage unit 38A to the storage units 135 _{0 to} 135 _n-1 .

As described above, the column data reading order control unit 150 (FIG. 17) reads all bits from the storage units 135 _{0 to} 135 _n−1 of the storage device 135 to perform radio frame combination, and column obtained by rate matching. The first interleaving is performed by exchanging predetermined columns. The column replacement may be performed so that the original bit stream can be restored from the result of the first interleaving in accordance with Subclause 4.2.5.2 of 3GPP TS25.212. More specifically, if the TTI = 20 ms, ie n = 2, the order of the columns 0,1, after reading all the bits of the column 0 from the storage unit 135 ₀ column 0, from the storage unit 135 ₁ of the column 1 Read all the bits in column 1. If TTI = 40 ms, i.e. n = 4 (illustrated example), the order of the columns 0,2,1,3, after reading all the bits of the column 0 from the storage unit 135 ₀ column 0, row 2 storage unit read all bits of the column 2 from 135 _2, followed by reading all bits of the column 1 from the storage unit 135 ₁ of the column 1, reading out all bits of the column 3 from the storage unit 135 ₃ the last column 3. If TTI = 80 ms, that is, n = 8, all bits are read in the order of columns 0, 4, 2, 6, 1, 5, 3, and 7.

As described above, according to the second embodiment, the parallel processing unit 131 extracts, from the data bit stream to be received, the same number of bits as the number of a plurality of radio frames received in the same reception cycle. The bits are regularly distributed to a plurality of columns equal to the number of the radio frames. Further, the parameter calculation unit 130 calculates rate _dematching basic parameters e _ini , e _plus , and e _minus . Further, the D calculation unit 132, based on the bit number m in the data bit stream assigned to each bit distributed to the column and the basic parameters e _ini , e _plus , e _minus , a plurality of bits distributed to the column Of the bits to be repeated or deleted. Furthermore, for each bit distributed to the column, the D calculation unit 132 determines the number of preceding bits to be repeated or deleted in the data bit stream and the number of bits when the bit is repeated or deleted. The cumulative repetition / deletion bit number D, which is the total number, is calculated. The output position control unit 133 functions as a rate dematching unit, and repeats or outputs bits determined to be repeated or deleted by the D calculation unit 132 among the plurality of bits distributed to the columns by the parallelization processing unit 131. In addition to deleting, a plurality of bits are redistributed to a plurality of columns based on the cumulative repetition / deletion bit number D. The column data reading order control unit 150 functions as a first deinterleave / radio frame combining unit, and reads a plurality of columns obtained by redistribution by the output position control unit 133 while exchanging at least two of them. And combine. In this way, by redistributing a plurality of bits into a plurality of columns based on the cumulative repetition / deletion bit number D, the bit redistribution can be completed at a high speed, and the plurality of bits obtained by the redistribution can be obtained. The first deinterleaving is completed only by exchanging bits of at least two of the columns. Therefore, the bit redistribution and the first deinterleaving can be completed at a higher speed than the case of the bit redistribution and the first deinterleaving based on the bit itself obtained by the rate dematching. As described above, it is possible to further speed up the decoding process while complying with W-CDMA.

The D calculation unit 132 also has a plurality of repetition / deletion determination units 40 ₀ to 40 for determining in parallel whether or not each of the plurality of bits distributed to the columns by the parallelization processing unit 131 should be repeated or deleted. _{with n-1} . Further, the D calculation unit 132 calculates the cumulative number of repeated / deleted bits D (i), D (i−1),... D (i + n−1) for each of the plurality of bits distributed to the columns by the parallel processing unit 131. D calculation units 39 _{0 to} 39 _n-1 for calculating in parallel are provided. The output position control unit 133 as a rate dematching unit, for each of a plurality of bits distributed to the column by the parallel processing unit 131, corresponds to the number of cumulative repetition / deletion bits D (i) and D (i-1). ,... D (i + n−1) based on a plurality of output position calculation units 36 _{0 to} 36 _n−1 that calculate columns to be redistributed, and a plurality of bits distributed to the columns by the parallel processing unit 131. each calculated by repeated or is deleted when it is determined that it should repeated or deleted in the corresponding iteration / deletion determining unit 40 ₀ ~40 _n-1, the output position calculator 36 ₀ ~36 _n-1 Are provided with a plurality of write control units 37 _{0 to} 37 _n-1 for redistribution to the arranged columns. According to this configuration, the parallelized bits are rate-dematched at the same time, and the decoding process is further performed by redistributing these bits to the columns at the same time in consideration of the cumulative repetition / deletion bit number D for each bit. Can be speeded up.

The output position control unit 133 as a rate dematching unit includes a plurality of bit storage units 38A larger than the number of columns, and a data output unit 38B that reads bits from each bit storage unit 38A and stores them in a radio frame. Each of the output position calculation units 36 _{0 to} 36 _n-1 calculates the position of the bit storage unit 38A where each bit is stored, and each of the write control units 37 _{0 to} 37 _n-1 repeats the bit. Alternatively, each bit is stored in the bit storage unit 38A at the position calculated by the output position calculation units 36 _{0 to} 36 _n-1 and the data output unit 38B has the same number of bits as the number of radio frames at a time. Are read from bit storage 38A and these bits are redistributed into columns. When the rate matching processing is bit repetition, bits exceeding the number n of columns are output from the write control units 37 _{0 to} 37 _n−1, but these bits are stored in a plurality of bit storage units 38A having a number larger than the number of columns. By doing so, overflow can be prevented.

  Further, the decoding processing device of the wireless communication device is configured to perform the first bit among the plurality of bits to be redistributed next based on the column in which the last bit among the plurality of bits redistributed immediately before is redistributed. Is further provided with an initial position calculation unit 134 for calculating an initial column to be redistributed, and the output position control unit 133 redistributes a plurality of bits to be redistributed next to a plurality of columns starting from the initial column. Therefore, the bits can be redistributed smoothly and at high speed.

Embodiment 3 FIG.
A coding processing apparatus for a wireless communication apparatus according to Embodiment 3 of the present invention is provided in a base station of a wireless communication system based on W-CDMA, and performs rate matching (step ST12) for downlink data transmission in FIG. 1 and first interleaving. (Step ST13) and radio frame division (step ST14). FIG. 26 is a functional block diagram showing an encoding processing apparatus according to Embodiment 3 of the present invention. Illustration of other components of the wireless communication device is omitted.

  The third embodiment is applied when bit deletion is used in rate matching processing when turbo coding is performed in the previous stage. In the turbo coding, 3 bits of information bits (hereinafter referred to as systematic bits S) input to the turbo encoder and two sequences of check bits (hereinafter referred to as parity bits P1 and P2) obtained by the coding. A series of bits is obtained. According to Subclause 4.2.7.4 of 3GPP TS25.212, when bit deletion is used in rate matching processing for turbo encoded data, systematic bit S must not be deleted, and parity bits P1, P2 Only deleted. Different rate matching patterns are applied to the parity bits P1 and P2. According to the specification, in the bit deletion rate matching processing of turbo-encoded data, the turbo code is bit-separated to obtain a systematic bit S sequence and parity bit P1 and P2 sequences, and parity The bits P1 and P2 are deleted in parallel, and then the bits S, P1 and P2 are combined by bit collection. The third embodiment speeds up this complicated rate matching process, first interleaving, and radio frame division by an improved method.

As shown in FIG. 26, the encoding processing apparatus includes a parameter calculation unit 30, a bit division unit 42, parallel processing units 43A, 43B, and 43C, an initial position calculation unit 44, and a D _p1 (= e _plus number) calculation unit. (First deletion determination unit) 45, D _p2 (= e _plus number) calculation unit (second deletion determination unit) 46, output position control unit (rate matching / first interleaving unit) 47, and storage device 48. . The parameter calculation unit 30 is actually a CPU or DSP of a wireless communication device, and operates according to a program. The parallel processing units 43A, 43B, and 43C, the initial position calculation unit 44, the D _p1 calculation unit 45, the D _p2 calculation unit 46, and the output position control unit 47 are each part of an FPGA or an LSI. The storage device 48 is a RAM.

As in the first embodiment, the parameter calculation unit 30 calculates e _ini , e _plus , and e _minus that are parameters necessary for the rate matching process, and uses these parameters as the D _p1 calculation unit 45 and the D _p2 calculation unit 46. Notify

Further, the known number of bits k and the number of first interleaved columns (equal to the number of radio frames created simultaneously in this embodiment) n are the bit division unit 42, parallel processing units 43A, 43B, 43C, D _{The p1} calculation unit 45, the _Dp2 calculation unit 46, and the output position control unit 47 are notified in advance.

  The bit division unit 42 includes input bits S (0), P1 (0), P2 (0),..., S (i) that are transmission targets encoded by a turbo encoder (not shown). , P1 (i), P2 (i),..., S (k-1), P1 (k-1), and P2 (k-1) streams are input. The number of bits in the turbo code is 3k. The bit division unit 42 uses a known method to input the bit stream of the turbo code, and systematic bits S (0), ..., S (i), ..., S (k-1), parity bits P1 (0), ..., P1 (i), ..., P1 (k-1), parity bits P2 (0), ..., P2 (i), ..., P2 (k-1). Divide into

  The systematic bits S (0),..., S (i),..., S (k−1) output from the bit division unit 42 are input to the parallelization processing unit 43A. The parallelization processing unit 43A generates the number of first interleaved columns n (simultaneously in this embodiment) from the systematic bits S (0), S (1),... S (k−1) according to the input order. Bits S (i), S (i + 1),..., S (i + n-1) are taken out, and these bits are distributed to n columns at a time, ie, n in parallel. Bits S (i), S (i + 1),..., S (i + n−1) are supplied in parallel to the output position controller 47. n is one of 2, 4, and 8. Since the time length of one radio frame is 10 ms, as defined in Subclause 4.2.5.2 of 3GPP TS25.212, n = 2 when TTI = 20 ms, n = 4 when TTI = 40 ms, and TTI = If 80 ms, n = 8.

  Parity bits P1 (0),..., P1 (i),..., P1 (k−1) output from the bit division unit 42 are input to the parallel processing unit 43B. The parallel processing unit 43B supplies n bits P1 (i), P1 (i + 1),..., P1 (i + n−1) to the output position control unit 47 in parallel by the same processing. Parity bits P2 (0),..., P2 (i),..., P2 (k−1) output from the bit division unit 42 are input to the parallel processing unit 43C. The parallel processing unit 43C supplies n bits P2 (i), P2 (i + 1),..., P2 (i + n−1) to the output position control unit 47 in parallel by similar processing. i is 0, n, 2n, 3n,. . . Is an arbitrary integer. In the turbo code bit stream, the systematic bit S (i) is the 3i + 1th bit, the parity bit P1 (i) is the 3i + 2nd bit, and the parity bit P2 (i) is the 3i + 3rd bit.

  Since the parallel processing units 43A, 43B, and 43C simultaneously perform the parallel processing described above, systematic bits S (i), S (i + 1),..., S (i + n−1), parity bits P1 (i), P1 , P1 (i + n-1), parity bits P2 (i), P2 (i + 1),..., P2 (i + n-1) are simultaneously output from the parallel processing units 43A, 43B, 43C to the output position control unit 47. To be supplied. These 3n bits are simultaneously processed in parallel in the output position control unit 47.

The output position control unit 47 collectively performs rate matching and first interleaving based on information supplied from the D _p1 calculation unit 45, the D _p2 calculation unit 46, and the initial position calculation unit 44. This collective processing will be described in detail later.

The D _p1 calculation unit 45 uses the bit number assigned to each parity bit P1 and the parameters e _ini , e _plus , e _minus and uses the variable calculation / iteration / deletion determination algorithm shown in FIG. 7 and described above with reference to the first embodiment. , P1 (i), P1 (i + 1),..., P1 (i + n−1) are determined by rate matching, and at the same time, each bit P1 (i), P1 (i + 1),. , P1 (i + n−1), the cumulative number of deleted bits D _p1 (i), D _p1 (i + 1),..., D _p1 (i + n−1) is obtained. The cumulative deletion bit number D _p1 indicates the number of times the parameter e _plus is incremented when the variable calculation / iteration / deletion decision algorithm is applied to each bit. The cumulative number of deleted bits D _p1 is the number of preceding bits deleted in the bit stream and the number of bits deleted for each bit P1 (i), P1 (i + 1),..., P1 (i + n−1). In this case, the total number of bits (1) is indicated, which is useful for appropriately redistributing each bit into the same number of columns as the number of bits decreases. The D _p1 calculation unit 45 supplies the output position control unit 47 with a deletion instruction specifying the bits to be deleted by rate matching and the cumulative deletion bit number D _p1 (= e _plus number).

At the same time, the D _p2 calculation unit 46 uses the bit number assigned to each parity bit P2 and the parameters e _ini , e _plus , e _minus to perform the parity bit P2 (i), P2 (i + 1),..., P2 (i + n-1) are determined by rate matching, and at the same time, the bits P2 (i), P2 (i + 1), ..., P2 (i + n-1) are determined. The cumulative number of deleted bits D _p2 (i), D _p2 (i + 1),..., D _p2 (i + n−1) is obtained. Further, the D _p2 calculation unit 46 supplies the output position control unit 47 with a deletion instruction specifying the bits to be deleted by rate matching and the cumulative deletion bit number D _p2 (= e _plus number).

Similarly to the D calculation unit 32 of the first embodiment, each of the D _p1 calculation unit 45 and the D _p2 calculation unit 46 includes n D (= e _plus number) calculation units 39 _{0 to} 39 as shown in FIG. _n-1 , n repetition / deletion determination units 40 ₀ to 40 _n-1 , and D (= e _plus number) storage unit 41 of the last bit. These functions are as described above in connection with the first embodiment. Accordingly, each of the D _p1 calculating unit 45 and the D _p2 calculating unit 46 includes n parity bits P1 (i), P1 (i + 1),..., P1 (i + n−1) or n parity bits P2 (i). , P2 (i + 1),..., P2 (i + n-1), the variable calculation / iteration / deletion determination algorithm can be applied simultaneously.

Based on the deletion instruction, the output position control unit 47 selects one of the n parity bits P1 (i), P1 (i + 1),..., P1 (i + n−1) and the n parity bits P2 (i), P2 (i + 1), ..., it deletes the P2 (i + n-1) , the cumulative delete bits _{D p1 (i), D p1} (i + 1), ..., D p1 (i + n-1) and cumulative number of deleted bits D _p2 ( i), D _p2 (i + 1),..., D _p2 (i + n−1) are used to calculate the output positions (output strings) of the systematic bit S, the parity bit P1, and the parity bit P2. The calculation of the output position is performed by calculating n systematic bits S (i), S (i + 1),..., S (i + n−1), n parity bits P1 (i), P1 (i + 1),. i + n−1) and n parity bits P2 (i), P2 (i + 1),..., P2 (i + n−1). This results in a new redistribution of bits into n columns with deletion and bit collection.

Further, the output position control unit 47 outputs a maximum of n bits among the bits subjected to rate matching and bit correction in this manner to the storage device 48 at a time. The storage device 48 is provided with _n storage units 48 _{0 to} 48 _n−1 . These storage units 48 _{0 to} 48 _n-1 correspond to n radio frames (frame 0 to frame n-1) created simultaneously, and each of the storage units 48 _{0 to} 48 _n-1 It is possible to store at least a number of bits corresponding to the length of the radio frame, and storing the bits in the storage device 48 results in storing the bits in a plurality of radio frames. When outputting bits to the storage device 48, the output position controller 47 performs the first interleaving by exchanging at least two predetermined columns among the columns obtained by rate matching and bit correction.

Along with rate matching and bit collection, the output sequence of each bit calculated by the output position control unit 47 is different from the sequence number given by the parallel processing units 43A, 43B, and 43C. Therefore, the output position control unit 47 determines the position of the output sequence on the n columns from which the maximum 3n bits to be subjected to rate matching and bit correction processing next are redistributed. Of the last bit (for example, P2 (i + n-1)) is notified to the initial position calculation unit 44 of the last bit position information indicating the value of the output string on the nth column. Based on the value of the output sequence of the last bit indicated in the last bit position information, the initial position calculation unit 44 sets a value that specifies the output sequence of the first 3n bits (for example, S (i)). The initial position information F _ini indicating this value is returned to the output position control unit 47. Based on the initial position information F _ini , the output position control unit 47 redistributes 3n bits to be processed next to a plurality of columns starting from the initial column indicated in the initial position information F _ini . In this way, the output position control unit 47 redistributes the bits smoothly and at high speed.

27 and 28 are block diagrams showing specific circuit examples of the output position control unit 47 of FIG. As shown in FIGS. 27 and 28, the output position control unit 47 includes 3n adders 52A _{0 to} 52A _n−1 , 52B _{0 to} 52B _n−1 , 52C _{0 to} 52C _n−1 , and 3n outputs. Position calculation units 49A _{0 to} 49A _n−1 , 49B _{0 to} 49B _n−1 , 49C _{0 to} 49C _n−1 , 3n write control units (redistribution control units) 50A _{0 to} 50A _n−1 , 50B ₀ to 50B _n−1 , 50C _{0 to} 50C _n−1 , and a bit storage output unit 51 are provided.

The adders 52A _{0 to} 52A _n−1 , the output position calculation units 49A _{0 to} 49A _n−1 and the write control units 50A _{0 to} 50A _n−1 are systematic bits S (i), S (i + 1),. i + n-1), that is, for each of columns 0 to n-1, subscripts 0 to n-1 correspond to columns 0 to n-1, respectively. The adders 52B _{0 to} 52B _n−1 , the output position calculation units 49B _{0 to} 49B _n−1, and the write control units 50B _{0 to} 50B _n−1 have parity bits P1 (i), P1 (i + 1),. i + n-1), that is, for each of columns 0 to n-1, subscripts 0 to n-1 correspond to columns 0 to n-1, respectively. The adders 52C _{0 to} 52C _n−1 , the output position calculation units 49C _{0 to} 49C _n−1, and the write control units 50C _{0 to} 50C _n−1 have parity bits P2 (i), P2 (i + 1),. i + n-1), that is, for each of columns 0 to n-1, subscripts 0 to n-1 correspond to columns 0 to n-1, respectively.

  FIGS. 29 and 30 are the same as FIGS. 27 and 28, and the number of first interleaved columns (the number of radio frames created simultaneously) n = 4, and parity bit P1 (i) and parity bit P2 ( i + 1) shows the flow of processing to be deleted. The specific operation of the output position control unit 47 will be described below with reference to FIGS.

The systematic bits S (i), S (i + 1),..., S (i + n−1) supplied from the parallel processing unit 43A are given to the write control units 50A _{0 to} 50A _n−1 . Parity bits P1 (i), P1 (i + 1),..., P1 (i + n−1) supplied from the parallel processing unit 43B are given to the write control units 50B _{0 to} 50B _n−1 . Parity bits P2 (i), P2 (i + 1),..., P2 (i + n−1) supplied from the parallel processing unit 43C are given to the write control units 50C _{0 to} 50C _n−1 .

The above-described initial position information F _ini is supplied from the initial position calculation unit 44 to the adders 52A _{0 to} 52A _n−1 , 52B _{0 to} 52B _n−1 , 52C _{0 to} 52C _n−1 . For 3n bits (n systematic bits S, n parity bits P1, n parity bits P2) of a row supplied to the output position control unit 47 first in the bitstream, initial position information F _ini is 0, and for the subsequent rows, the initial position information F _ini indicates the output sequence (output position) of the first bit among the 3n bits. As in the first embodiment, the initial position calculation unit 44 is notified of final bit position information indicating the position of the last bit string of the rate matching processing result immediately before in the output position control unit 47. The initial position calculation unit 44 adds the value of the last bit column +1 indicated in the last bit position information, and divides the result of the addition by the number n of the first interleave columns (modulo operation result). Store as F _ini . For example, if the number of columns of the first interleave n = 4 and the last bit position of the previous row is column 3, (3 + 1) mod 4 = 0 is the initial position information F _ini .

The adders 52A _{0 to} 52A _n−1 , 52B _{0 to} 52B _n−1 , 52C _{0 to} 52C _n−1 add the column number value C to the initial position information F _ini . The addition result is loaded to the output position calculation unit as position information of each bit. In the figure, F1 (i),..., F1 (i + n−1) is position information of systematic bits S (i),..., S (i + n−1), and output position calculation units 49A _{0 to} 49A. loaded into _n-1 . F2 (i), ···, F2 (i + n-1) parity bits P1 (i), ···, P1 (i + n-1) is the position information of the output position calculation section 49B ₀ ~49B _n-1 Is loaded. F3 (i), ···, F3 (i + n-1) parity bits P2 (i), ···, P2 (i + n-1) is the position information of the output position calculation section 49C ₀ ~49C _n-1 Is loaded.

Column number values C (0), C (1),..., C (3n−1) are set as follows according to the number of columns of the first interleave (= number of radio frames) n.
When n = 2, C (0) = 0 for systematic bit S, C (n−1) = C (1) = 3, C (n) = C (2) = 1 for parity bit P1, C ( 2n-1) = C (3) = 4, C (2n) = C (4) = 2 for parity bit P2, and C (3n-1) = C (5) = 5.
When n = 4, C (0) = 0, C (1) = 3, C (2) = 6, C (n−1) = C (3) = 9 for the systematic bit S, and parity bit P1 C (n) = C (4) = 1, C (5) = 4, C (6) = 7, C (2n-1) = C (7) = 10, C (2n) = C for parity bit P2 (8) = 2, C (9) = 5, C (10) = 8, C (3n-1) = C (11) = 11.
When n = 8, C (0) = 0, C (1) = 3, C (2) = 6, C (3) = 9, C (4) = 12, C (5) for the systematic bit S = 15, C (6) = 18, C (n-1) = C (7) = 21, C (n) = C (8) = 1, C (9) = 4, C (10) for the parity bit P1 ) = 7, C (11) = 10, C (12) = 13, C (13) = 16, C (14) = 19, C (2n-1) = C (15) = 22, and parity bit P2 C (2n) = C (16) = 2, C (17) = 5, C (18) = 8, C (19) = 11, C (20) = 14, C (21) = 17, C (22 ) = 20, C (3n−1) = C (23) = 23.

In this way, the column number value C is a column in which each bit is arranged in the order of the systematic bit S, the parity bit P1, and the parity bit P2 when there is no bit to be deleted and the initial position information F _ini is 0. Indicates the number.

The output position calculation unit includes position information F1 (i), ..., F1 (i + n-1), F2 (i), ..., F2 (i + n-1), F3 (i), ..., F3 (i + n-1) is loaded respectively. Furthermore, the cumulative deletion bit numbers D _p1 and D _p2 corresponding to each column are loaded into the output position calculation units 49A _{0 to} 49A _n−1 , 49B _{0 to} 49B _n−1 , 49C _{0 to} 49C _n−1 , respectively ( _Dp1 (i), _Dp1 (i + 1), ..., _Dp1 (i + n-1), _Dp2 (i), _Dp2 (i + 1), ..., _Dp2 (i + n-1)). Each of the output position calculation units 49A _{0 to} 49A _n−1 , 49B _{0 to} 49B _n−1 , 49C _{0 to} 49C _n−1 has the position information F loaded therein and the cumulative number of deleted bits D _p1 and D _p2 . Based on this, the output position is calculated as follows. The output positions calculated by the output position calculation units 49A _{0 to} 49A _n−1 , 49B _{0 to} 49B _n−1 , 49C _{0 to} 49C _n−1 are considered in consideration of the preceding bit and rate deletion by rate matching processing. This is an output string to which the bits are to be distributed, and is a column 0 to 4n-1 assigned to the bit storage unit 51A of the bit storage output unit 51 described later.

Output position of systematic bits S (i + 0) is the output position calculation unit 49A _0, is determined as F1 (i). The output position of the bit S (i + 1) is obtained by F1 (i + 1) −D _p1 (i) −D _p2 (i) by the output position calculation unit 49A ₁ . Output position bits S (i + 2) is the output position calculation portion 49A _2, obtained by _{F1 (i + 2) -D p1} (i + 1) -D p2 (i + 1). Similarly, the output position of the bit S (i + n−1) is F1 (i + n−1) −D _p1 (i + n−2) −D _p2 (i + n−2) by the output position calculation unit 49A _n−1. Desired,

Output position of the parity bits P1 (i + 0) is the output position calculation section 49B _0, obtained in _{F2 (i) -D p1 (i} ). Output position bits P1 (i + 1) is the output position calculation section 49B _1, obtained by _{F2 (i + 1) -D p1} (i + 1) -D p2 (i). Output position bits P1 (i + 2) is the output position calculation section 49B _2, obtained by the _{F2 (i + 2) -D p1} (i + 2) -D p2 (i + 1). Similarly, the output position of the bit P1 (i + n-1) is F2 (i + n-1) _-Dp1 (i + n-1) _-Dp2 (i + n-2) by the output position calculation unit 49Bn _-1. Desired.

Output position of the parity bit P2 (i + 0) is the output position calculating unit 49C _0, obtained by _{F3 (i) -D p1 (i} ) -D p2 (i). Output position bits P2 (i + 1) is the output position calculation unit 49C _1, obtained by _{F3 (i + 1) -D p1} (i + 1) -D p2 (i + 1). Output position output position bits P2 (i + 2) is the output position calculation section 49C _2, obtained by _{F3 (i + 2) -D p1} (i + 2) -D p2 (i + 2). Similarly, the output position of the bit P2 (i + n−1) is F3 (i + n−1) −D _p1 (i + n−1) −D _p2 (i + n−1) by the output position calculation unit 49C _n−1. Desired.

As an example, as shown in FIGS. 29 and 30, n = 4, initial position information F _ini = 0, D _p1 (i) = 1, D _p1 (i + 1) = 1, D _p1 (i + 2) = 1, D _{When p1} (i + 3) = 1, D _p2 (i) = 0, D _p2 (i + 1) = 1, D _p2 (i + 2) = 1, D _p2 (i + 3) = 1, the output position calculation unit 49A ₀ The output position of bit S (i) is calculated as 0. In the same case, the output position calculation unit 49A ₁ calculates the output position of the bit S (i + 1) as 2, the output position calculation unit 49A ₂ calculates the output position of the bit S (i + 2) as 4, and the output position calculation unit 49A ₃ calculates the output position bits S (i + 3) 7 and.

After calculating the output position of each bit by the output position calculation units 49A, 49B, and 49C, the write control units 50A _{0 to} 50A _n−1 , 50B _{0 to} 50B _n−1 , 50C _{0 to} 50C _n−1 are converted to the bit S ( i), S (i + 1), ..., S (i + n-1), P1 (i), P1 (i + 1), ..., P1 (i + n-1), P2 (i), P2 (i + 1), ..., P2 ( i + n−1) is written to the bit storage output unit 51. The bit storage output unit 51 includes 4n bit storage units 51A for storing each of the bits in column 0 to column 4n-1, and 4n for reading out the bits stored from each bit storage unit 51A. Data output units 51B. Each bit storage unit 51A is assigned an address that designates one of columns 0 to 4n-1.

Since the number of output bits of the output position control unit 47 exceeds the number n of the storage units 48 _{0 to} 48 _n−1 provided for each radio frame created at the same time, the bit storage / output unit 51 This is a buffer provided for matching the bit writing to the memory. The bit storage units 51A of the columns n to 2n-1 correspond to the columns 0 to n-1, respectively, and when the bit storage units 51A of the columns 0 to n-1 are filled with the preceding bits, the columns 0 to n- Store the bits to be redistributed to one. The bit storage units 51A of the columns 2n to 3n-1 also correspond to the columns 0 to n-1, respectively, and the bit storage units 51A of the columns 0 to n-1 in the preceding bits are also the bit storage units 51A of the columns n to 2n-1. Stores the bits to be redistributed in columns 0 to n−1. The bit storage units 51A of the columns 3n to 4n-1 also correspond to the columns 0 to n-1, respectively, and when the bit storage units 51A of the columns 0 to 3n-1 are filled with the preceding bits, the columns 0 to n- Store the bits to be redistributed to one.

The write control units 50A, 50B, and 50C distribute and write the bits S, P1, and P2 to the bit storage unit 51A corresponding to the output sequence calculated by the output position calculation units 49A, 49B, and 49C. The write control units 50A _{0 to} 50A _n−1 , 50B _{0 to} 50B _n−1 , and 50C _{0 to} 50C _n−1 are notified of deletion instructions from the D _p1 calculation unit 45 and the D _p2 calculation unit 46, and write control is performed. The units 50A _{0 to} 50A _n−1 , 50B _{0 to} 50B _n−1 , 50C _{0 to} 50C _n−1 do not write the bits to be deleted according to the deletion instruction to the bit storage unit 51A.

As an example, as shown in FIGS. 29 and 30, the D _p1 calculation unit 45 instructs the deletion of the parity bit P1 (i), and the D _p2 calculation unit 46 instructs the deletion of the parity bit P2 (i + 1). In this case, even if the output position calculation units 49B ₀ and 49C ₁ calculate the output positions of the parity bits P1 (i) and P2 (i + 1) as 0 and 3, respectively, the parity bits P1 (i) and P2 (i + 1 The write control units 50B ₀ and 50C ₁ corresponding to) discard the bits P1 (i) and P2 (i + 1) without writing them in the bit storage unit 51A for the columns 0 and 3. The other write control unit writes the bit into the bit storage unit 51A according to the calculation result of the corresponding output position calculation unit. In this case, the bit storage unit 51A for row 0, since the systematic bits S (i) is written by the write control unit 50A ₀ in accordance with the calculated result of the output position calculating unit 49A _0, the write control unit 50B ₀ parity bits By not writing P1 (i) in the bit storage unit 51A for the column 0, the consistency of the column in the bit storage output unit 51 is maintained. Also, the bit storage unit 51A for row 3, but the parity bits P1 (i + 1) is written by the write control unit 50A ₁ in accordance with the calculated result of the output position calculating section 49B _1, the write control unit 50C ₁ parity bit P2 By not writing (i + 1) into the bit storage 51A for column 3, inappropriate collision can be avoided.

The bit storage output unit 51 notifies the initial position calculation unit 44 of the final bit position information described above according to the contents of the bit storage unit 51A. For example, in the case of FIGS. 29 and 30, the bit storage output unit 51 notifies the initial position calculation unit 44 of the final bit position information indicating the column 9, and the initial position calculation unit 44 sets the next initial position information F _ini as the next initial position information F _ini. (9 + 1) mod 4 = 2 is calculated. The contents of the initial position calculation unit 44 are reset every time one TTI expires, and the initial position information F _ini for the calculation of the first bit thereafter becomes zero.

After completing the bit writing to the bit storage unit 51A of the bit storage output unit 51, the data output unit 51B stores bits in the storage units 48 _{0 to} 48 _n−1 provided for each number of radio frames created simultaneously in the storage device 48. Perform writing. First, when the first clock pulse after completion of bit writing to the bit storage unit 51A is supplied to the bit storage output unit 51, the data output unit 51B for columns 0 to n-1 corresponds to the corresponding bit storage unit 51A. N bits are read out and written into the storage units 48 _{0 to} 48 _n−1 . At this time, the columns are exchanged by the first interleave and written in the storage units 48 _{0 to} 48 _n−1 . For example, if the first number of columns interleaved n = 4 (= radio frame number is created at the same time), bits of the column 0 of bit storage unit 51A in the storage unit 48 ₀ of frame 0 of the storage device 48, frame 1 bits of the column 2 in the storage unit 48 ₁ of the bits of the column 1 in the storage unit 48 ₂ of the frame 2, to write the bits of the column 3 in the storage unit 48 ₃ of the frame 3, in this example columns 1 and 2 Exchanged. After the bit is read, the contents of the bit storage unit 51A are erased.

When the next clock pulse is supplied to the bit storage output unit 51, n bits in the columns _{n to 2n-1} are transferred from the bit storage unit 51A to the storage units 48 _{0 to} 48 _n-1 . For the replacement of the column, for example, in the case of the first interleave sequence number n = 4 in as shown, the storage unit 48 ₀ of frame 0 of the storage device 48 of the bit storage unit 51A column 4 bits of the frame 1 bits of the column 6 in the storage unit 48 _1, bits of the column 5 in the storage unit 48 ₂ of the frame 2, the storage unit 48 ₃ of the frame 3 writes the bits of the column 7. In this example, columns 1 and 2 corresponding to columns 5 and 6 are exchanged. When the next clock pulse is supplied to the bit storage output unit 51, n bits in the columns 2n to 3n _-1 are transferred from the bit storage unit 51A to the storage units 48 _{0 to} 48 _n-1 . When the next clock pulse is supplied to the bit storage output unit 51, n bits in the columns 3n to 4n _-1 are transferred from the bit storage unit 51A to the storage units 48 _{0 to} 48 _n-1 .

FIG. 31 is an operation timing chart of processing in which parity bits P1 (i) and P2 (i + 1) in 12 bits shown in FIGS. 29 and 30 are deleted. Time T in the figure indicates the rising time of the clock pulse. At time T0 to T1, the D _p1 calculating unit 45 and the D _p2 calculating unit 46 have n parity bits P1 (i),..., (I + 3) and n P2 (i),. cumulative remove bits D _p1 (i) for _{all, ···, D p1 (i +} 3), D p2 (i), is calculated · · ·, D _p2 the (i + 3), whether to remove the bit Judging. In addition, at time T2 to T3, the D _p1 calculating unit 45 and the D _p2 calculating unit 46 perform cumulative deletion bit numbers D _p1 (i),..., D _p1 (i + 3) with respect to parity bits other than the parity bit P2 (i). , D _p2 (i + 1),..., D _p2 (i + 3) are calculated, and it is determined whether or not the bit should be deleted. The reason why the processing time ends earlier by the parity bit P2 (i) is that the cumulative deletion bit number D _p2 (i) for the parity bit P2 (i) is 0, and the cumulative deletion bit number D _p1 ( This is because the processing cycle is short because it is smaller than i),..., D _p1 (i + 3), D _p2 (i + 1),..., D _p2 (i + 3) (see FIGS. 29, 30 and 7). ).

2n pieces of cumulative delete bits _{D p1 (i), ···,} D p1 (i + 3), D p2 (i), ···, D p2 (i + 3) After all calculate completion of, at the time T2~T3 The output position calculation units 49A, 49B, and 49C have 3n bits S (i), ..., S (i + 3), P1 (i), ..., P1 (i + 3), P1 (i), ... .., P2 (i + 3) is calculated, and the write control units 50A, 50B, 50C are calculated according to the calculation results of the output position calculation units 49A, 49B, 49C and the deletion instructions from the _Dp1 calculation unit 45, _Dp2 calculation unit 46. Writes or discards bits in the bit storage unit 51A of the bit storage output unit 51 (more precisely, discards the parity bits P1 (i) and P2 (i + 1) and writes the other bits in the bit storage unit 51A). .

In this way, after all rate matching processing results of 3n bits S, P1, and P2 are stored in the bit storage unit 51A, at time T3 to T4, in the bit storage output unit 51, column 0 to column n -1 data output unit 51B reads the bits of column 0 to column n-1 from bit storage unit 51A and writes them to storage units 48 _{0 to} 48 _n-1 provided for each number of radio frames created simultaneously. (Output). Similarly, if a bit is stored in any of the bit storage units 51A for the columns n to 2n-1 of the bit storage output unit 51, the column n to the column 2n-1 at time T4 to T5. The data output unit 51B reads the bits in the columns n to 2n-1 from the bit storage unit 51A and writes them in the storage units 48 _{0 to} 48 _n-1 . If bits are stored in any of the bit storage units 51A for the columns 2n to 3n-1 of the bit storage output unit 51, at time T5 to T6, the data output unit for the columns 2n to 3n-1 51B reads the bits in the columns 2n to 3n-1 from the bit storage unit 51A and writes them in the storage units 48 _{0 to} 48 _n-1 . Further, if bits are stored in any of the bit storage units 51A for the columns 3n to 4n-1 of the bit storage output unit 51, at time T5 to T6, the data output unit for the columns 3n to 4n-1 51B reads the bits in the columns 3n to 4n-1 from the bit storage unit 51A and writes them to the storage units 48 _{0 to} 48 _n-1 .

As described above, according to the third embodiment, the bit division unit 42 divides the turbo-encoded data bit stream into the systematic bit S, the first parity bit P1, and the second parity bit P2. The first parallel processing unit 43A extracts, from the stream of systematic bits S, the same number of systematic bits as the number of a plurality of radio frames created at the same time, and puts these systematic bits into a plurality of columns of the same number as the number of radio frames. Distribute regularly. The second parallel processing unit 43B extracts from the stream of the first parity bits P1 the same number of first parity bits as the number of the plurality of radio frames created at the same time, and extracts these first parity bits as radio frames. Distribute regularly to as many columns as there are. The third parallel processing unit 43C extracts from the stream of the second parity bits P2 the same number of second parity bits as the number of the plurality of radio frames created simultaneously, and extracts these second parity bits as radio frames. Distribute regularly to as many columns as there are. The parameter calculation unit 30 calculates rate matching basic parameters e _ini , e _plus , and e _minus . Further, the D _p1 calculation unit 45 functions as a first deletion determination unit, and a bit number m and a basic parameter in the stream of the first parity bits assigned to each first parity bit P1 distributed to the column. Based on e _ini , e _plus , and e _minus , a bit to be deleted is determined among a plurality of first parity bits distributed to the column. The D _p2 calculation unit 46 functions as a second deletion determination unit, and the bit number m and the basic parameter e _{ini in} the stream of the second parity bits assigned to each second parity bit P2 distributed to the column. , E _plus , e _minus , a bit to be deleted is determined among a plurality of second parity bits distributed to the column. Furthermore, the D _p1 calculation unit 45, for each first parity bit P distributed to the column, a first accumulation that is the total number of the preceding bits to be deleted and the corresponding bits in the stream of the first parity bits. The number of deleted bits _Dp1 is calculated. For each second parity bit distributed to the column, the D _p2 calculation unit 46 calculates the second cumulative deletion bit number D that is the total number of the preceding bits to be deleted and the corresponding bits in the second parity bit stream. _p2 is calculated. The output position control unit 47 functions as a rate matching / first interleaving unit, and includes a plurality of first parity bits P1 distributed to the columns by the second parallel processing unit 43B and the third parallel processing unit 43C. Of the plurality of second parity bits P2, the bits determined to be deleted by the D _p1 calculating unit 45 and the D _p2 calculating unit 46 are deleted, and the first accumulated deleted bit number D _p1 and the second accumulated bit The plurality of systematic bits S, the first parity bit P1, and the second parity bit P2 are newly redistributed into a plurality of columns based on the number of deleted bits _Dp2 , and at least two of the plurality of columns obtained by the redistribution The bits of the columns are exchanged with each other, and the bits of the columns that have been redistributed and exchanged are stored in a plurality of radio frames, respectively. Thus, by redistributing a plurality of bits to a plurality of columns based on the cumulative repetition / deletion bit number D, it is possible to complete bit redistribution (rate matching including bit collection) at high speed. Furthermore, the first interleaving is completed only by exchanging at least two bits of the plurality of columns obtained by the redistribution. Therefore, it is possible to complete the bit redistribution and the first interleaving at a higher speed than in the case of the bit redistribution and the first interleaving based on the bit itself obtained by the rate matching. In addition, since the parallel processing unit performs rate matching on the bits distributed or parallelized to a plurality of columns and performs the first interleaving by exchanging the columns, the first interleaving result corresponds to a plurality of radio frames. Therefore, it is not necessary to perform the radio frame division again. As described above, it is possible to further speed up the encoding process while complying with W-CDMA.

It is a figure which shows the outline | summary of the encoding process at the time of the downlink data transmission of the radio | wireless communications system by W-CDMA. It is a figure which shows the outline | summary of the decoding process at the time of the uplink data reception of the radio | wireless communications system by W-CDMA. It is a functional block diagram which shows the encoding processing apparatus of the radio | wireless communication apparatus which concerns on Embodiment 1 of this invention. It is a figure which shows the rate matching pattern determination algorithm prescribed | regulated to the 3GPP specification. It is a figure which shows the example of the process by which a bit is deleted (puncture) by rate matching process as operation | movement of the encoding processing apparatus of FIG. It is a figure which shows the example of the process in which a bit is repeated (repetition) by rate matching process as operation | movement of the encoding processing apparatus of FIG. 4 is a flowchart illustrating a variable calculation / iteration / deletion determination algorithm executed by a D calculation unit of the encoding processing apparatus in FIG. 3. It is a block diagram which shows the specific structural example of D calculation part of the encoding processing apparatus of FIG. It is the left half of the block diagram which shows the specific structural example of the output position control part of the encoding processing apparatus of FIG. It is the right half of the said block diagram which comprises the block diagram which shows the specific structural example of an output position control part in cooperation with FIG. It is the left half of the figure which shows the process example of each element of the output position control part of FIG. 9 and FIG. 10 when a bit is deleted by rate matching processing. FIG. 11 is a right half of the diagram configured in cooperation with FIG. 11 to illustrate a processing example of each element of the output position control unit of FIG. 9 and FIG. 10. FIG. 11 is a left half of a diagram illustrating a processing example of each element of the output position control unit of FIGS. 9 and 10 when bits are repeated in the rate matching process. FIG. 14 is a right half of the figure configured in cooperation with FIG. 13 to illustrate a processing example of each element of the output position control unit of FIG. 9 and FIG. 10. FIG. 13 is an operation timing chart of the processing shown in FIGS. 11 and 12. FIG. 15 is an operation timing chart of the processing shown in FIGS. 13 and 14. It is a functional block diagram which shows the decoding processing apparatus of the radio | wireless communication apparatus which concerns on Embodiment 2 of this invention. It is a figure which shows the first step of the example of the process in which a bit is deleted by rate matching process as operation | movement of the encoding processing apparatus of FIG. It is a figure which shows the next stage of FIG. It is a figure which shows the next step of FIG. It is a figure which shows the next stage of FIG. It is a figure which shows the first step of the example of the process in which a bit is repeated by rate matching process as operation | movement of the encoding processing apparatus of FIG. It is a figure which shows the next step of FIG. It is a figure which shows the next step of FIG. It is a figure which shows the next stage of FIG. It is a functional block diagram which shows the encoding processing apparatus of the radio | wireless communication apparatus which concerns on Embodiment 3 of this invention. FIG. 27 is a left half of a block diagram illustrating a specific configuration example of an output position control unit of the encoding processing device of FIG. 26. It is the right half of the said block diagram which comprises the block diagram which shows the specific structural example of an output position control part in cooperation with FIG. It is the left half of the figure which shows the process example of each element of the output position control part of FIG. 27 and FIG. FIG. 29 is a right half of the figure configured in cooperation with FIG. 29 to illustrate a processing example of each element of the output position control unit of FIGS. 27 and 28. FIG. 31 is an operation timing chart of the processing shown in FIGS. 29 and 30.

Explanation of symbols

30, 130 Parameter calculation unit 31, 43A, 43B, 43C, 131 Parallel processing unit, 32, 132 D (= e _plus number) calculation unit (repetition / deletion determination unit), 33, 47 Output position control unit (rate matching the first interleave _{unit), 33A 0 ~33 n-1} , 52A 0 ~52A n-1, 52B 0 ~52B n-1, 52C 0 ~52C n-1 adders, calculated 34,44,134 initial position 35, 48, 135 storage device, 35 _{0 to} 35 _n-1 , 48 _{0 to} 48 _n-1 , 135 _{0 to} 135 _n-1 storage unit, 36 _{0 to} 36 _n-1 , 49A _{0 to} 49A _{n- 1} , 49B _{0 to} 49B _n-1 , 49C _{0 to} 49C _n-1 output position calculation unit, 37 _{0 to} 37 _n-1 , 50A _{0 to} 50A _n-1 , 50B _{0 to} 50B _n-1 , 50C _{0 to} 50C _n-1 write controller (redistribution control unit), 38,51-bit storage output unit, 38A, 51A Tsu DOO storage unit, 38B, 51B data output _{unit, 39 0 ~39 n-1 D} (= e plus number) calculating unit, 40 ₀ ~40 _n-1 iteration / deletion determining unit 41 of the last bit D (= e _plus number) storage unit, 42-bit dividing unit, 45 D _p1 (= e _plus number) calculation unit (first deletion determination unit), 46 D _p2 (= e _plus number) calculation unit (second deletion determination unit) 133 Output position control unit (rate dematching unit), 150 column data reading order control unit (first deinterleave / radio frame combining unit).

Claims (9)

A parallel processing unit that extracts the same number of bits as the number of a plurality of radio frames created simultaneously from the data bit stream to be transmitted, and regularly distributes these bits to a plurality of columns of the same number as the number of the radio frames. When,
A parameter calculator for calculating basic parameters of rate matching;
Based on a bit number in the data bit stream assigned to each bit distributed to the column and the basic parameter, a bit to be repeated or deleted among the plurality of bits distributed to the column is determined. An iteration / deletion determination unit;
For each bit distributed to the column, a cumulative repetition / deletion bit number calculation unit for calculating a cumulative repetition / deletion bit number that is a total number of the preceding bits to be repeated or deleted in the data bitstream and the bit;
Of the plurality of bits distributed to the column by the parallel processing unit, the bit determined to be repeated or deleted by the repetition / deletion determination unit is repeated or deleted, and the cumulative number of repeated / deleted bits And redistributing a plurality of bits to a plurality of columns based on the above, replacing at least two bits of the plurality of columns obtained by the redistribution with each other, and redistributing and exchanging the bits of the columns Each of the plurality of radio frames stores a rate matching / first interleaving unit. The repetition / deletion determination unit includes a plurality of repetition / deletion determination units for determining in parallel whether or not each of the plurality of bits distributed to the columns by the parallel processing unit should be repeated or deleted.
The cumulative repetition / deletion bit number calculation unit includes a cumulative repetition / deletion bit number calculation unit for calculating the cumulative repetition / deletion bit number in parallel for each of the plurality of bits distributed to the columns by the parallel processing unit,
The rate matching / first interleaving unit calculates, for each of a plurality of bits distributed to the columns by the parallel processing unit, a plurality of outputs for calculating a column to be redistributed based on the corresponding cumulative repetition / deletion bit number A position calculation unit;
Each of the plurality of bits distributed to the column by the parallel processing unit is repeated or deleted when it is determined that the corresponding repetition / deletion determination unit should repeat or delete, and the output position calculation The encoding processing apparatus for a wireless communication apparatus according to claim 1, further comprising a plurality of redistribution control units that redistribute to the columns calculated by the unit. The rate matching / first interleaving unit includes a plurality of bit storage units larger than the number of columns, and a data output unit that reads bits from each bit storage unit and stores them in a radio frame,
Each of the output position calculation unit calculates the position of the bit storage unit to store each bit,
Each of the redistribution control units stores each bit in the bit storage unit at the position calculated by the output position calculation unit,
The data output unit reads the same number of bits as the number of the radio frames at a time from the bit storage unit, exchanges at least two of these bits, and stores them in the plurality of radio frames. The encoding processing device for a wireless communication device according to claim 2. The initial position for calculating the initial sequence in which the first bit of the plurality of bits to be redistributed next is redistributed based on the column in which the last bit among the plurality of bits redistributed immediately before is redistributed A calculation unit;
The encoding process of the radio communication apparatus according to claim 1, wherein the rate matching / first interleaving unit redistributes a plurality of bits to be redistributed next to a plurality of columns starting from the initial sequence. apparatus. A bit division unit for dividing the turbo encoded data bit stream into systematic bits, first parity bits, and second parity bits;
A first parallel that extracts from the stream of systematic bits the same number of systematic bits as the number of radio frames that are created simultaneously, and regularly distributes these systematic bits into the same number of columns as the number of radio frames. The processing unit,
From the first parity bit stream, the same number of first parity bits as the number of a plurality of radio frames created simultaneously are extracted, and these first parity bits are arranged in a plurality of columns of the same number as the number of the radio frames. A first parallel processing unit that regularly distributes;
From the second parity bit stream, the same number of second parity bits as the number of a plurality of radio frames created at the same time are extracted, and these second parity bits are arranged in a plurality of columns of the same number as the number of the radio frames. A second parallel processing unit that distributes regularly;
A parameter calculator for calculating basic parameters of rate matching;
The plurality of first parity bits distributed to the column based on a bit number in the stream of the first parity bits assigned to each first parity bit distributed to the column and the basic parameter A first deletion determination unit that determines a bit to be deleted,
The plurality of second parity bits distributed to the column based on the bit number in the stream of the second parity bits assigned to each second parity bit distributed to the column and the basic parameter A second deletion determination unit for determining a bit to be deleted,
For each first parity bit distributed to the column, a first cumulative deletion bit number that is a total number of preceding bits to be deleted in the stream of the first parity bit and the first bit is calculated. A cumulative deletion bit number calculation unit;
For each second parity bit distributed to the column, a second cumulative deletion bit number that is a total number of preceding bits to be deleted in the stream of the second parity bit and the second bit is calculated. A cumulative deletion bit number calculation unit;
Of the plurality of first parity bits and the plurality of second parity bits distributed to the column by the second parallel processing unit and the third parallel processing unit, the first deletion determination A plurality of systematic bits based on the first cumulative deletion bit number and the second cumulative deletion bit number, the first cumulative deletion bit number, and the second deletion determination unit. The parity bit and the second parity bit are newly redistributed to a plurality of columns, and at least two of the plurality of columns obtained by the redistribution are interchanged with each other, and the redistribution and the replacement are performed. An encoding processing apparatus for a wireless communication apparatus, comprising: a rate matching / first interleaving unit that stores a column bit in each of the plurality of wireless frames. In parallel, the same number of bits as the number of the plurality of radio frames received in the same reception cycle are extracted from the data bit stream to be received, and these bits are regularly distributed to the same number of columns as the number of the radio frames. The processing unit,
A parameter calculation unit for calculating basic parameters of rate dematching;
Based on a bit number in the data bit stream assigned to each bit distributed to the column and the basic parameter, a bit to be repeated or deleted among the plurality of bits distributed to the column is determined. An iteration / deletion determination unit;
For each bit distributed to the column, a cumulative repetition / deletion bit number calculation unit for calculating a cumulative repetition / deletion bit number that is a total number of the preceding bits to be repeated or deleted in the data bitstream and the bit;
Of the plurality of bits distributed to the column by the parallel processing unit, the bit determined to be repeated or deleted by the repetition / deletion determination unit is repeated or deleted, and the cumulative number of repeated / deleted bits A rate dematching unit that redistributes a plurality of bits to a plurality of columns based on
Decoding processing of a wireless communication apparatus including a first deinterleave / radio frame combining unit that reads and combines a plurality of columns obtained by redistribution by the rate dematching unit while exchanging at least two of them apparatus. The repetition / deletion determination unit includes a plurality of repetition / deletion determination units for determining in parallel whether or not each of the plurality of bits distributed to the columns by the parallel processing unit should be repeated or deleted.
The cumulative repetition / deletion bit number calculation unit includes a cumulative repetition / deletion bit number calculation unit for calculating the cumulative repetition / deletion bit number in parallel for each of the plurality of bits distributed to the columns by the parallel processing unit,
The rate dematching unit, for each of a plurality of bits distributed to the column by the parallel processing unit, a plurality of output position calculation units that calculate a column to be redistributed based on the corresponding cumulative repetition / deletion bit number When,
Each of the plurality of bits distributed to the column by the parallel processing unit is repeated or deleted when it is determined that the corresponding repetition / deletion determination unit should repeat or delete, and the output position calculation The decoding processing device for a wireless communication device according to claim 6, further comprising a plurality of redistribution control units that redistribute into the columns calculated by the unit. The rate dematching unit includes a plurality of bit storage units larger than the number of columns, and a data output unit that reads bits from each bit storage unit and stores them in a radio frame,
Each of the output position calculation unit calculates the position of the bit storage unit to store each bit,
Each of the redistribution control units stores each bit in the bit storage unit at the position calculated by the output position calculation unit,
8. The decoding processing device for a wireless communication device according to claim 7, wherein the data output unit reads the same number of bits as the number of the wireless frames at a time from the bit storage unit and redistributes them to the columns. . The initial position for calculating the initial sequence in which the first bit of the plurality of bits to be redistributed next is redistributed based on the column in which the last bit among the plurality of bits redistributed immediately before is redistributed A calculation unit;
7. The decoding processing apparatus for a wireless communication apparatus according to claim 6, wherein the rate dematching unit redistributes a plurality of bits to be redistributed next to a plurality of columns starting from the initial column.

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