JP2009231979A - Memory reduction rate matching processor for broadcast channel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce memory capacity equivalent to a virtual circular buffer, by eliminating NULL detection in rate matching processing and by reducing the bits necessary for NULL detection. <P>SOLUTION: A memory reduction rate matching processor comprises a bit collector which puts output data (respectively being 1 bit) of coding processing which is a pre-stage processing of rate-matching processing for memory reduction rate matching processing of a BCH together into 3 bits; a memory which stores the data put together into the 3 bits, an interleaver which performs block interleaving processing on the data put together into the 3 bits, a bit splitter which divides the interleaved 3-bit output data by bit; and a selector which selects and outputs the divided data at a desired timing. The memory is disposed, before the interleaver and interleaving points which serve as NULL are skipped in the block interleaving to read the data out of the memory. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory reduction rate matching processing device for a broadcast channel (hereinafter referred to as BCH), and more particularly to a memory reduction rate matching processing device for BCH in a radio base station device in LTE (Long-Term Evolution).

  FIG. 5 shows a transport channel process in the BCH in the downlink channel (hereinafter referred to as DL) in LTE disclosed in Non-Patent Document 1.

  This transport channel process has a CRC attachment unit 1, a channel coding unit 2, and a rate matching unit 3.

  FIG. 6 is a block diagram illustrating the channel coding unit 2 of FIG. 5 in detail, and is an example using encoding by a rate 1/3 tail binding convolutional code.

  FIG. 7 is a block diagram showing in detail the rate matching unit 3 in FIG. 5, and is an example of rate matching between BCH and DL-CCH.

  The BCH is encoded by adding a 16-bit CRC bit, a rate 1/3 bit-biting convolutional code, and rate matching.

BCH rate matching is performed by sub-block interleavers 4, 5, and 6 for input data after channel coding (d _k ⁽⁰⁾ , d _k ⁽¹⁾ , d _k ⁽²⁾ : 1 bit each). Interleave.

The output data (v _k ⁽⁰⁾ , v _k ⁽¹⁾ , v _k ⁽²⁾ ) of each of the sub-block interleavers 4, 5 and 6 has an input data size that is larger than the block interleaver size (R * C). When it is small, NULL indicating that it is not data is mapped.

The output data (v _k ⁽⁰⁾ , v _k ⁽¹⁾ , v _k ⁽²⁾ ) of the sub-block interleavers 4, 5, 6 is received by the bit collection unit 7 and v _k ⁽⁰⁾ → v _k ⁽¹⁾ The data is stored in the virtual circular buffer in the order of v _k ⁽²⁾ , and the bit selection / planning unit 8 outputs the data stored in the virtual circular buffer while circulating (see FIG. 7).

  Refer to the following in Non-Patent Document 1 for a detailed description of the processing of each part.

CRC attachment part 1: 5.1.1 CRC calculation
Channel coding unit 2: 5.1.3.1 Tail biting conventional coding
Rate matching unit 3: 5.1.4.2 Rate matching for BCH and DL-CCH
FIG. 8 is a block diagram for explaining a configuration example of a BCH rate matching processing device assumed as a conventional technique based on FIG.

  The configuration example of the BCH rate matching processing device shown in FIG. 8 is almost the same as that in FIG.

In other words, this BCH rate matching processing device performs interleavers 11, 12, which perform block inleaving on each of input data (d _k ⁽⁰⁾ , d _k ⁽¹⁾ , d _k ⁽²⁾ : 1 bit each). 13, memories 14, 15, 16 for storing output data (v _k ⁽⁰⁾ , v _k ⁽¹⁾ , v _k ⁽²⁾ ) of the interleavers 11, 12, 13, a bit collection unit 17, , And bit selection / planning 17.

  In the configuration of the BCH rate matching processing apparatus shown in FIG. 8 as such a conventional technique, the memories 14, 15, and 16 that store the output results of the interleavers 11, 12, and 13 serve as virtual circular buffers. Since this virtual circular buffer is located after the interleavers 11, 12, 13, a bit for detecting the above-mentioned NULL is required in each of the memories 14, 15, 16 serving as the virtual circular buffer.

  For this reason, the bit width of each of the memories 14, 15, and 16 needs to be expanded to 2 bits in which 1 bit for detecting NULL is added to 1 bit of input data.

  Conventionally, as related to this type of technology, Patent Document 1 discloses a downlink transmission path of a wireless communication system based on a W-CDMA (Wide-Code Division Multiple Access) system such as a third generation mobile communication system. In particular, an interleave processing device such as retransmission data (HARQ data) based on the HARQ (Hybrid Automatic Repeat reQuest) technology is disclosed in connection with the HSDPA (High Speed Downlink Packet Access) technology.

  As shown in FIG. 9, the interleave processing device includes a plurality of physical channels arranged in the row direction so that the bit strings of the respective physical channels are aligned in the column direction. A plurality of physical channels, third and fourth memories 23 and 24 for storing a plurality of physical channels arranged in the row direction so that the bit strings of the respective physical channels are along the column direction; From the first memory 21 in which the physical channels are stored, or from the first and second memories 21 and 22 in which the plurality of physical channels are stored, the bit columns in the row direction are sequentially arranged in the column direction. The bit string for each column read out is read out from the first memory 21 of the third memory 23, the third memory 23, 24, or the first, second memory. The reading at 22 A column replacement unit 25 to write to the different rows and columns of bit strings, and a interleave reference table 27.

  When the HARQ data is 16QAM data, the interleave processing device arranges physical channels # 0 to # 14 in the memory 21 and 22 in the row direction, and arranges the bit string of each physical channel in the column direction. As described above, the column replacement units 25 and 26 read out a bit string consisting of one bit of each of the physical channels # 0 to # 14 in the column order. The read bit string is written in a column different from the memories 21 and 22 in the memories 23 and 24 by the column replacement units 25 and 26 according to the interleave pattern in the table 27.

  Thereby, in the memories 23 and 24, the bit arrangement in the column direction in the physical channels # 0 to # 14 is different from the memories 21 and 22, and the interleave processing is performed for each physical channel.

  If the HARQ data is QPSK data, the memories 21 and 23 are used.

Such an interleave processing device suppresses an increase in the number of interleaving processes regardless of the number of physical channels, and makes it possible to reduce the processing amount.
DRAFT-3GPP TS36.212 V8.0.0 (2007-09) JP 2007-142944 A

  However, as described above, in BCH rate matching, NULL detection is not performed in bit selection of rate matching processing, and bits necessary for NULL detection are reduced to reduce the memory capacity corresponding to the virtual circular buffer. In this case, a technique such as that by the interleave processing device disclosed in Patent Document 1 cannot be applied.

  Therefore, the present invention has been made in view of the above points, and an object of the present invention is to place a memory corresponding to a virtual circular buffer before rate matching processing in BCH rate matching. To provide a BCH memory reduction rate matching processing device that eliminates NULL detection in bit selection of matching processing, reduces bits necessary for NULL detection, and reduces the memory capacity corresponding to a virtual circular buffer. It is.

According to the present invention, in order to solve the above problems,
In a rate matching processing device that performs rate matching processing of a broadcast channel (hereinafter referred to as BCH) that is one of the downlink transport channels of a radio base station device in LTE (Long-Term Evolution),
The output data (v _k ⁽⁰⁾ , v _k ⁽¹⁾ , v _k ⁽²⁾ : 1 bit each) of the coding process by the rate 1/3 tail-biding convolutional encoding, which is the previous stage of the rate matching process, is 3 bits. A bit collector
A memory for storing data collected in 3 bits by the bit collector;
An interleaver that performs block interleaving on the data collected in 3 bits by the bit collector;
A bit splitter that divides the 3-bit output data interleaved by the interleaver into each bit (v _k ^{′ (0)} , v _k ^{′ (1)} , v _k ^{′ (2)} );
A rate matching processing device in the BCH configured by a selector that selects and outputs data divided by the bit splitter at a desired timing,
By placing the memory before the interleaver in the rate matching processing device, in the block interleaving in the rate matching processing device, skip the NULL interleaving point and read the data from the memory, thereby the rate matching processing device There is provided a memory reduction rate matching processing device for BCH, wherein NULL detection in bit selection by the selector is eliminated, bits required at the time of NULL detection are reduced, and the capacity of the memory is reduced.

  The memory reduction rate matching processing apparatus for BCH according to the present invention eliminates NULL detection in bit selection of rate matching processing by placing a memory corresponding to a virtual circular buffer in front of rate matching processing in BCH rate matching. Bits required at the time of detection are reduced to reduce the memory capacity.

  The memory usage breakdown comparing the memory reduction rate matching processing apparatus in the BCH according to the present invention with the prior art shown in FIG. 8 is as follows. As shown in FIG. 3, in the prior art, each bit of 2 bits of data is used to detect NULL. Since the memory is allocated for each data, a total memory capacity of 6 × [bit] is necessary, whereas in the present invention, one bit is collected by bit-collecting three bit data. As a result, the memory capacity is 3X [bit] as a whole, and BCH rate matching can be realized with a memory capacity that is ½ that of the prior art.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram of a main part shown for explaining the configuration of a memory reduction rate matching processing apparatus in BCH according to the present invention.

That is, the memory reduction rate matching processing apparatus in BCH according to the present invention is basically a broadcast channel (hereinafter referred to as BCH) which is one of the downlink transport channels of a radio base station apparatus in LTE (Long-Term Evolution). ) In the rate matching processing apparatus that performs the rate matching process, the output data (v _k ⁽⁰⁾ , v _k ^{(1 )} of the coding process based on the tail-binding convolutional encoding at a rate of 1/3, which is the preceding stage of the rate matching process. ⁾ , V _k ⁽²⁾ : A bit collector 31 that collects 1 bit) into 3 bits, a memory 32 that stores data organized into 3 bits by the bit collector 31, and data that is organized into 3 bits by the bit collector 31 The Interleaver 33 that performs lock interleaving, and bits that divide the 3-bit output data interleaved by the interleaver 33 for each bit (v _k ^{′ (0)} , v _k ^{′ (1)} , v _k ^{′ (2)} ) A rate matching processing device in BCH comprising a splitter 34 and a selector 35 that selects and outputs data divided by the bit splitter 34 at a desired timing, and the memory 32 in the rate matching processing device Bits by the selector 35 in the rate matching processing device are placed before the interleaver 33, skipping NULL interleaving points in the block interleaving in the rate matching processing device, and reading data from the memory. Without the NULL detection in collection, to reduce the bit required when NULL detection is characterized by reducing the capacity of the memory.

Specifically, as shown in FIG. 1, three pieces of input data (d _k ⁽⁰⁾ , d _k ⁽¹⁾ , d _k ⁽²⁾ : 1 bit each) after channel coding are transmitted by a bit collector 31. The data is collected into one 3-bit data and stored in the memory 32.

Here, the memory 32 is a memory having a bit width of 3 bits, and the input data (d _k ⁽⁰⁾ , d _k ⁽¹⁾ , d _k ⁽²⁾ ) collected into one 3 bit data by the bit collector 31 is stored. It is written in the memory area in time series.

  Reading from the memory 32 is performed by reading data stored at an address specified by an interleaver 33 provided at a subsequent stage of the memory 32.

  As the interleaver 33, a sub-block interleaver is used, and the interleaving processing by this sub-block interleaver is performed by the size D of the input data to the block interleaver and the size of the block interleaver (R * C: number of R rows, C If the conditional expression D <R * C is true, the block interleaver is filled with R * C-D (hereinafter referred to as ND) NULL, and then input data is put into the block. Processing by an interleaver is performed.

  The block interleaver inputs input data in the column direction, performs interleaving in units of columns, and then outputs from the row direction.

  Here, the number of columns C is fixed to 32, and the interleave pattern P [i] is <1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31, 0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30>.

  Since the number of columns C is fixed at 32, ND is 0 or more and less than 32, and NULL is mapped only in the first row of the interleaver.

This block interleaver algorithm is
for (1 = 0; i <C; i ++) {
for (i = 0; j <R; j ++) {
Output [k ++] = input [j * 32 + P [i]]
}
}
It becomes.

  Here, i is an index in the column direction, j is an index in the row direction, k is an index of output data, and P [i] is an interleave pattern.

  Since NULL is included in the input, the output becomes a data string including NULL and becomes 2-bit data.

  In the present invention, NULL uses the fact that only the first row of the interleaver is mapped, and for a column with NULL, it is an algorithm that subtracts the number of times of NULL from the number of rows R, and outputs it. Since the storage position of the input data is offset by ND, it is assumed that processing for correcting the offset from the interleave pattern P [i] is performed at the same time.

When representing the algorithm of the present invention,
for (1 = 0; i <C; i ++) {
offset = (P [i] −ND)% 32
if (P [i] ≧ ND) tmp = 0
else tmp = 1
for (i = 0; j <R-tmp; j ++) {
Output [k ++] = Input [j * 32 + offset]
}
}
It becomes.

  In this algorithm, output [k ++] = input [j * 32 + offset], but actually, j * 32 + offset, which is an index of the memory 32, is obtained, and after interleaving from the memory 32 using this index j * 32 + offset. Reading data.

  The interleaver 33 reads 3 bit data from the memory 32 and outputs it to the bit splitter 34.

  Further, when one interleave is completed, the selector number is updated, and the selector number is notified to the selector 35.

  As shown in FIG. 2, the interleaver 33 performs iterative processing until the post-rate matching size E is reached.

  The bit splitter 34 is a processing unit that separates the 3-bit data from the interleaver 33 into 1-bit data of three pieces.

  The selector 35 is a processing unit that selects and outputs 1-bit 1-bit data among the 3-bit 1-bit data from the bit splitter 34.

  FIG. 4 is a diagram for explaining a rate matching flow chart according to the present invention.

  Next, a rate matching flowchart according to the present invention will be described with reference to FIG.

  First, in step S1 after the start, initialization processing of each parameter (selector number, D, R, ND, number of output data sizes) is performed as initialization processing.

  Next, in step S2 and step S14, the repetition (1): START and repetition (1): repetition processing of the data size after rate matching by END is performed.

  Next, in step S3 and step S12, repetition processing of the number of columns C is performed by repetition (2): START and repetition (2): END.

  Next, in step S8 and step S11, repetition processing of the number of columns R by repetition (3): START and repetition (3): END is performed.

  In this case, the number of repetitions is one less for a column with NULL.

  By repeating the repetition (1), repetition (2), and repetition (3) as described above, the block interleaved data is output while circulating (see FIG. 2).

  Next, in step S4, as the column rearrangement offset update process, a process for correcting the storage position of the input data offset by ND from the interleave pattern P [i] is performed.

  Next, in step S5, as a condition (1), processing for checking the presence / absence of NULL in the column of the interleave pattern P [i] is performed.

  If there is no NULL, the process proceeds to step S6.

  If NULL is present, the process proceeds to step S7.

  Next, in step S6, as the repeated offset update (1), since there is no NULL, a process of setting 0 to the repeated offset (tmp) is performed.

  Next, in step S7, since NULL is present as repetitive offset update (2), processing for setting 1 to repetitive offset (tmp) is performed.

  Next, in step 9, as a data output process, a read address of the memory 32 is calculated, and a process of reading data stored in the read address from the memory 32 is performed.

  Next, in step 10, as the output data number update process, a process of incrementing the output data number is performed.

  Next, in step 13, a selector number used in the selector 35 is generated as selector switching processing.

  This selector number is incremented after one interleaving process.

  Needless to say, the present invention is not limited to the embodiment described above and illustrated, and various modifications and applications are possible without departing from the spirit of the present invention.

FIG. 1 is a block diagram of a main part shown for explaining the configuration of a memory reduction rate matching processing apparatus in BCH according to the present invention. FIG. 2 is a diagram for explaining an output example of the interleaver according to the present invention. FIG. 3 is a diagram showing a breakdown of memory usage comparing the memory reduction rate matching processing device in the BCH according to the present invention and the prior art shown in FIG. FIG. 4 is a diagram for explaining a rate matching flow chart according to the present invention. FIG. 5 is a block diagram illustrating a transport channel process in the BCH in the downlink channel in LTE disclosed in Non-Patent Document 1. FIG. 6 is a block diagram illustrating the channel coding unit 2 of FIG. 5 in detail, and is an example using encoding by a rate 1/3 tail binding convolutional code. FIG. 7 is a block diagram showing in detail the rate matching unit 3 in FIG. 5, and is an example of rate matching between BCH and DL-CCH. FIG. 8 is a block diagram for explaining a configuration example of a BCH rate matching processing device assumed as a conventional technique based on FIG. FIG. 9 is a block diagram for explaining the configuration of the interleave processing device disclosed in Patent Document 1. In FIG.

Explanation of symbols

31 ... Bit collector,
32 ... Memory,
33 ... Interleaver,
34 ... Bit splitter,
35 ... Selector.

Claims (1)

In a rate matching processing device that performs rate matching processing of a broadcast channel (hereinafter referred to as BCH) that is one of the downlink transport channels of a radio base station device in LTE (Long-Term Evolution),
The output data (v _k ⁽⁰⁾ , v _k ⁽¹⁾ , v _k ⁽²⁾ : 1 bit each) of the coding process by the rate 1/3 tail-biding convolutional encoding, which is the previous stage of the rate matching process, is 3 bits. A bit collector
A memory for storing data collected in 3 bits by the bit collector;
An interleaver that performs block interleaving on the data collected in 3 bits by the bit collector;
A bit splitter that divides the 3-bit output data interleaved by the interleaver into each bit (v _k ^{′ (0)} , v _k ^{′ (1)} , v _k ^{′ (2)} );
A rate matching processing device in the BCH configured by a selector that selects and outputs data divided by the bit splitter at a desired timing,
By placing the memory before the interleaver in the rate matching processing device, in the block interleaving in the rate matching processing device, skip the NULL interleaving point and read the data from the memory, thereby the rate matching processing device A memory reduction rate matching processing apparatus for BCH, wherein NULL detection in bit selection by the selector is eliminated, bits necessary at the time of NULL detection are reduced, and the capacity of the memory is reduced.

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