JP2001102408A - Circuit board for mounting flip chip and method for mounting flip chip - Google Patents

Circuit board for mounting flip chip and method for mounting flip chip

Info

Publication number
JP2001102408A
JP2001102408A JP27419699A JP27419699A JP2001102408A JP 2001102408 A JP2001102408 A JP 2001102408A JP 27419699 A JP27419699 A JP 27419699A JP 27419699 A JP27419699 A JP 27419699A JP 2001102408 A JP2001102408 A JP 2001102408A
Authority
JP
Japan
Prior art keywords
circuit board
electrode
conductive
conductor
chip mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27419699A
Other languages
Japanese (ja)
Other versions
JP3414332B2 (en
Inventor
Yasukazu Fukunaga
靖一 福永
Hideo Imoto
秀夫 猪本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP27419699A priority Critical patent/JP3414332B2/en
Publication of JP2001102408A publication Critical patent/JP2001102408A/en
Application granted granted Critical
Publication of JP3414332B2 publication Critical patent/JP3414332B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a circuit board for mounting and a mounting method for removing and reducing connection failures between the conductive electrode of the circuit board and the electrode pad of a semiconductor element due to the irreglarities of the surface of the circuit board at the time of connecting the conductive electrode of the circuit board and the electrode pad of the semiconductor element in flip chip mounting using conductive adhesive. SOLUTION: A plurality of conductive electrodes 2 are formed at the prescribed positions of the surface of a circuit board 1, and then the surfaces of the conductive electrodes are polished so that the surfaces of the plurality of conductive electrodes can be turned into the same plane, and while conductive adhesive 5 is adhered to the electrode pads of a semiconductor element to be jointed, the electrode pads are press-fit to the conductive electrodes 2 so that the electrode pads can be electrically connected with the conductive electrodes 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を回路
基板に接続するフリップチップ実装に使用される回路基
板およびその回路基板を使用したフリップチップ実装方
法に関するものであり、半導体素子の電極と回路基板の
導体電極との接続抵抗値のバラツキがなく、良好な状態
で接続できる回路基板および実装方法を提供する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board used for flip-chip mounting for connecting a semiconductor element to a circuit board and a flip-chip mounting method using the circuit board. Provided are a circuit board and a mounting method that can be connected in a good state without variation in connection resistance with a conductor electrode of the board.

【0002】[0002]

【従来の技術】近年、電子機器の小型化要求に伴い、回
路モジュールの高密度実装が望まれている。そのため
に、半導体装置に実装される半導体素子は従来のプラス
チックモールド品からベアチップへと小型化され、各社
において様々な実装工法の開発が行われている。これら
の中で特に、ベアチップ半導体素子の実装工法としてフ
リップチップ実装が注目されている。
2. Description of the Related Art In recent years, with the demand for miniaturization of electronic equipment, high-density mounting of circuit modules is desired. For this purpose, semiconductor elements mounted on semiconductor devices have been reduced in size from conventional plastic molded products to bare chips, and various companies have been developing various mounting methods. Among these, flip-chip mounting has attracted attention as a method of mounting bare chip semiconductor elements.

【0003】以下に従来の回路基板を用いたフリップチ
ップ実装用回路基板および実装方法について、図3を用
いて説明する。接合すべき半導体素子3の電極パッド上
に形成したバンプ4に導電性接着剤5を転写付着させ、
フリップチップ実装用として形成した導体電極2を有す
る回路基板1に対向させながら、半導体素子3を吸着し
たチップヘッドを一定速度で徐々に降下させ、導体電極
2とバンプ4とを精度良く位置合わせしながら圧着し、
その後に封止樹脂を注入し硬化して、フリップチップ実
装を行っていた。
A circuit board for flip-chip mounting using a conventional circuit board and a mounting method will be described below with reference to FIG. A conductive adhesive 5 is transferred and attached to the bumps 4 formed on the electrode pads of the semiconductor element 3 to be joined,
While facing the circuit board 1 having the conductor electrodes 2 formed for flip-chip mounting, the chip head holding the semiconductor elements 3 is gradually lowered at a constant speed, and the conductor electrodes 2 and the bumps 4 are accurately aligned. While crimping,
Thereafter, a sealing resin was injected and cured, and flip-chip mounting was performed.

【0004】[0004]

【発明が解決しようとする課題】しかし、従来のフリッ
プチップ実装用回路基板は、焼成後の回路基板1の表面
平滑度が数十乃至100μm程度の凹凸があるために、
その表面上にスクリーン印刷などで形成した複数の導体
電極2の表面間にも数十乃至100μm程度の凹凸がそ
のまま残っていた。このような回路基板1に対して導電
性接着剤5を使ってフリップチップ実装すると、付着さ
れている導電性接着剤5の量が一定であったとしても、
導体電極2とバンプ4との各接続部において、一部の接
続部では接着が十分でないものが見られたり、接続の不
安定なものがあったりするなど、接続抵抗値のバラツキ
が生じていた。また、導電性接着剤5の付着量の差があ
る場合などには、導電性接着剤5が導体電極2に接着し
ないというような接続不良が発生することなど、製造上
の接続歩留まりが低くなるという不具合も生じていた。
上記のような接続抵抗値のバラツキのある実装品を電子
機器装置の部品として使用した場合には、一部の電極端
子の接続抵抗値が高いことにより、電子機器装置の動作
不良を生じるおそれがあるなどの問題があった。
However, in the conventional flip-chip mounting circuit board, the surface smoothness of the fired circuit board 1 has irregularities of about several tens to about 100 μm.
Irregularities of about several tens to 100 μm remained between the surfaces of the plurality of conductor electrodes 2 formed by screen printing or the like on the surface. When flip-chip mounting is performed on such a circuit board 1 using the conductive adhesive 5, even if the amount of the conductive adhesive 5 attached is constant,
At each connection between the conductor electrode 2 and the bump 4, there were variations in the connection resistance value such that some of the connections were not sufficiently bonded or some of the connections were unstable. . In addition, when there is a difference in the amount of the conductive adhesive 5 attached, a connection failure in manufacturing such as a connection failure such that the conductive adhesive 5 does not adhere to the conductor electrode 2 is reduced, and the connection yield in manufacturing is reduced. There was also a problem that.
When a mounted product having a variation in connection resistance as described above is used as a component of an electronic device, a malfunction of the electronic device may occur due to a high connection resistance of some of the electrode terminals. There was such a problem.

【0005】[0005]

【課題を解決するための手段】前記課題を解決するため
に、本発明のフリップチップ実装用回路基板は、回路基
板の表面の所定の位置に形成された複数の導体電極を、
その複数の導体電極の表面が同一平面となるように導体
電極の表面を研磨したことを特徴とするものであり、電
極パッドと電極導体部との接続が安定し、接続抵抗値も
低く抑えることが可能となり、高い歩留まりを有する半
導体装置を提供することができる。また、電極表面に生
じた酸化物や付着物等の膜が研磨によって除去できるた
め、酸化物や付着物による抵抗値上昇を防ぐことがで
き、低抵抗値で安定した接続をも実現できる。
In order to solve the above-mentioned problems, a flip-chip mounting circuit board according to the present invention comprises a plurality of conductor electrodes formed at predetermined positions on the surface of the circuit board.
The surface of the conductor electrode is polished so that the surfaces of the plurality of conductor electrodes are flush with each other, so that the connection between the electrode pad and the electrode conductor portion is stable and the connection resistance value is also low. And a semiconductor device having a high yield can be provided. Further, since a film such as an oxide or a deposit formed on the surface of the electrode can be removed by polishing, an increase in the resistance value due to the oxide or the deposit can be prevented, and a stable connection with a low resistance value can be realized.

【0006】[0006]

【発明の実施の形態】本発明の請求項1に記載の発明
は、回路基板の表面の所定の位置に形成された複数の導
体電極を、その複数の導体電極の表面が同一平面となる
ように前記導体電極の表面を研磨したことを特徴とする
フリップチップ実装用回路基板であり、導電性接着剤を
用いたフリップチップ実装において、接続用導体電極の
表面位置が揃った基板を実装用基板として使用すること
により、安定して高い歩留まりを有した半導体装置を提
供することが可能となり、また、導体電極表面に生じた
酸化物や付着物等の膜が研磨によって除去できるため、
酸化物や付着物による抵抗値上昇を防ぐことができ、低
抵抗値で安定した接続をも実現できる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, a plurality of conductor electrodes formed at predetermined positions on a surface of a circuit board are arranged so that the surfaces of the plurality of conductor electrodes are flush with each other. A circuit board for flip-chip mounting, characterized in that the surface of the conductor electrode is polished, and in flip-chip mounting using a conductive adhesive, a substrate in which the surface positions of the connection conductor electrodes are aligned with a mounting board By using as a, it becomes possible to provide a semiconductor device having a stable and high yield, and since a film such as an oxide or a deposit generated on the surface of the conductor electrode can be removed by polishing,
It is possible to prevent an increase in resistance value due to oxides and deposits, and to realize a stable connection with a low resistance value.

【0007】次に、本発明の請求項2に記載の発明は、
前記複数の導体電極の表面間の凹凸が10μm以下に研
磨されていることを特徴とする請求項1に記載のフリッ
プチップ実装用回路基板であり、回路基板に形成された
導体電極の表面間の凹凸を10μm以下に規制すること
により、安定して高い歩留まりで半導体装置が製造でき
る。
Next, the invention according to claim 2 of the present invention is:
2. The flip-chip mounting circuit board according to claim 1, wherein unevenness between the surfaces of the plurality of conductor electrodes is polished to 10 μm or less, and between the surfaces of the conductor electrodes formed on the circuit board. 3. By regulating the unevenness to 10 μm or less, a semiconductor device can be manufactured stably with a high yield.

【0008】次に、本発明の請求項3に記載の発明は、
回路基板の所定の複数位置にカーボン系材料のペースト
にて成膜した後、前記膜の表面が同一平面になるように
研磨して形成された導電層の表面に、導電性のダイヤモ
ンド・ライク・カーボン膜を形成して、半導体素子を接
続する導体電極としたことを特徴とするフリップチップ
実装用回路基板であり、導電層の各表面に、導電性のダ
イヤモンド・ライク・カーボン膜を形成したことによ
り、酸化による抵抗値の増加はなくなるものである。
Next, the invention according to claim 3 of the present invention provides:
After a film of carbon-based material is formed at a plurality of predetermined positions on a circuit board, the surface of the film is polished so that the surface of the film is flush with the surface of the film. A flip-chip mounting circuit board characterized in that a carbon film is formed as a conductor electrode for connecting a semiconductor element, and a conductive diamond-like carbon film is formed on each surface of the conductive layer. Thus, the increase in resistance value due to oxidation is eliminated.

【0009】次に、本発明の請求項4に記載の発明は、
回路基板の表面の所定の位置に複数の導体電極を形成し
た後、その複数の導体電極の表面が同一平面となるよう
に導体電極の表面を研磨し、接合すべき半導体素子の電
極パッドに導電性接着剤を付着した状態で、前記電極パ
ッドとを前記半導体電極に圧接せしめて、その電極パッ
ドと導体電極とを電気的に接続することを特徴とするフ
リップチップ実装方法であり、接続用導体電極の表面位
置が揃った基板を実装用基板として使用することによ
り、安定して高い歩留まりを有した半導体装置を提供す
ることが可能となるとともに、導体電極表面に生じた酸
化物や付着物等の膜が研磨によって除去できるため、酸
化物や付着物による抵抗値上昇を防ぐことができ、低抵
抗値で安定した接続をも実現できる。
Next, the invention described in claim 4 of the present invention is:
After a plurality of conductor electrodes are formed at predetermined positions on the surface of the circuit board, the surfaces of the plurality of conductor electrodes are polished so that the surfaces of the plurality of conductor electrodes are flush with each other. A flip-chip mounting method, wherein the electrode pad is pressed against the semiconductor electrode in a state where a conductive adhesive is adhered, and the electrode pad and the conductive electrode are electrically connected. By using a substrate having the same electrode position as the mounting substrate, it is possible to provide a semiconductor device having a stable and high yield and to provide oxides and deposits generated on the conductor electrode surface. Since the film can be removed by polishing, it is possible to prevent an increase in resistance value due to an oxide or a deposit, and to realize a stable connection with a low resistance value.

【0010】次に、本発明の請求項5に記載の発明は、
前記複数の導体電極の表面間の凹凸を10μm以下に研
磨することを特徴とする請求項4に記載のフリップチッ
プ実装方法であり、回路基板に形成された導体電極の表
面の凹凸を10μm以下に規制することにより、安定し
て高い歩留まりで半導体装置が製造できる。
Next, the invention described in claim 5 of the present invention is:
The flip-chip mounting method according to claim 4, wherein the unevenness between the surfaces of the plurality of conductive electrodes is polished to 10 µm or less, and the unevenness on the surface of the conductive electrodes formed on the circuit board is set to 10 µm or less. By regulating, a semiconductor device can be manufactured stably with a high yield.

【0011】次に、本発明の請求項6に記載の発明は、
回路基板の表面の所定の複数位置にカーボン系材料のペ
ーストにて導電層を形成した後、その複数の導電層の表
面が同一平面となるように導電層の表面を研磨し、その
研磨された導電層の表面に導電性のダイヤモンド・ライ
ク・カーボン膜を形成することにより導体電極を形成
し、接合すべき半導体素子の電極パッドに導電性接着剤
を付着した状態で、前記電極パッドとを前記半導体電極
に圧接せしめて、その電極パッドと導体電極とを電気的
に接続することを特徴とするフリップチップ実装方法で
あり、導電性接着剤を用いたフリップチップ実装におい
て、接続用導体電極の電極表面に平滑面を有した基板を
実装用基板として使用することにより、安定して高い歩
留まりを有した半導体装置を提供することができる。ま
た、導体電極の表面は、導電性のダイヤモンド・ライク
・カーボン膜で覆われているため、酸化物や付着物が覆
うことによる抵抗値上昇を防ぐことができる。
Next, the invention according to claim 6 of the present invention is as follows:
After forming a conductive layer with a carbon-based material paste at a plurality of predetermined positions on the surface of the circuit board, the surface of the conductive layer is polished so that the surfaces of the plurality of conductive layers are flush with each other, and the polished surface is polished. A conductive electrode is formed by forming a conductive diamond-like carbon film on the surface of the conductive layer, and the electrode pad is connected to the electrode pad while a conductive adhesive is attached to the electrode pad of the semiconductor element to be joined. A flip-chip mounting method characterized in that a semiconductor electrode is pressed into contact and an electrode pad and a conductive electrode are electrically connected. In flip-chip mounting using a conductive adhesive, an electrode of a connecting conductive electrode is provided. By using a substrate having a smooth surface on the surface as a mounting substrate, a semiconductor device having a stable and high yield can be provided. Further, since the surface of the conductor electrode is covered with the conductive diamond-like carbon film, it is possible to prevent the resistance value from increasing due to the covering of the oxide or the deposit.

【0012】(実施の形態1)以下、本発明の請求項1
ないし請求項6に記載された発明の実施の形態につい
て、図1を用いて説明する。
(Embodiment 1) Hereinafter, claim 1 of the present invention will be described.
An embodiment of the invention described in claim 6 will be described with reference to FIG.

【0013】図1において、回路基板1はセラミック基
板で構成されており、焼成された回路基板1上の所定の
位置には、銀−パラジウム導体等で形成された複数の導
体電極2がスクリーン印刷にて形成されている。前述の
ように、通常のセラミック回路基板では、焼成後の基板
表面の表面平滑度が数十乃至100μm程度の凹凸であ
るため、基板表面上にスクリーン印刷で形成した複数の
導体電極2の表面間にも少なくとも数十乃至100μm
程度の高低差が生じていた。そこで、本発明において
は、導体電極2の形成後に、回路基板1の半導体実装領
域の少なくとも一部の導体電極2の電極表面を研磨し
て、複数の導体電極2の電極表面の高さを揃え同一平面
の平坦面6を有した構造にする。かかる構成により上記
のような不具合は解決され、半導体素子の電極パッドに
形成したバンプ4と導体電極2とが確実に接着できる。
In FIG. 1, a circuit board 1 is composed of a ceramic substrate, and a plurality of conductor electrodes 2 formed of a silver-palladium conductor or the like are screen-printed at predetermined positions on the fired circuit board 1. Is formed. As described above, in the case of a normal ceramic circuit substrate, the surface smoothness of the fired substrate surface is unevenness of about several tens to 100 μm, so that the surface of the plurality of conductor electrodes 2 formed by screen printing on the substrate surface is reduced. At least several tens to 100 μm
There was a difference in elevation. Therefore, in the present invention, after the formation of the conductor electrodes 2, at least a part of the electrode surfaces of the conductor electrodes 2 in the semiconductor mounting region of the circuit board 1 is polished to make the heights of the electrode surfaces of the plurality of conductor electrodes 2 uniform. A structure having the same flat surface 6 is adopted. With such a configuration, the above-mentioned disadvantages are solved, and the bumps 4 formed on the electrode pads of the semiconductor element and the conductor electrodes 2 can be securely bonded.

【0014】前記電極導体2の表面の研磨は、平滑な面
を有した研削盤などを使って研磨し、研磨を施した複数
の電極導体2の表面間の凹凸が10μm以下の平坦度を
有した平坦面6を得る。研削盤の研削用材料は磨耗に耐
える硬い物質で、かつ、研削クズが発生しても簡易的に
除去できる材料でなければならない。さらに、本発明の
回路基板の構成によれば、電極導体2を形成した後に時
間の経過とともに電極導体2の電極表面上を覆うように
生じた酸化物や付着物等の膜が研磨によってすべて除去
できるため、酸化物や付着物による抵抗値上昇を防ぐこ
とができ、低抵抗値のまま安定した接続をも実現でき
る。
The surface of the electrode conductor 2 is polished using a grinder having a smooth surface, and the unevenness between the polished surface of the plurality of electrode conductors 2 has a flatness of 10 μm or less. Obtained flat surface 6 is obtained. The grinding material of the grinder must be a hard substance that can withstand abrasion and a material that can be easily removed even if grinding flaws occur. Further, according to the configuration of the circuit board of the present invention, after the electrode conductor 2 is formed, a film such as an oxide or an adhering substance generated so as to cover the electrode surface of the electrode conductor 2 with the passage of time is entirely removed by polishing. Therefore, it is possible to prevent an increase in the resistance value due to oxides and deposits, and to realize a stable connection with a low resistance value.

【0015】(実施の形態2)上記の酸化物や付着物が
覆うことによる抵抗値上昇を防ぐという課題をより確実
に解決する回路基板1の製造方法について、図2を用い
て説明する。
(Embodiment 2) A method of manufacturing a circuit board 1 that more reliably solves the problem of preventing an increase in the resistance value due to the above-mentioned covering by an oxide or a deposit will be described with reference to FIG.

【0016】図2において、回路基板1上の所定の位置
にある複数の導電層7は、カーボン系ペースト材料を用
いてスクリーン印刷にてカーボン膜を成膜した後、60
0℃〜800℃程度で焼成して形成される。その後、回
路基板1の半導体素子実装領域の導電層7の表面を平滑
な面を有した研削盤などで研磨を行い、研磨を施し領域
の表面粗さが10μm以下となる平坦面を得る。最後
に、研磨した導電層7の表面の上に0.1μm以下の薄
い導電性のDLC(ダイヤモンド・ライク・カーボン)
膜8をスパッタ法もしくはレーザーアブレーション法等
の方法にて成膜する。DLCは、ダイヤモンドのアモル
ファス的な構造を持つものであり、ノンドープのDLC
やフッ素、窒素、ホウ素をドープしたDLCが存在する
が、本実施例ではそのいずれでもよい。こうして、研磨
した導電層7の表面上を酸化膜や付着物が覆わないよう
にした導体電極2を有する本発明の回路基板1を得る。
In FIG. 2, a plurality of conductive layers 7 at predetermined positions on the circuit board 1 are formed by forming a carbon film by screen printing using a carbon-based paste material.
It is formed by firing at about 0 ° C. to 800 ° C. Thereafter, the surface of the conductive layer 7 in the semiconductor element mounting region of the circuit board 1 is polished with a grinder having a smooth surface or the like to obtain a flat surface having a surface roughness of 10 μm or less. Finally, a thin conductive DLC (diamond-like carbon) of 0.1 μm or less is placed on the polished surface of the conductive layer 7.
The film 8 is formed by a method such as a sputtering method or a laser ablation method. DLC is a non-doped DLC having an amorphous structure of diamond.
There is a DLC doped with fluorine, nitrogen, and boron, but in this embodiment, any of them may be used. Thus, the circuit board 1 of the present invention having the conductor electrodes 2 in which the polished surface of the conductive layer 7 is not covered with the oxide film or the deposit is obtained.

【0017】このような方法で得られた回路基板1に対
して、回路基板1の導体電極2と半導体素子3のバンプ
4とを精度良く位置合わせしながら接続し、さらに、導
電性接着剤5を硬化させ、半導体素子3と回路基板1の
隙間に封止樹脂を注入したのち、封止樹脂を硬化してフ
リップチップ実装体を得ることができる。
The conductor electrodes 2 of the circuit board 1 and the bumps 4 of the semiconductor element 3 are connected to the circuit board 1 obtained by such a method while accurately aligning the conductive electrodes 2 and the conductive adhesive 5. Is cured, a sealing resin is injected into a gap between the semiconductor element 3 and the circuit board 1, and then the sealing resin is cured to obtain a flip-chip mounted body.

【0018】[0018]

【発明の効果】以上のように本発明の回路基板によれ
ば、回路基板の電極導体の導体表面に研磨を施して導体
表面間の凹凸を除去しているため、フリップチップ実装
する場合において、回路基板の導体電極と半導体素子の
バンプとが安定して接続でき、接続部もバラツキのない
低い抵抗値が得られ、高い歩留まりを有する半導体装置
を提供できるという有利な効果が得られる。また、酸化
物や付着物が覆うことによる接続抵抗値の上昇を防ぐと
いう有利な効果も得られる。
As described above, according to the circuit board of the present invention, the conductor surface of the electrode conductor of the circuit board is polished to remove irregularities between the conductor surfaces. The conductive electrode of the circuit board and the bump of the semiconductor element can be stably connected, the connection portion has a low resistance value without variation, and the advantageous effect that a semiconductor device having a high yield can be provided can be obtained. In addition, an advantageous effect of preventing an increase in connection resistance value due to the covering with an oxide or a deposit can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のフリップチップ実装方法の接合行程を
模式的に示す側面図
FIG. 1 is a side view schematically showing a bonding process of a flip chip mounting method according to the present invention.

【図2】本発明の第2の実施例に示す導体電極の構造を
模式的に示す側面図
FIG. 2 is a side view schematically showing a structure of a conductor electrode according to a second embodiment of the present invention.

【図3】従来のフリップチップ実装方法の接合行程を模
式的に示す側面図
FIG. 3 is a side view schematically showing a bonding process of a conventional flip chip mounting method.

【符号の説明】[Explanation of symbols]

1 実装用回路基板 2 導体電極 3 半導体素子 4 バンプ 5 導電性接着剤 6 研磨による平滑面 7 導電層 8 DLC膜 DESCRIPTION OF SYMBOLS 1 Circuit board for mounting 2 Conductive electrode 3 Semiconductor element 4 Bump 5 Conductive adhesive 6 Smooth surface by grinding 7 Conductive layer 8 DLC film

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】 回路基板の表面の所定の位置に形成され
た複数の導体電極を、その複数の導体電極の表面が同一
平面となるように前記導体電極の表面を研磨したことを
特徴とするフリップチップ実装用回路基板。
1. A plurality of conductor electrodes formed at predetermined positions on a surface of a circuit board, wherein the surfaces of the plurality of conductor electrodes are polished so that the surfaces of the plurality of conductor electrodes are flush with each other. Circuit board for flip chip mounting.
【請求項2】 前記複数の導体電極の表面間の凹凸が1
0μm以下に研磨されていることを特徴とする請求項1
に記載のフリップチップ実装用回路基板。
2. The method according to claim 1, wherein the unevenness between the surfaces of the plurality of conductor electrodes is one.
2. The polishing method according to claim 1, wherein the polishing is performed to a thickness of 0 μm or less.
4. The flip-chip mounting circuit board according to claim 1.
【請求項3】 回路基板の所定の複数位置にカーボン系
材料のペーストにて成膜した後、前記膜の表面が同一平
面になるように研磨して形成された導電層の表面に、導
電性のダイヤモンド・ライク・カーボン膜を形成して、
半導体素子を接続する導体電極としたことを特徴とする
フリップチップ実装用回路基板。
3. A conductive layer formed by forming a film of carbon-based material at a plurality of predetermined positions on a circuit board and polishing the surface of the film so that the surface of the film is flush with the surface of the conductive layer. Forming a diamond-like carbon film of
A circuit board for flip-chip mounting, comprising a conductor electrode for connecting a semiconductor element.
【請求項4】 回路基板の表面の所定の位置に複数の導
体電極を形成した後、その複数の導体電極の表面が同一
平面となるように導体電極の表面を研磨し、接合すべき
半導体素子の電極パッドに導電性接着剤を付着した状態
で、前記電極パッドとを前記半導体電極に圧接せしめ
て、その電極パッドと導体電極とを電気的に接続するこ
とを特徴とするフリップチップ実装方法。
4. A semiconductor element to be joined after a plurality of conductor electrodes are formed at predetermined positions on a surface of a circuit board, and the surfaces of the conductor electrodes are polished so that the surfaces of the plurality of conductor electrodes are flush with each other. Flip-chip mounting, wherein said electrode pad is pressed against said semiconductor electrode in a state where a conductive adhesive is adhered to said electrode pad, and said electrode pad and said conductive electrode are electrically connected.
【請求項5】 前記複数の導体電極の表面間の凹凸を1
0μm以下に研磨することを特徴とする請求項4に記載
のフリップチップ実装方法。
5. The method according to claim 1, wherein unevenness between surfaces of the plurality of conductor electrodes is reduced by one.
5. The flip chip mounting method according to claim 4, wherein the polishing is performed to a thickness of 0 [mu] m or less.
【請求項6】 回路基板の表面の所定の複数位置にカー
ボン系材料のペーストにて導電層を形成した後、その複
数の導電層の表面が同一平面となるように導電層の表面
を研磨し、その研磨された導電層の表面に導電性のダイ
ヤモンド・ライク・カーボン膜を形成することにより導
体電極を形成し、接合すべき半導体素子の電極パッドに
導電性接着剤を付着した状態で、前記電極パッドとを前
記半導体電極に圧接せしめて、その電極パッドと導体電
極とを電気的に接続することを特徴とするフリップチッ
プ実装方法。
6. A conductive layer is formed at a plurality of predetermined positions on the surface of a circuit board using a carbon-based material paste, and the surfaces of the conductive layers are polished so that the surfaces of the plurality of conductive layers are flush with each other. Forming a conductive electrode by forming a conductive diamond-like carbon film on the surface of the polished conductive layer, and attaching a conductive adhesive to an electrode pad of a semiconductor element to be joined; A flip chip mounting method, wherein an electrode pad is pressed against the semiconductor electrode to electrically connect the electrode pad and the conductor electrode.
JP27419699A 1999-09-28 1999-09-28 Circuit board for flip chip mounting and flip chip mounting method using the same Expired - Fee Related JP3414332B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27419699A JP3414332B2 (en) 1999-09-28 1999-09-28 Circuit board for flip chip mounting and flip chip mounting method using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27419699A JP3414332B2 (en) 1999-09-28 1999-09-28 Circuit board for flip chip mounting and flip chip mounting method using the same

Publications (2)

Publication Number Publication Date
JP2001102408A true JP2001102408A (en) 2001-04-13
JP3414332B2 JP3414332B2 (en) 2003-06-09

Family

ID=17538382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27419699A Expired - Fee Related JP3414332B2 (en) 1999-09-28 1999-09-28 Circuit board for flip chip mounting and flip chip mounting method using the same

Country Status (1)

Country Link
JP (1) JP3414332B2 (en)

Also Published As

Publication number Publication date
JP3414332B2 (en) 2003-06-09

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