JP2001094056A - Semiconductor integrated circuit and manufacturing method therefor - Google Patents

Semiconductor integrated circuit and manufacturing method therefor

Info

Publication number
JP2001094056A
JP2001094056A JP27011599A JP27011599A JP2001094056A JP 2001094056 A JP2001094056 A JP 2001094056A JP 27011599 A JP27011599 A JP 27011599A JP 27011599 A JP27011599 A JP 27011599A JP 2001094056 A JP2001094056 A JP 2001094056A
Authority
JP
Japan
Prior art keywords
integrated circuit
protective film
semiconductor integrated
electrode
positive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27011599A
Other languages
Japanese (ja)
Inventor
Kimitaka Yokoo
公孝 横尾
Hiroaki Monjuji
弘明 文珠寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Victor Company of Japan Ltd
Original Assignee
Victor Company of Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company of Japan Ltd filed Critical Victor Company of Japan Ltd
Priority to JP27011599A priority Critical patent/JP2001094056A/en
Publication of JP2001094056A publication Critical patent/JP2001094056A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit that can be manufactured with a simple process and less manufacturing costs, so that a solution used in the process can be subjected easily to waste liquid treatment. SOLUTION: In this semiconductor integrated circuit with a semiconductor integrated circuit, where a semiconductor element is formed and a protective film formed on the semiconductor integrated circuit, the protective film is made of an inorganic insulation film and an organic insulation resin with positive photosensitive property.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の形成
された半導体集積回路基板上の電極を覆って形成した保
護膜を、その電極と外部電極とを接続するための電極引
出し用のスルーホールを保護膜に形成するのに好適な構
成とした半導体集積回路及びその製造方法に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a protective film formed on a semiconductor integrated circuit substrate on which a semiconductor element is formed by covering the electrode with a through hole for leading an electrode for connecting the electrode to an external electrode. And a method of manufacturing the semiconductor integrated circuit having a structure suitable for forming a semiconductor integrated circuit on a protective film.

【0002】[0002]

【従来の技術】以下、添付図面を参照して、従来例の半
導体集積回路の製造方法を説明する。図2は、従来例の
半導体集積回路の製造方法を説明するための工程図であ
る。まず、半導体素子(LSI)が形成された半導体集
積回路基板2には、外部電極と接続されるべき電極1が
形成されており、この上に無機絶縁性保護膜10(単
に、無機保護膜ともいう)が形成される(図2の
(a))。
2. Description of the Related Art A conventional method for manufacturing a semiconductor integrated circuit will be described below with reference to the accompanying drawings. FIG. 2 is a process chart for explaining a conventional method for manufacturing a semiconductor integrated circuit. First, an electrode 1 to be connected to an external electrode is formed on a semiconductor integrated circuit substrate 2 on which a semiconductor element (LSI) is formed, and an inorganic insulating protective film 10 (simply referred to as an inorganic protective film) is formed thereon. Is formed (FIG. 2A).

【0003】次に、無機絶縁性保護膜10の上にポジ型
フォトレジスト30が塗布され、仮乾燥される(図2の
(b))。次に、ポジ型レチクル40により、電極1の
上部の、スルーホールをあけたい部分のポジ型レジスト
30に光41を照射し、露光部31を形成する(図2の
(c))。
Next, a positive photoresist 30 is applied on the inorganic insulating protective film 10 and is preliminarily dried (FIG. 2B). Next, light 41 is irradiated to the portion of the positive resist 30 above the electrode 1 where a through hole is to be formed by the positive reticle 40 to form an exposed portion 31 (FIG. 2C).

【0004】次に、ポジ型フォトレジスト30を非溶剤
系水溶液、例えばのNMD−3(東京応化工業(株)
製)等で現像し、露光部31を除去し、スルーホール6
0を形成し、熱硬化によりポジ型フォトレジストを最終
硬化・定着する(図2の(d))。次に、ポジ型フォト
レジスト30をマスクとして、プラズマエッチング等に
より電極1の上の無機絶縁性保護膜10を除去し、電極
1を露出させるスルーホール61を形成する(図2の
(e))。
Next, the positive photoresist 30 is coated with a non-solvent aqueous solution such as NMD-3 (Tokyo Ohka Kogyo Co., Ltd.).
), The exposed portion 31 is removed, and the through hole 6 is removed.
Then, the positive photoresist is finally cured and fixed by thermal curing (FIG. 2 (d)). Next, using the positive photoresist 30 as a mask, the inorganic insulating protective film 10 on the electrode 1 is removed by plasma etching or the like to form a through hole 61 exposing the electrode 1 (FIG. 2E). .

【0005】次に、ポジ型フォトレジスト30を溶解除
去する(図2の(f))。次に、ネガ型有機絶縁性樹脂
70(単に、有機保護膜ともいう)をスルーホール62
に充填すると共に無機絶縁性保護膜10上の全面に被覆
し、仮乾燥し(図2の(g))、速やかに次の工程に移
る。ネガ型レチクル80を所定の位置に配置して、電極
1の上部以外に光81を照射し、ネガ型有機絶縁性樹脂
70の未露光部71を残す。この後直ちに、ポスト・エ
クスポージャ・ベーク(以下、PEBともいう)を行
い、ネガ型有機絶縁性樹脂70の露光後の光反応促進・
安定化を図る(図2の(h))。
Next, the positive photoresist 30 is dissolved and removed (FIG. 2 (f)). Next, a negative type organic insulating resin 70 (also simply referred to as an organic protective film) is passed through the through hole 62.
At the same time, the entire surface of the inorganic insulating protective film 10 is covered and temporarily dried (FIG. 2 (g)), and the process immediately proceeds to the next step. The negative reticle 80 is arranged at a predetermined position, and the light 81 is irradiated to portions other than the upper portion of the electrode 1, leaving the unexposed portion 71 of the negative organic insulating resin 70. Immediately after this, post-exposure bake (hereinafter also referred to as PEB) is performed to promote the photoreaction after exposure of the negative type organic insulating resin 70.
Stabilization is attempted (FIG. 2 (h)).

【0006】次に、有機溶剤系現像液、例えばDV−6
05(東レ(株)社製)により現像し、イソプロピルア
ルコール(以下、IPAともいう)を用いてリンスし、
未露光部71を除去し、スルーホール90を形成し、こ
の後にネガ型有機絶縁性樹脂の70の乾燥を行う(図2
の(i))。これにより、半導体集積回路基板2上に形
成されている、外部電極と接続すべき電極2上にはスル
ーホール90が形成され、回りには無機絶縁性保護膜1
0とネガ型有機絶縁性樹脂70が形成されている。
Next, an organic solvent-based developer such as DV-6
05 (manufactured by Toray Industries, Inc.) and rinsed with isopropyl alcohol (hereinafter also referred to as IPA),
The unexposed portion 71 is removed to form a through hole 90, and thereafter, the negative type organic insulating resin 70 is dried (FIG. 2).
(I)). Thus, a through hole 90 is formed on the electrode 2 formed on the semiconductor integrated circuit substrate 2 to be connected to the external electrode, and the inorganic insulating protective film 1 is formed therearound.
0 and a negative type organic insulating resin 70 are formed.

【0007】[0007]

【発明が解決しようとする課題】ところで、従来の半導
体集積回路基板上の電極上にスルーホールを形成するの
に、2回にわたる露光・現像工程と、ポスト・エクスポ
ージャ・ベークを必要とすること、さらにはネガ型樹脂
の現像液は、危険物第4類第3石油類であるN−メチル
ピロリドン(以下、NMPともいう)を主成分とするも
のであり、リンス液は危険物第4類アルコールであるI
PAであり、これらの廃液の処理にコストが必要とさ
れ、さらに簡便なスルーホール作成方法を実現すること
が課題であった。
However, forming a through-hole on an electrode on a conventional semiconductor integrated circuit substrate requires two exposure and development steps and a post-exposure bake. Further, the developer of the negative type resin is mainly composed of N-methylpyrrolidone (hereinafter also referred to as NMP) which is a dangerous substance of the fourth kind and the third petroleum, and the rinsing liquid is a dangerous substance of the fourth kind. Alcohol I
It is a PA, and processing of these waste liquids requires cost, and it has been a problem to realize a simpler through-hole forming method.

【0008】そこで、本発明は上記課題を解決し、簡略
な工程により、製造コストも少なく、しかも、工程で用
いる溶液を容易に廃液処理可能に、製造できる半導体集
積回路及びその製造方法を提供することを目的とする。
Accordingly, the present invention solves the above-mentioned problems, and provides a semiconductor integrated circuit and a method of manufacturing the semiconductor integrated circuit, which can be manufactured by a simple process, the manufacturing cost is low, and the solution used in the process can be easily treated as a waste liquid. The purpose is to:

【0009】[0009]

【課題を解決するための手段】上記目的を達成する手段
として、請求項1に記載の本発明の半導体集積回路は、
半導体素子の形成された半導体集積回路基板とこの半
導体集積回路基板上に形成された保護膜とを有する半導
体集積回路において、前記保護膜を無機絶縁性膜とポジ
型感光性を有する有機絶縁性樹脂とから構成したことを
特徴とする半導体集積回路を提供しようとするものであ
る。
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit according to the present invention.
In a semiconductor integrated circuit having a semiconductor integrated circuit substrate on which a semiconductor element is formed and a protective film formed on the semiconductor integrated circuit substrate, the protective film is formed of an inorganic insulating film and an organic insulating resin having a positive photosensitive property. And a semiconductor integrated circuit characterized by the above.

【0010】また、上記目的を達成するための手段とし
て、請求項2に記載の本発明の半導体集積回路の製造方
法は、半導体集積回路基板上の外部電極と接続されるべ
き電極を覆って形成された無機保護膜と有機保護膜と
に、前記電極を引出すための電極引出し用スルーホール
を形成する半導体集積回路の製造方法において、前記半
導体集積回路基板の上に前記無機保護膜を形成する工程
と、前記無機保護膜上にポジ型感光性を有する前記有機
保護膜を形成する工程と、前記有機保護膜上にポジ型感
光性樹脂を塗布する工程と、前記電極の上の前記有機保
護膜と前記感光性樹脂とに所定形状の前記スルーホール
を、露光・現像により形成する工程と、前記スルーホー
ルを通して、前記電極の上の前記無機保護膜をエッチン
グし、前記電極を露出させる工程とを有することを特徴
とする半導体集積回路の製造方法を提供しようとするも
のである。
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit according to the present invention, which covers an electrode to be connected to an external electrode on a semiconductor integrated circuit substrate. Forming an inorganic protective film on the semiconductor integrated circuit substrate in a method of manufacturing a semiconductor integrated circuit in which electrode through holes for extracting the electrodes are formed in the formed inorganic protective film and organic protective film. Forming the organic protective film having a positive photosensitive property on the inorganic protective film, applying a positive photosensitive resin on the organic protective film, and forming the organic protective film on the electrode; Forming the through hole of a predetermined shape in the photosensitive resin by exposure and development; and etching the inorganic protective film on the electrode through the through hole to expose the electrode. Is intended to provide a method of manufacturing a semiconductor integrated circuit, characterized in that it comprises a step of.

【0011】[0011]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図1は、本発明による半導
体集積回路の製造方法の実施例を説明するための工程図
である。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a process chart for explaining an embodiment of a method of manufacturing a semiconductor integrated circuit according to the present invention.

【0012】まず、半導体素子(LSI)が形成された
半導体集積回路基板2には、外部電極と接続されるべき
電極1が形成されており、この上に無機絶縁性保護膜1
0(単に、無機保護膜ともいう)が形成される。無機絶
縁性保護膜10は、LSIの劣化原因となる水分やアル
カリイオン等の汚染物質の侵入を防ぐためのもので、例
えば、CVD法によりSiO2膜またはSiN膜あるい
はそれらの多層膜が用いられる。
First, an electrode 1 to be connected to an external electrode is formed on a semiconductor integrated circuit substrate 2 on which a semiconductor element (LSI) is formed, and an inorganic insulating protective film 1 is formed thereon.
0 (also simply referred to as an inorganic protective film) is formed. The inorganic insulating protective film 10 is for preventing intrusion of contaminants such as moisture and alkali ions which cause deterioration of the LSI. For example, a SiO 2 film, a SiN film, or a multilayer film thereof is used by a CVD method. .

【0013】ここでは、プラズマCVD装置により、S
iH4/N2O混合ガスを用いて約8μm厚さのSiO2
膜を形成し、さらに同様にプラズマCVD装置により、
SiH4/NH3/N2混合ガスを用いて約4μm厚さの
SiN膜を形成した(図1の(a))。
In this case, S
About 8 μm thick SiO 2 using iH 4 / N 2 O mixed gas
A film is formed, and similarly, by a plasma CVD device,
An SiN film having a thickness of about 4 μm was formed using a mixed gas of SiH 4 / NH 3 / N 2 (FIG. 1A).

【0014】次に、無機絶縁性保護膜10の上に、ポジ
型感光性を有する有機絶縁性樹脂20(以下単に、ポジ
型有機樹脂ともいう)を形成する。なお、ポジ型有機樹
脂20は、有機絶縁性保護膜となり、最終的にプラスチ
ック・パッケージで集積回路を封止する際、例えばエポ
キシ樹脂からなる封止剤から、集積回路表面が受ける応
力を緩和するバッファー膜になる。
Next, an organic insulating resin 20 having a positive type photosensitivity (hereinafter, also simply referred to as a positive type organic resin) is formed on the inorganic insulating protective film 10. The positive type organic resin 20 becomes an organic insulating protective film, and when the integrated circuit is finally sealed with a plastic package, the stress applied to the surface of the integrated circuit is reduced by a sealing agent made of, for example, an epoxy resin. Becomes a buffer membrane.

【0015】ポジ型有機樹脂20としては、例えばCR
C−8300(住友ベークライト(株)社製:ポリイミド
系ポジ型感光性樹脂)をスピンナーにて塗布し、120
℃でのプリベーク後、約10μm厚さのポジ型有機樹脂
20の膜を得た(図1の(b))。次に、このポジ型有
機樹脂20の上に、ポジ型フォトレジスト30、例えば
THMR−iP3450(東京応化工業(株)社製)を
スピンコートにて塗布し、110℃でプリベークし、約
1μm厚さのポジ型フォトレジスト30の膜を形成した
(図1の(c))。
As the positive type organic resin 20, for example, CR
C-8300 (manufactured by Sumitomo Bakelite Co., Ltd .: polyimide-based positive photosensitive resin) is applied with a spinner,
After pre-baking at a temperature of about 10 ° C., a film of the positive type organic resin 20 having a thickness of about 10 μm was obtained (FIG. 1B). Next, on this positive type organic resin 20, a positive type photoresist 30, for example, THMR-iP3450 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is applied by spin coating, and prebaked at 110 ° C. to have a thickness of about 1 μm. A positive photoresist 30 film was formed (FIG. 1C).

【0016】次に、ポジ型レチクル40を所定の位置に
配置し、i−ラインステッパを用いて、電極2上のポジ
型有機樹脂20及びポジ型フォトレジスト30の所定部
分に、一括して光41を照射し、ポジ型有機樹脂20の
露光部21及びポジ型フォトレジスト30の露光部31
を同時に形成した(図1の(d))。
Next, the positive type reticle 40 is arranged at a predetermined position, and light is collectively applied to predetermined portions of the positive type organic resin 20 and the positive type photoresist 30 on the electrode 2 using an i-line stepper. 41, the exposed portion 21 of the positive organic resin 20 and the exposed portion 31 of the positive photoresist 30
Was simultaneously formed (FIG. 1 (d)).

【0017】次に、非溶剤系アルカリ水溶液、例えばテ
トラメチルアンモニウムハイドロオキサイド(TMA
H)2.38%溶液を用いて、ポジ型有機樹脂20及び
ポジ型フォトレジスト30を同時に現像し、純水でリン
スして、それぞれの露光部21及び露光部31を除去
し、スルーホール50を形成し、110℃でポジ型フォ
トレジスト30の後乾燥・硬化を行った(図1の
(e))。
Next, a non-solvent aqueous alkaline solution, for example, tetramethylammonium hydroxide (TMA)
H) The positive-type organic resin 20 and the positive-type photoresist 30 are simultaneously developed using a 2.38% solution, and rinsed with pure water to remove the respective exposed portions 21 and 31 and remove the through holes 50. After drying at 110 ° C., the positive photoresist 30 was dried and cured (FIG. 1E).

【0018】次に、スルーホール50を通して、例えば
プラズマエッチング装置を用い、無機絶縁性保護膜10
のエッチングを行う。この時、マスクとしては、ポジ型
有機樹脂20及びポジ型フォトレジスト30の二重膜を
用い、導入ガスとしては、SiN膜には、CF4/Ar
/O2混合ガスを、SiO2膜には、CHF3/CF4/A
r混合ガスをそれぞれ用いる。このエッチングにより、
電極1に達するスルーホール51を形成した(図1の
(f))。
Next, the inorganic insulating protective film 10 is passed through the through hole 50 using, for example, a plasma etching apparatus.
Is etched. At this time, a double film of the positive organic resin 20 and the positive photoresist 30 is used as a mask, and CF 4 / Ar is used as a gas to be introduced into the SiN film.
/ O 2 mixed gas, the SiO 2 film, CHF 3 / CF 4 / A
r mixed gas is used. By this etching,
A through hole 51 reaching the electrode 1 was formed (FIG. 1 (f)).

【0019】次に、ポジ型フォトレジスト30を、剥離
溶液を用いて、溶解除去する。こうして、集積回路基板
2上の電極部にスルーホール52を形成し、この後、3
50℃でポジ型有機樹脂20の乾燥を行った(図1の
(g))。
Next, the positive photoresist 30 is dissolved and removed using a stripping solution. In this way, a through hole 52 is formed in the electrode portion on the integrated circuit board 2 and thereafter,
The positive type organic resin 20 was dried at 50 ° C. ((g) in FIG. 1).

【0020】以上の説明より分かるように、本発明の集
積回路においては、無機絶縁性保護膜の上に感光性を有
するポジ型有機樹脂とポジ型フォトレジストとが形成さ
れているので、一回の一括露光現像処理することによっ
て、スルーホールを形成することができ、それにより、
露光・現像工程の削減を図ることができ、リードタイム
の短縮及び製造コストの低減を実現できる。また、ネガ
型有機絶縁性樹脂を使用する必要がないことより、有機
溶剤系の現像液を使用しないので、廃液処理の設備及び
処理のコストが不要であり、製造コストを大幅に低減で
きる。
As can be understood from the above description, in the integrated circuit of the present invention, since the positive type organic resin and the positive type photoresist having photosensitivity are formed on the inorganic insulating protective film, the integrated circuit is formed once. By performing the batch exposure and development processing, through holes can be formed,
Exposure / development steps can be reduced, and lead time and manufacturing cost can be reduced. Further, since there is no need to use a negative-type organic insulating resin, and no organic solvent-based developer is used, waste liquid processing equipment and processing costs are unnecessary, and manufacturing costs can be significantly reduced.

【0021】[0021]

【発明の効果】以上説明したように、請求項1に記載の
本発明の半導体集積回路は、半導体素子の形成された半
導体集積回路基板とこの半導体集積回路基板上に形成さ
れた保護膜とを有する半導体集積回路において、前記保
護膜を無機絶縁性膜とポジ型感光性を有する有機絶縁性
樹脂とから構成したことにより、簡略な工程により、製
造コストも少なく、しかも、工程で用いる溶液を容易に
廃液処理可能に、製造できる半導体集積回路を提供する
ことができるという効果がある。
As described above, the semiconductor integrated circuit according to the first aspect of the present invention comprises a semiconductor integrated circuit substrate on which a semiconductor element is formed and a protective film formed on the semiconductor integrated circuit substrate. In the semiconductor integrated circuit having the above, since the protective film is composed of the inorganic insulating film and the organic insulating resin having positive photosensitivity, the manufacturing cost is reduced by a simple process, and the solution used in the process is easily manufactured. In addition, there is an effect that a semiconductor integrated circuit that can be manufactured so that waste liquid can be treated can be provided.

【0022】また、以上説明したように、請求項2に記
載の本発明の半導体集積回路の製造方法は、半導体集積
回路基板上の外部電極と接続されるべき電極を覆って形
成された無機保護膜と有機保護膜とに、前記電極を引出
すための電極引出し用スルーホールを形成する半導体集
積回路の製造方法において、前記半導体集積回路基板の
上に前記無機保護膜を形成する工程と、前記無機保護膜
上にポジ型感光性を有する前記有機保護膜を形成する工
程と、前記有機保護膜上にポジ型感光性樹脂を塗布する
工程と、前記電極の上の前記有機保護膜と前記感光性樹
脂とに所定形状の前記スルーホールを、露光・現像によ
り形成する工程と、前記スルーホールを通して、前記電
極の上の前記無機保護膜をエッチングし、前記電極を露
出させる工程とを有することにより、簡略な工程によ
り、製造コストも少なく、しかも、工程で用いる溶液を
容易に廃液処理可能に、製造できる半導体集積回路の製
造方法を提供することができるという効果がある。
Further, as described above, the method of manufacturing a semiconductor integrated circuit according to the second aspect of the present invention provides an inorganic protection circuit formed by covering an electrode to be connected to an external electrode on a semiconductor integrated circuit substrate. In a method for manufacturing a semiconductor integrated circuit, in which a film and an organic protective film are provided with through-holes for extracting electrodes for extracting the electrodes, a step of forming the inorganic protective film on the semiconductor integrated circuit substrate; Forming the organic protective film having positive photosensitivity on the protective film, applying a positive type photosensitive resin on the organic protective film, and forming the organic protective film on the electrode and the photosensitive A step of forming the through hole having a predetermined shape in a resin by exposure and development, and a step of exposing the electrode by exposing the inorganic protective film on the electrode through the through hole. By, by simple process, production cost reduced, moreover, the solution to be easily effluent processing used in step, there is an effect that it is possible to provide a method of manufacturing a semiconductor integrated circuit can be produced.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体集積回路の製造方法の実施
例を説明するための工程図である。
FIG. 1 is a process chart for explaining an embodiment of a method of manufacturing a semiconductor integrated circuit according to the present invention.

【図2】従来例の半導体集積回路の製造方法を説明する
ための工程図である。
FIG. 2 is a process chart for explaining a method of manufacturing a conventional semiconductor integrated circuit.

【符号の説明】[Explanation of symbols]

1 電極 2 半導体集積回路基板 10 無機絶縁性保護膜 20 ポジ型有機絶縁性樹脂 21 露光部 30 ポジ型フォトレジスト 31 露光部 40 ポジ型レチクル 41 光 50 スルーホール 51 スルーホール 52 スルーホール 60 スルーホール 61 スルーホール 62 スルーホール 70 ネガ型有機絶縁性樹脂 80 ネガ型レチクル 81 光 90 スルーホール REFERENCE SIGNS LIST 1 electrode 2 semiconductor integrated circuit board 10 inorganic insulating protective film 20 positive organic insulating resin 21 exposed part 30 positive photoresist 31 exposed part 40 positive reticle 41 light 50 through hole 51 through hole 52 through hole 60 through hole 61 Through hole 62 Through hole 70 Negative organic insulating resin 80 Negative reticle 81 Light 90 Through hole

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体素子の形成された半導体集積回路基
板とこの半導体集積回路基板上に形成された保護膜とを
有する半導体集積回路において、 前記保護膜を無機絶縁性膜とポジ型感光性を有する有機
絶縁性樹脂とから構成したことを特徴とする半導体集積
回路。
1. A semiconductor integrated circuit having a semiconductor integrated circuit substrate on which a semiconductor element is formed and a protective film formed on the semiconductor integrated circuit substrate, wherein the protective film is formed of an inorganic insulating film and a positive photosensitive material. And an organic insulating resin having the same.
【請求項2】半導体集積回路基板上の外部電極と接続さ
れるべき電極を覆って形成された無機保護膜と有機保護
膜とに、前記電極を引出すための電極引出し用スルーホ
ールを形成する半導体集積回路の製造方法において、 前記半導体集積回路基板の上に前記無機保護膜を形成す
る工程と、 前記無機保護膜上にポジ型感光性を有する前記有機保護
膜を形成する工程と、前記有機保護膜上にポジ型感光性
樹脂を塗布する工程と、 前記電極の上の前記有機保護膜と前記感光性樹脂とに所
定形状の前記スルーホールを、露光・現像により形成す
る工程と、 前記スルーホールを通して、前記電極の上の前記無機保
護膜をエッチングし、前記電極を露出させる工程とを有
することを特徴とする半導体集積回路の製造方法。
2. A semiconductor comprising an inorganic protective film and an organic protective film formed so as to cover an electrode to be connected to an external electrode on a semiconductor integrated circuit substrate, and a through hole for leading out the electrode being formed in the inorganic protective film and the organic protective film. In the method of manufacturing an integrated circuit, a step of forming the inorganic protective film on the semiconductor integrated circuit substrate; a step of forming the organic protective film having positive photosensitivity on the inorganic protective film; A step of applying a positive photosensitive resin on the film; a step of forming the through hole having a predetermined shape in the organic protective film and the photosensitive resin on the electrode by exposure and development; and Etching the inorganic protective film on the electrode to expose the electrode.
【請求項3】請求項2に記載の半導体集積回路の製造法
において、前記現像においては、非溶剤系アルカリ水溶
液にて現像することを特徴とする半導体回路の製造方
法。
3. The method of manufacturing a semiconductor integrated circuit according to claim 2, wherein said developing is performed with a non-solvent-based alkaline aqueous solution.
JP27011599A 1999-09-24 1999-09-24 Semiconductor integrated circuit and manufacturing method therefor Pending JP2001094056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27011599A JP2001094056A (en) 1999-09-24 1999-09-24 Semiconductor integrated circuit and manufacturing method therefor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27011599A JP2001094056A (en) 1999-09-24 1999-09-24 Semiconductor integrated circuit and manufacturing method therefor

Publications (1)

Publication Number Publication Date
JP2001094056A true JP2001094056A (en) 2001-04-06

Family

ID=17481762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27011599A Pending JP2001094056A (en) 1999-09-24 1999-09-24 Semiconductor integrated circuit and manufacturing method therefor

Country Status (1)

Country Link
JP (1) JP2001094056A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026240B2 (en) 2003-08-07 2006-04-11 Samsung Electronics, Co., Ltd. Method of fabricating a semiconductor device having a photo-sensitive polyimide layer and a device fabricated in accordance with the method
CN104900685A (en) * 2014-03-07 2015-09-09 英飞凌科技股份有限公司 Semiconductor Device with a Passivation Layer and Method for Producing Thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7026240B2 (en) 2003-08-07 2006-04-11 Samsung Electronics, Co., Ltd. Method of fabricating a semiconductor device having a photo-sensitive polyimide layer and a device fabricated in accordance with the method
CN104900685A (en) * 2014-03-07 2015-09-09 英飞凌科技股份有限公司 Semiconductor Device with a Passivation Layer and Method for Producing Thereof
JP2015170857A (en) * 2014-03-07 2015-09-28 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag Semiconductor device with passivation layer and method for producing the same
JP2017224838A (en) * 2014-03-07 2017-12-21 インフィネオン テクノロジーズ アーゲーInfineon Technologies Ag Semiconductor element with passivation layer and method for producing the same
US11158557B2 (en) 2014-03-07 2021-10-26 Infineon Technologies Ag Semiconductor device with a passivation layer and method for producing thereof
US11854926B2 (en) 2014-03-07 2023-12-26 Infineon Technologies Ag Semiconductor device with a passivation layer and method for producing thereof

Similar Documents

Publication Publication Date Title
US5407788A (en) Photoresist stripping method
KR100271761B1 (en) Manufacturing method of semiconductor device
JP3871923B2 (en) Pattern forming method and manufacturing method of active matrix substrate using the same
JP2001094056A (en) Semiconductor integrated circuit and manufacturing method therefor
JP2001332545A (en) Semiconductor integrated circuit and manufacturing method therefor
JP4362275B2 (en) Thin film transistor manufacturing method
JPH06275511A (en) Forming method of polyimide pattern
US20090253082A1 (en) Method for forming resist pattern
KR20090055775A (en) Manufacturing method of semiconductor device
JPH03268427A (en) Formation of organic resin film pattern and manufacture of multilayered wiring board
KR100216732B1 (en) Etching method of aluminium thin film
JPS6386550A (en) Formation of multilayer interconnection layer
JP2000260765A (en) Pattern formation method of organic insulating film
JPH11307525A (en) Semiconductor device and its manufacture
JPH04196306A (en) Manufacture of polyimide resin film pattern
JPH05218008A (en) Manufacture of polyimide resin film pattern
JP2589471B2 (en) Method for manufacturing semiconductor device
JP3243904B2 (en) Method of forming resist pattern
KR100198599B1 (en) Alligning method for semiconductor device fabrication
KR100206896B1 (en) Method for forming contact of bypola device
JPH05190790A (en) Semiconductor device
JP2000277512A (en) Semiconductor device and manufacture thereof
JPH0845900A (en) Method for forming desired pattern of resin film on semiconductor substrate, semiconductor chip, semiconductor package and resist pattern stiripper
JPS63231338A (en) Fine pattern forming method
KR20010056120A (en) Method for forming contact hole using i-line resist having oxide characteristic