JP2001094042A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the surface of a semiconductor chip from being flawed. SOLUTION: This semiconductor device is of so-called 'chip-on-chip structue' and is constituted by stacking a subordinate chip 2 on the surface of a master chip 1 and jointing the chips together. A hollow part 5 is formed between the master chip 1 and the subordinate chip 2, and is filled with air.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-on-chip structure in which another semiconductor chip is superimposed on and bonded to the surface of a semiconductor chip, or a flip-chip structure in which the surface of a semiconductor chip is bonded to a wiring board. The present invention relates to a semiconductor device having a chip bonding structure.

[0002]

2. Description of the Related Art Conventionally, there has been known a semiconductor device having a chip-on-chip structure in which another semiconductor chip is superimposed on and joined to the surface of a semiconductor chip. In a semiconductor device having such a chip-on-chip structure, as shown in FIG. 2, one semiconductor chip 91 is joined to the other semiconductor chip 92 by a so-called face-down method. By a plurality of bumps 93 provided therebetween, they are connected so as to keep a predetermined interval, and
They are electrically connected to each other. The surface between the opposing semiconductor chips 91 and 92 is sealed with a resin 94. The semiconductor module obtained by sealing the space between the semiconductor chips 91 and 92 with the resin 94 is further sealed with a mold resin. In a package (not shown).

[0003]

However, in the resin 94 for sealing between the semiconductor chips 91 and 92, this resin 9
In order to match the coefficient of thermal expansion of No. 4 with the coefficient of thermal expansion of the semiconductor chips 91 and 92, a particulate matter (filler) 95 such as silica is mixed. Therefore, the semiconductor chip 9
The surface protection film formed on the outermost surface of
4 is damaged by the filler 95 in the semiconductor chip 9.
There was a possibility that the performances of 1,92 would be deteriorated.

An object of the present invention is to solve the above-mentioned technical problems and to provide a semiconductor device which can prevent the surface of a semiconductor chip from being damaged.

[0005]

Means for Solving the Problems and Effects of the Invention According to the first aspect of the present invention, an assembly obtained by bonding a semiconductor chip to a solid surface with the surface of the semiconductor chip facing the solid surface is mounted on a package. A semiconductor device configured to be accommodated, wherein a hollow portion surrounded by a material of the package is formed between the solid surface and the semiconductor chip.

[0006] The solid surface may be the surface of another semiconductor chip or the surface of a wiring board such as a lead frame. According to the present invention, the hollow portion is formed between the surface of the solid contained in the package and the surface of the semiconductor chip. Thereby, since the surface of the semiconductor chip faces the hollow portion, there is no possibility that the surface of the semiconductor chip is damaged. Therefore, there is no possibility that the performance of the semiconductor chip is deteriorated due to the surface being damaged.

[0007] The hollow portion may be filled with air or an inert gas, or may be evacuated. When the hollow portion is filled with an inert gas or when the hollow portion is evacuated, performance degradation of the semiconductor chip can be further prevented. The invention according to claim 2 is characterized in that a filler having a particle size larger than a distance between the solid surface and the surface of the semiconductor chip is mixed into the material of the package. Semiconductor device.

When a plurality of types of fillers are mixed in the package material, the particle size of the filler mixed in the package material is larger than the distance between the solid surface and the surface of the semiconductor chip. It is preferable that a filler having a large particle diameter smaller than the interval is not mixed in the material of the package. In the material of the package, a particulate filler is mainly mixed to match the coefficient of thermal expansion of the package with the coefficient of thermal expansion of the semiconductor chip. According to the present invention, the filler contained in the material of the package enters between the solid surface and the surface of the semiconductor chip because the particle size is larger than the distance between the solid surface and the surface of the semiconductor chip. Never. Therefore, there is no possibility that the surface of the semiconductor chip is damaged by the filler in the package material, and the performance deterioration of the semiconductor chip can be further prevented.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. This semiconductor device is a semiconductor device having a so-called chip-on-chip structure, and is configured by superposing and joining a child chip 2 on a surface 11 of a parent chip 1.

The parent chip 1 is made of, for example, a silicon chip. The surface 11 of the parent chip 1 is a surface on the active surface layer region side on which a functional element such as a transistor is formed on a semiconductor substrate, and the outermost surface is covered with a surface protective film made of, for example, silicon nitride. Child chip 2
Is made of, for example, a silicon chip. The surface 21 of the slave chip 2 is a surface on the active surface layer region side where a functional element such as a transistor is formed on the semiconductor substrate,
The outermost surface is covered with a surface protective film made of, for example, silicon nitride. The child chip 2 is bonded to the parent chip 1 by a so-called face-down method in which the surface 21 faces the surface 11 of the parent chip 1, and a plurality of bumps B provided between the child chip 2 and the parent chip 1 The main chip 1 is supported while maintaining a predetermined distance D between the main chip 1 and the front surface 11, and electrical connection with the main chip 1 is achieved.

The semiconductor module formed by bonding the parent chip 1 and the child chip 2 is bonded to a lead frame 3 and then set in a mold cavity (not shown) and subjected to a resin sealing step. Is sealed in the package 4. In the resin sealing step, the semiconductor module bonded to the lead frame 3 is set, for example, in a cavity of a mold provided in an air atmosphere. Thereafter, the resin material forming the package 4 is injected into the cavity. This resin material is obtained by mixing a filler 41 for matching the coefficient of thermal expansion with that of the parent chip 1 and the child chip 2 in a synthetic resin such as an epoxy resin. This filler 41 is
For example, it is a silica particle, and the particle diameter R is formed larger than the distance D formed between the parent chip 1 and the child chip 2. When a plurality of types of fillers are mixed in the resin material, the particle diameters of all the fillers are formed to be larger than the interval D.

The resin material injected into the cavity covers the periphery of the semiconductor module.
And the child chip 2. However, since this resin sealing step is performed in an air atmosphere, the resin material enters between the parent chip 1 and the child chip 2 due to the air existing between the parent chip 1 and the child chip 2. Blocked by As a result, air remains between the parent chip 1 and the child chip 2, and the resin material is cured in this state to form the package 4, so that a hollow portion is formed between the parent chip 1 and the child chip 2. 5 is completed.

As described above, according to this embodiment, the hollow portion 5 is formed between the parent chip 1 and the child chip 2 housed in the package 4, and the hollow part 5 is formed between the parent chip 1 and the child chip 2. The surface faces the hollow part 5. In other words,
Unlike the conventional configuration, the space between the parent chip 1 and the child chip 2 is not sealed with resin. Therefore, the surface protective films formed on the surfaces of the parent chip 1 and the child chip 2
There is no danger of being damaged by the filler contained in the resin. Therefore, there is no possibility that the performance of the parent chip 1 and the child chip 2 is deteriorated due to the damage of the surface protective film.

The filler 41 contained in the resin material constituting the package 4 has a particle diameter R larger than the distance D formed between the parent chip 1 and the child chip 2.
There is no entry between the parent chip 1 and the child chip 2.
Therefore, there is no possibility that the surface protection films formed on the surfaces of the parent chip 1 and the child chip 2 are damaged by the filler 41. Although one embodiment of the present invention has been described, the present invention can be embodied in other forms. For example, in the above embodiment, the step of forming the package 4 and sealing the parent chip 1 and the child chip 2 with resin is performed in an air atmosphere. However, this resin sealing step may be performed in a vacuum. Good. In this case, since the inside of the hollow portion 5 between the parent chip 1 and the child chip 2 is evacuated, the parent chip 1
And the child chip 2 can be improved in adhesion. Also,
The resin sealing step may be performed in an inert gas atmosphere such as nitrogen gas. In this case, since the inside of the hollow portion 5 between the parent chip 1 and the child chip 2 is filled with the inert gas, the performance degradation of the parent chip 1 and the child chip 2 can be further prevented.

Although the parent chip 1 and the child chip 2 are both chips made of silicon, in addition to silicon, other arbitrary chips such as a compound semiconductor (for example, a gallium arsenide semiconductor) or a germanium semiconductor may be used. A semiconductor chip using a semiconductor material may be used. In this case, the semiconductor material of the parent chip 1 and the semiconductor material of the child chip 2 may be the same or different. In the above-described embodiment, the chip-on-chip structure has been described. However, the present invention can be applied to a flip-chip bonding structure in which the surface of a semiconductor chip is bonded to a wiring board such as a lead frame so as to be opposed. .

In addition, various design changes can be made within the scope of the matters described in the claims.

[Brief description of the drawings]

FIG. 1 is an illustrative sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an illustrative sectional view for describing a problem of a semiconductor device in which a space between a parent chip and a child chip is sealed with a resin;

[Explanation of symbols]

Reference Signs List 1 parent chip (solid) 11 surface (solid surface) 2 child chip (semiconductor chip) 21 surface (surface of semiconductor chip) 4 package 41 filler (filler included in package material) 5 hollow space D interval (solid surface and semiconductor) (Space between chip surface) R Particle size (particle size of filler)

Claims (2)

[Claims] 1. A semiconductor device comprising an assembly obtained by joining a semiconductor chip to a solid surface with a surface of the semiconductor chip facing the solid surface, wherein the assembly is housed in a package. A semiconductor device, wherein a hollow portion surrounded by the material of the package is formed. 2. The semiconductor device according to claim 1, wherein a filler having a particle size larger than a distance between the solid surface and the surface of the semiconductor chip is mixed in the material of the package. .