JP2001086108A - Synchronization detection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a synchronization detection system that can reduce more a time until a phase relation between data and a frame pulse is not warranted in the case that a phase of a synchronization pattern received by a synchronization detection circuit is fluctuated. SOLUTION: This synchronization detection system is provided with synchronization detection circuits 1, 2 in parallel with respect to input data. When the synchronization detecting circuit 1 in the synchronization establishing state enters a forward protection operation due to a synchronization bit offset, the detection circuit 1 allows the synchronization detection circuit 2 to immediately start a backward protection operation from a hunting state. Thus, the one detection circuit can start the backward protection operation as soon as the other detection circuit conducts the forward protection operation and then the time for re-synchronization establishment can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection system, and more particularly to a synchronization detection system for detecting a frame synchronization pattern of an input signal.

[0002]

2. Description of the Related Art A conventional synchronous detection method will be described. The input data has a certain length for one cycle (1
A frame synchronization pattern (hereinafter, simply referred to as a synchronization pattern), which is a combination of fixed patterns, one set for each frame, is inserted. A synchronization detection circuit is provided to detect the synchronization pattern, and the synchronization detection circuit searches for a synchronization pattern from an input data sequence (referred to as a hunting operation).

[0003] When a synchronization pattern is detected once, the synchronization detection circuit determines that the first bit of the pattern is the head of the frame, and from the next, it is input one frame after the detected first bit. It is determined whether the data matches the synchronization pattern (referred to as a backward protection operation). If they do not match at this time, the hunting operation starts again. Here, if the patterns match,
The number of times specified as the number of backward protection stages is confirmed to match the synchronization pattern input for each frame, and a synchronization is established, and a frame pulse indicating the beginning of the frame is output at the timing of the synchronization pattern. I have.

Next, the synchronization detection circuit confirms that the synchronization pattern of each frame matches when the synchronization is established.
When a pattern that matches the expected position of the synchronization pattern in a certain frame is not detected, a mismatch is confirmed a number of times defined as the number of forward protection steps (referred to as forward protection operation). It issues a disconnection alarm and starts the hunting operation again.

Here, with reference to Japanese Patent Application Laid-Open No. Hei 5-37519, a technique is provided in which two synchronization detection circuits are provided, and when one of them is out of synchronization, the other immediately starts the backward protection operation. Has been proposed.

[0006]

The above-mentioned problem of the prior art is that the input data has a bit shift due to a malfunction of a circuit connected to the preceding stage of the synchronization detection circuit. The synchronization detection circuit detects a synchronization pattern that is a few bits away from the place where it was, after a bit shift from the synchronization establishment state before the bit shift occurs, until the synchronization is established again, It is necessary to have the number of frames (= time) equal to (the number of front protection steps + the number of rear protection steps). This means that when data has a bit shift, the phase relationship between the data and the frame pulse is not guaranteed until a new synchronization pattern is detected and the synchronization is established again. (The number of protection stages).

[0007] The reason is that in the conventional synchronization detection circuit, when the position of the input synchronization pattern fluctuates due to bit shift or the like in the synchronization established state, the new synchronization pattern cannot be immediately detected, and the forward synchronization detection circuit cannot detect the new synchronization pattern. This is because, after the protection operation, the hunting operation is started only when the synchronization is lost.

In the technique disclosed in Japanese Patent Application Laid-Open No. Hei 5-37519, when one is in the forward protection state, the other starts the hunting operation. Since the backward protection operation can be started, the time required for the hunting operation can be reduced as compared with the above-described conventional technology, but the other is that the hunting operation is completed and a new synchronization pattern can be detected. However, until one of them is out of synchronization, the time for (backward protection stage number + rearward protection stage number) is still required in order not to enter the rearward protection operation.

An object of the present invention is to set a time period during which the phase relationship between data and a frame synchronization pulse is not guaranteed when the position of a synchronization pattern input to the synchronization detection circuit changes.
An object of the present invention is to provide a synchronization detection method that can be shortened.

[0010]

According to the present invention, there is provided a synchronization detection system for detecting a synchronization pattern of an input signal, wherein two synchronization detection circuits for detecting the synchronization pattern are provided with respect to the input signal. A synchronous detection system is provided in which one of the synchronous detection circuits is provided in parallel so that when one of the synchronous detection circuits enters the forward protection operation, the other synchronization detection circuit immediately starts the backward protection operation.

When the one synchronization detection circuit is in a synchronization established state, the other synchronization detection circuit is in a hunting state, and the one synchronization detection circuit is in a forward protection operation. When a state change signal is supplied to the other synchronization detection circuit, in response to the state change signal, the other synchronization detection circuit starts the rearward protection operation immediately from the hunting state. I do.

Each of the two synchronization detection circuits generates the state change signal when the forward protection operation is performed, sends the state change signal to the other synchronization detection circuit, and responds to the reception of the state change signal. The rear protection operation is started.

According to the present invention, there is provided a synchronization detection method for detecting a frame synchronization pattern of an input signal, wherein the frame synchronization pattern is detected and a frame pulse is outputted, respectively, and when the synchronization is lost. Two synchronization detection circuits for respectively outputting out-of-synchronization alarm signals,
A selector for selectively deriving one of the two frame pulses in accordance with the state of the two out-of-sync alarm signals, and when one of the synchronization detection circuits is in the forward protection operation,
A synchronization detection method is obtained in which the other synchronization detection circuit immediately starts the backward protection operation.

[0014] The selector is characterized in that when one of the two out-of-sync alarm signals is generated, the selector selectively derives a frame pulse of the other sync detection circuit.

The operation of the present invention will be described. 2 synchronization detection circuits
In combination, when one enters the forward protection operation from the state of synchronization establishment, the other operates immediately to start the backward protection operation, thereby reducing the number of frames required until synchronization is re-established. The time during which the phase relationship between the result data and the frame pulse is not guaranteed can be shortened.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings. Referring to FIG.
The embodiment of the present invention includes a synchronization detection circuit 1, a synchronization detection circuit 2, and a selector 3, and the synchronization detection circuits 1 and 2 can have exactly the same conventional circuit configuration.

The synchronization detecting circuits 1 and 2 receive the input data as shown in FIG. 2 and detect a synchronization pattern from the data sequence. When the synchronization is established, the frame pulses 11 and 21 are generated. In addition, it has a function of outputting out-of-synchronization alarms 12 and 22 when an out-of-synchronization state occurs. The out-of-synchronization alarms 12 and 22 indicate "L (low level)" when the synchronization detection circuit is in the synchronization established state, and indicate "H (high level)" in the out-of-synchronization state.

Further, the synchronization detecting circuits 1 and 2 have a function of outputting the state change triggers 13 and 23 and supplying the same to the other, respectively. "L" in the state, forward protection /
“H” is indicated during any of the rear protection / hunting operations.

The operation of the synchronization detection circuit in response to the state change trigger will be described. Each of the synchronization detection circuits outputs this signal to the other party.
When the state change trigger from the other party is "L" and the terminal is out of synchronization, the hunting state is maintained without moving to the backward protection operation even if a synchronization pattern is detected from the input signal (the standby state is maintained). And). Next, when the state trigger becomes “H”, the backward protection operation is started from the standby state, and the normal synchronization establishing operation is performed.

The selector 3 uses the out-of-synchronization alarms 12 and 22 from the synchronization detection circuits 1 and 2 as input selection signals S1 and S2. One and one of the out-of-synchronization alarms 12 and 22 are selected, and are derived as an output frame pulse 4 and an out-of-synchronization alarm 5. The input selection signals S1,
The operation for S2 is as shown in the table of FIG.

Here, the synchronization pattern is "011".
In the following description, it is assumed that the number of stages of the forward protection and the rear protection is both “3.” The frame pulses 11 and 21 output from the synchronization detection circuits 1 and 2 and the loss of synchronization alarms 12 and 22 are input. The relationship with the data synchronization pattern is as shown in FIG.

Now, the operation will be described with reference to the timing chart of FIG. 4 assuming that the synchronization detection circuit 1 is in a synchronization established state. Forward protection counters 14 and 2 in FIG.
Numeral 4 denotes a counter for counting the number of forward protection stages in the synchronization detection circuits 1 and 2 during the forward protection operation, and rear protection counters 15 and 25 count the number of front protection stages in the synchronization detection circuits 1 and 2 during the forward protection operation. Although these counters are not particularly shown in FIG. 1, they are well known.

When the synchronization detection circuit 1 is in the synchronization established state, the state change trigger 13 indicates "L", so that the synchronization detection circuit 2
Is in a standby state and constantly hunting. Considering the case where the data of the input pattern shown in FIG. 2 is input to the synchronization detection circuits 1 and 2, the synchronization pattern is shifted by one bit in the fourth frame shown in FIG. 2 (either forward or backward). Occurs, the synchronization detection circuit 1 starts the forward protection operation. Therefore, at this time, the state change trigger 13 becomes “H”.

As a result, the synchronization detection circuit 2 becomes ready for normal operation from the standby state.
A synchronization pattern at a bit shifted position is detected, and the rear protection operation is started. The synchronization detection circuit 1 continues the forward protection operation, changes to an out-of-sync state at the seventh frame, and issues an out-of-sync alarm 12. Since the selector is currently selecting the A side (the input side from the synchronization detection circuit 1), the output loss of synchronization alarm 5
As a result, the out-of-synchronization alarm 12 is output.

On the other hand, in the eighth frame, the synchronization detecting circuit 2 changes from the backward protection operation to a synchronization established state with a synchronization pattern at a new position shifted by one bit, and the synchronization loss alarm 22
Is released to “L”. At this time, the selector is switched from the A side selection to the B side selection, the released out-of-sync alarm 22 is output as the output out-of-sync alarm 5, and the output frame pulse 4 is newly output by the synchronization detection circuit 2. The frame pulse 21 at the detected timing is output.

Here, a description will be given, with reference to FIG. 5, that the time required for reestablishing frame synchronization according to the above-described embodiment of the present invention is reduced as compared with the conventional example. FIG. 5 is a timing chart showing the operation when a pattern similar to the above is input in a conventional circuit. In this case, the number of frames from which the phase relationship between the data and the frame pulse cannot be guaranteed from the fourth frame until the input pattern causes a bit shift and re-establishes synchronization is:
Six frames from the fourth frame to the ninth frame (three frames indicated by dotted lines in the frame pulse in FIG. 5 and three frames in which no out-of-synchronization alarm is issued and no pulse is output) are required.

On the other hand, when the synchronization detection circuit of the present invention is used, the number of frames for which the phase relationship between the data and the frame pulse cannot be guaranteed until the input signal causes a bit shift and synchronization is established again is reduced. From the fourth frame to the seventh frame (shown in the output frame pulse 4 in FIG. 4)
This can be realized in four frames of three frames in which the pulse is indicated by the dotted line and one frame in which no out-of-synchronization alarm is issued and no pulse is output (one frame).

The reason is as follows. By using two synchronization detection circuits so that when one of them is in the state of synchronization establishment, the other always keeps hunting operation, the position of the synchronization pattern from a certain frame can be changed. In the case of deviation, the forward protection operation of the circuit that was in the synchronization established state until immediately before, and the rear protection operation at the new synchronization pattern position of the other circuit can be performed simultaneously,
Therefore, the number of frames until re-synchronization is established can be shortened.

In the configuration of FIG. 1, for example, a state change trigger 13 is issued from the synchronization detection circuit 1 to the synchronization detection circuit 2, and the synchronization detection circuit 2 immediately enters the hunting operation and the backward protection operation from the out-of-synchronization state. For example, the synchronization detection circuit 2 can be controlled by the state change trigger 13.
This can be achieved by controlling the mask so that the rear protection counter does not operate. That is, when the synchronization detection circuit 1 is in the synchronization state, the state change trigger 13 is "L".
Therefore, by masking the input so that the rear protection counter 25 of the synchronization detection circuit 2 does not count up due to the “L” of the state change trigger 13, the synchronization detection circuit 2 enters the rear protection operation. Absent. When the state change trigger 13 from the synchronization detection circuit 1 changes to "H", the masking of the rear protection counter 25 of the synchronization detection circuit 2 is released, and the counting operation for the rear protection operation can be performed immediately from the hunting state. Thus, the above operation can be performed.

State change trigger 23 from synchronization detection circuit 2
It is obvious that the same applies to the rear protection counter of the synchronization detection circuit 1.

[0031]

As described above, according to the present invention, the input synchronization pattern is shifted, the synchronization detection circuit during synchronization enters the forward protection operation, and the other synchronization detection circuit is immediately hunted. And the backward protection operation, the forward protection operation of the synchronization detection circuit during the establishment of synchronization and the backward protection operation at the new synchronization pattern position of the other circuit can be performed simultaneously. There is an effect that resynchronization can be established in a shorter time than in the technique of Japanese Patent Application Laid-Open No. 5-37519, which always requires a time of (the number of front protection stages + the number of rear protection stages).

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing chart showing a general operation of a synchronization detection circuit in the system of FIG. 1;

FIG. 3 is a diagram showing an operation of a selector in the system of FIG. 1;

FIG. 4 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 5 is a timing chart showing the operation of the related art.

[Explanation of symbols]

 1, 2 synchronization detection circuit 3 selector 4 output frame pulse 5 output loss of synchronization alarm 11, 21 frame pulse 12, 22 loss of synchronization alarm 13, 23 state change trigger

Claims (6)

[Claims] 1. A synchronization detection method for detecting a synchronization pattern of an input signal, wherein two synchronization detection circuits for detecting the synchronization pattern are provided in parallel with the input signal, and one of the synchronization detection circuits is provided. Is in the forward protection action,
A synchronization detection method wherein the other synchronization detection circuit immediately starts the backward protection operation. 2. The synchronization detection system according to claim 1, wherein said one synchronization detection circuit is in a hunting state when said one synchronization detection circuit is in a synchronization established state. 3. The one synchronization detection circuit supplies a state change signal to the other synchronization detection circuit when a forward protection operation is performed, and the other synchronization detection circuit responds to the state change signal. 3. The synchronization detecting method according to claim 2, wherein the backward protection operation is started immediately from a hunting state. 4. Each of the two synchronization detection circuits generates the state change signal when the forward protection operation is performed, sends the state change signal to the other synchronization detection circuit, and responds to the reception of the state change signal. 4. The synchronization detection method according to claim 3, wherein the rearward protection operation is started by the control unit. 5. A synchronization detection method for detecting a frame synchronization pattern of an input signal, wherein the frame synchronization pattern is detected and a frame pulse is output, respectively. Two synchronous detection circuits each outputting a signal, and a selector for selectively deriving one of the two frame pulses in accordance with the state of the two out-of-sync alarm signals, and one of the synchronous detection circuits performs a forward protection operation. A synchronous detection method wherein the other synchronous detection circuit immediately starts a backward protection operation when the synchronous detection circuit becomes inactive. 6. The synchronization according to claim 5, wherein the selector selects and derives a frame pulse of the other synchronization detection circuit when one of the two out-of-synchronization alarm signals is generated. Detection method.