JP2001085471A - Method of mounting electronic component - Google Patents
Method of mounting electronic componentInfo
- Publication number
- JP2001085471A JP2001085471A JP26433399A JP26433399A JP2001085471A JP 2001085471 A JP2001085471 A JP 2001085471A JP 26433399 A JP26433399 A JP 26433399A JP 26433399 A JP26433399 A JP 26433399A JP 2001085471 A JP2001085471 A JP 2001085471A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- resin film
- electronic component
- protruding electrode
- flip chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/13144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/8102—Applying permanent coating to the bump connector in the bonding apparatus, e.g. in-situ coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8136—Bonding interfaces of the semiconductor or solid state body
- H01L2224/81375—Bonding interfaces of the semiconductor or solid state body having an external coating, e.g. protective bond-through coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えばフリップチ
ップ実装等のように、ワイヤボンディング法により形成
された突起状電極を有する電子部品を基板上に実装する
にあたって、該突起状電極と基板のランドとを半田接合
する電子部品の実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting an electronic component having a protruding electrode formed by a wire bonding method on a substrate, such as flip-chip mounting, for example. And a method for mounting an electronic component by soldering.
【０００２】[0002]
【従来の技術】近年、携帯用機器（携帯電話等）の小型
化、高密度実装化が求められている。中でも、フリップ
チップ実装は、チップサイズとほぼ同じ面積の基板上に
実装でき、基板自体を小さくできるため、盛んに検討が
行われている。従来のフリップチップの概略断面を図３
（ａ）に示す。図３（ａ）においては、チップＪ１上に
公知のウェハプロセス技術（蒸着やスパッタ等）を用い
てＡｌ（アルミニウム）配線（配線部）Ｊ２及び保護膜
Ｊ３が形成されている。2. Description of the Related Art In recent years, there has been a demand for miniaturization and high-density mounting of portable equipment (mobile phones and the like). Above all, flip-chip mounting is being actively studied because it can be mounted on a substrate having almost the same area as the chip size and the substrate itself can be made smaller. FIG. 3 shows a schematic cross section of a conventional flip chip.
(A). In FIG. 3A, an Al (aluminum) wiring (wiring portion) J2 and a protective film J3 are formed on the chip J1 by using a known wafer process technique (such as vapor deposition or sputtering).
【０００３】そして、Ａｌ配線Ｊ２のうち保護膜Ｊ３の
開口部から露出したパッド部上には、Ａｕワイヤ等をワ
イヤボンディング法によりボールボンディングすること
により、突起状電極としてのスタッドバンプＪ４が形成
されている。なお、このようなフリップチップを以下、
スタッドバンプ方式のフリップチップという。このスタ
ッドバンプ方式のフリップチップは、上記ウェハプロセ
スによって突起状電極（バンプ）を形成する場合に比べ
て安価に突起状電極を形成することが可能なため、広く
開発が進められている。A stud bump J4 as a protruding electrode is formed on the pad portion of the Al wiring J2 exposed from the opening of the protective film J3 by ball bonding of an Au wire or the like by a wire bonding method. ing. In addition, such a flip chip is hereinafter referred to as
It is called a stud bump type flip chip. This stud bump type flip chip has been widely developed because a protruding electrode (bump) can be formed at a lower cost than in the case where a protruding electrode (bump) is formed by the above wafer process.
【０００４】[0004]
【発明が解決しようとする課題】ところで、図３（ｂ）
に示すようなウェハプロセスによって保護膜Ｊ３及びＡ
ｌ配線Ｊ２上に形成される電極（バンプ）Ｊ５と異な
り、上記図３（ａ）に示した構造においては、スタッド
バンプＪ４は、保護膜Ｊ３によって開口したＡｌ配線Ｊ
２のパッド部上に形成されており、バンプＪ４とＡｌ配
線Ｊ２との接合面が露出している（図３（ａ）中の露出
部Ｊ６）。FIG. 3 (b)
The protective films J3 and A are formed by the wafer process shown in FIG.
Unlike the electrode (bump) J5 formed on the l wiring J2, in the structure shown in FIG. 3A, the stud bump J4 is formed by the Al wiring J opened by the protective film J3.
2 is formed on the pad portion, and the bonding surface between the bump J4 and the Al wiring J2 is exposed (exposed portion J6 in FIG. 3A).
【０００５】このように該接合面が露出しているのは、
保護膜とワイヤボンディング法により形成された突起状
電極との接合性が悪いことから、バンプＪ４をＡｌ配線
Ｊ２のパッド部上にのみ形成するようにしているためで
ある。つまり、そのバンプ形成におけるワイヤボンディ
ングする際の寸法精度等の面から、必然的に露出部Ｊ６
が存在するのである。The reason why the bonding surface is exposed is as follows.
This is because the bump J4 is formed only on the pad portion of the Al wiring J2 because the bonding property between the protective film and the protruding electrode formed by the wire bonding method is poor. That is, in view of the dimensional accuracy and the like at the time of wire bonding in the bump formation, the exposed portion J6 is inevitably required.
Exists.
【０００６】また、上記スタッドバンプ方式のフリップ
チップは、図３（ｃ）に示す様に、所定部位に低融点金
属の半田Ｊ７が配設された基板Ｊ８上に対して、スタッ
ドバンプＪ４と半田Ｊ７とを接触させるように位置決め
された後、半田Ｊ７を溶融させることにより、フリップ
チップと基板Ｊ８とが、バンプＪ４及び半田Ｊ７を介し
て電気的に接続される。Further, as shown in FIG. 3 (c), the stud bump type flip chip is mounted on a substrate J8 having a low melting point metal solder J7 disposed at a predetermined position. After being positioned so as to make contact with J7, by melting solder J7, the flip chip and substrate J8 are electrically connected via bump J4 and solder J7.
【０００７】しかしながら、上記のように、スタッドバ
ンプ方式のフリップチップは、バンプＪ４とＡｌ配線Ｊ
２との接合面が露出しているため、この実装工程におい
て、半田Ｊ７でバンプＪ４と基板Ｊ８とを接続した場
合、バンプＪ４とＡｌ配線Ｊ２との界面に、半田Ｊ７が
付着することがある。このように、当該界面に半田Ｊ７
が付着した場合は、図３（ｃ）中の白抜き矢印に示す様
に、この界面に沿って半田Ｊ７中の成分（例えばスズ
等）が拡散し易く、その影響によって該界面にクラック
が発生する等、バンプＪ４とＡｌ配線Ｊ２との接続信頼
性が著しく低下するという問題があった。However, as described above, the flip chip of the stud bump type uses the bump J4 and the Al wiring J
In this mounting step, when the bump J4 is connected to the substrate J8 with the solder J7 in the mounting process, the solder J7 may adhere to the interface between the bump J4 and the Al wiring J2. . Thus, the solder J7
3B, the components (for example, tin) in the solder J7 easily diffuse along the interface, as indicated by a white arrow in FIG. 3C, and a crack is generated at the interface due to the influence. For example, there is a problem that the connection reliability between the bump J4 and the Al wiring J2 is significantly reduced.
【０００８】ここで、特開平３−５０９７３６号公報で
は、接続信頼性向上のためにＡｌ配線上に上記のような
拡散を防止するためのＴｉ−Ｐｔ−Ａｕ等のバリアメタ
ルを形成した上に、ワイヤボンディング法にて突起状電
極（金属ボール）を形成する方法が紹介されている。し
かし、このバリアメタル形成は、前述のウェハプロセス
で作られる電極Ｊ５と同様にコストが高くなるため、ワ
イヤボンディング法で突起状電極を形成することにある
コストダウン効果を相殺してしまうという問題が生じ
る。In Japanese Patent Application Laid-Open No. 3-509736, a barrier metal such as Ti-Pt-Au for preventing the above-described diffusion is formed on an Al wiring in order to improve connection reliability. A method for forming a protruding electrode (metal ball) by a wire bonding method is introduced. However, since the formation of the barrier metal is expensive as in the case of the electrode J5 formed by the above-described wafer process, there is a problem that the cost reduction effect of forming the protruding electrodes by the wire bonding method is offset. Occurs.
【０００９】そこで、本発明は上記問題に鑑み、配線部
上にワイヤボンディング法により突起状電極を形成して
なる電子部品を、該突起状電極を介して半田接合するこ
とで基板上に実装する電子部品の実装方法において、コ
ストアップを極力抑えつつ、突起状電極と配線部との界
面に半田が付着するの防止することを目的とする。In view of the above problem, the present invention mounts an electronic component having a protruding electrode formed on a wiring portion by a wire bonding method on a substrate by soldering via the protruding electrode. In a method for mounting an electronic component, an object is to prevent solder from adhering to an interface between a protruding electrode and a wiring portion while minimizing cost increase.
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、請求項１記載の発明では、一面側に配線部（２）及
び該配線部上にワイヤボンディング法により形成された
突起状電極（４）を有する電子部品（１０）と、一面側
にランド（６）及びこのランド上に配設された半田
（７）を有する基板（８）とを用意し、該電子部品にお
いて少なくとも該配線部及び該突起状電極の表面上を液
状もしくは半硬化状態の樹脂膜（５）にて被覆した状態
のまま、該電子部品の一面と該基板の一面とを対向さ
せ、該突起状電極の先端部を該半田に押しつけることに
より該樹脂膜を排除して該突起状電極の先端部と該半田
とを接触させる工程と、しかる後、該樹脂膜を硬化させ
るとともに、該半田を溶融させて該突起状電極を該ラン
ドに電気的に接続する工程と、を備えることを特徴とし
ている。In order to achieve the above object, according to the first aspect of the present invention, a wiring portion (2) is formed on one surface and a protruding electrode (4) formed on the wiring portion by a wire bonding method. ) And a substrate (8) having a land (6) on one side and a solder (7) disposed on the land, and at least the wiring portion and With the surface of the protruding electrode covered with a liquid or semi-cured resin film (5), one surface of the electronic component and one surface of the substrate are opposed to each other. A step of removing the resin film by pressing against the solder to bring the tip of the protruding electrode into contact with the solder; and thereafter, curing the resin film and melting the solder to form the protruding portion. Electrically connecting electrodes to the lands It is characterized in that it comprises.
【００１１】本実装方法によれば、樹脂膜を液状もしく
は半硬化状態とし、この状態で突起状電極を半田に押し
つけるから、突起状電極の先端部と半田との間の樹脂膜
を容易に排除できる。そのため、当該間に樹脂が残ら
ず、突起状電極の接続性は確保できる。また、半田を溶
融させる際、突起状電極と配線部との界面は、硬化した
状態もしくは硬化しつつある状態の樹脂により半田から
ブロックされているから、当該界面に半田が付着するこ
とはない。According to this mounting method, since the resin film is in a liquid or semi-cured state and the protruding electrodes are pressed against the solder in this state, the resin film between the tip of the protruding electrodes and the solder is easily removed. it can. Therefore, the resin does not remain between them, and the connectivity of the protruding electrodes can be secured. Further, when the solder is melted, the interface between the protruding electrode and the wiring portion is blocked from the solder by the resin in a hardened or hardening state, so that the solder does not adhere to the interface.
【００１２】また、本実装方法において、樹脂膜によっ
て被覆する工程は、樹脂の転写や塗布等にて実行でき、
従来のウェハプロセスにおける蒸着やスパッタといった
工程に比べて安価であり、これらウェハプロセス工程を
用いて突起状電極を形成する場合や、上記のバリアメタ
ル形成の場合に比べて、コストアップが小さい。よっ
て、本発明によれば、コストアップを極力抑えつつ、突
起状電極と配線部との界面に半田が付着するの防止する
ことができる。In this mounting method, the step of coating with a resin film can be performed by transferring or applying a resin.
It is inexpensive as compared with processes such as vapor deposition and sputtering in a conventional wafer process, and the cost increase is smaller than when projecting electrodes are formed using these wafer process processes or when the above-described barrier metal is formed. Therefore, according to the present invention, it is possible to prevent solder from adhering to the interface between the protruding electrode and the wiring portion while minimizing cost increase.
【００１３】また、請求項２記載の発明のように、樹脂
膜（５）として、その硬化温度が半田（７）の溶融温度
よりも低いものを用いることが好ましい。これは、樹脂
膜を熱硬化させ且つ半田を溶融させる工程において、半
田を溶融させる際、突起状電極と配線部との界面を、十
分に硬化した状態の樹脂により半田からブロックでき、
当該界面への半田の付着をより確実に防止できるためで
ある。Further, as in the second aspect of the present invention, it is preferable to use a resin film (5) whose curing temperature is lower than the melting temperature of the solder (7). This is because, in the step of thermally curing the resin film and melting the solder, when melting the solder, the interface between the protruding electrode and the wiring portion can be blocked from the solder by the resin in a sufficiently cured state,
This is because the adhesion of the solder to the interface can be more reliably prevented.
【００１４】なお、上記各手段の括弧内の符号は、後述
する実施形態に記載の具体的手段との対応関係を示す一
例である。The reference numerals in parentheses of the above means are examples showing the correspondence with specific means described in the embodiments described later.
【００１５】[0015]
【発明の実施の形態】以下、本発明を図に示す実施形態
について説明する。本実施形態はフリップチップ実装に
本発明を適用したものとして説明する。図１は、本実施
形態に係る実装方法を示す工程図であって、実装される
基板の法線方向に沿った概略断面図である。以下を図１
に従って工程順に説明していく。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention. This embodiment will be described on the assumption that the present invention is applied to flip chip mounting. FIG. 1 is a process diagram illustrating a mounting method according to the present embodiment, and is a schematic cross-sectional view along a normal direction of a board to be mounted. Figure 1 below
Will be described in the order of the steps.
【００１６】まず、図１（ａ）に示す様に、スタッドバ
ンプ方式のフリップチップ（本発明でいう電子部品）１
０を用意する。このフリップチップは、Ｓｉ（シリコ
ン）チップ１の一面上に、公知のウェハプロセス技術を
用いて、Ａｌ等よりなる配線パッド（本発明でいう配線
部、本例ではＡｌ）２及びＳｉ窒化膜やポリイミド等よ
りなる保護膜３が形成されている。配線パッド２は保護
膜３の開口部から露出している。First, as shown in FIG. 1A, a stud bump type flip chip (electronic component according to the present invention) 1
Prepare 0. This flip chip is formed on one surface of a Si (silicon) chip 1 by using a known wafer process technique by using a wiring pad (a wiring portion in the present invention, Al in this example) 2 made of Al or the like and a Si nitride film or the like. A protective film 3 made of polyimide or the like is formed. The wiring pad 2 is exposed from the opening of the protective film 3.
【００１７】そして、この配線パッド２上に、ワイヤボ
ンディング法により突起状電極４が形成されている。こ
の突起状電極４は、ワイヤボンディングにおける金属ボ
ールをバンプとして形成したもので、ワイヤボンド実装
と同様な工程で作られる。本例では、ボンディングツー
ルによってＡｕワイヤから作られたＡｕボールを配線パ
ッド２の表面に接続し、その後、ワイヤ部分を切り離す
ことで突起状電極４は作製されている。この突起状電極
４はワイヤボンドにおける超音波振動で、パッド２と超
音波溶接された形となっている。The protruding electrodes 4 are formed on the wiring pads 2 by a wire bonding method. The protruding electrode 4 is formed by forming a metal ball as a bump in wire bonding as a bump, and is formed in the same process as wire bonding mounting. In this example, the bump-shaped electrode 4 is manufactured by connecting an Au ball made of an Au wire to the surface of the wiring pad 2 by a bonding tool and then cutting off the wire portion. The protruding electrode 4 is ultrasonically welded to the pad 2 by ultrasonic vibration in a wire bond.
【００１８】次に、図１（ｂ）に示す工程では、このフ
リップチップ１０を半田によって接続する前に、少なく
とも配線パッド２及び突起状電極３の表面上を液状もし
くは半硬化状態の樹脂膜５にて被覆する（第１の工
程）。本例では、配線パッド２及び突起状電極３の表面
と保護膜３の表面とを含めて、チップ１０の一面の略全
域を樹脂膜５にて被覆する。Next, in the step shown in FIG. 1B, before connecting the flip chip 10 by soldering, at least the surfaces of the wiring pads 2 and the protruding electrodes 3 are covered with a liquid or semi-cured resin film 5. (First step). In this example, the resin film 5 covers substantially the entire surface of the chip 10 including the surfaces of the wiring pads 2 and the protruding electrodes 3 and the surface of the protective film 3.
【００１９】具体的には、液状の熱硬化性樹脂（または
有機溶媒等で溶液化させた熱硬化性樹脂）を適当な容器
等に入れ、フリップチップ１０の一面をこの液状樹脂に
押しつける（つまりスタンプする）ことで、チップ１０
の一面に液状樹脂が転写される。この時点では液状の樹
脂膜５が形成される。さらに、液状の樹脂膜５が転写さ
れたチップ１０を、加熱または乾燥して樹脂を半硬化さ
せれば、半硬化状態の樹脂膜５が形成される。こうし
て、配線パッド２と突起状電極４との界面が樹脂膜５に
よって被覆保護される。Specifically, a liquid thermosetting resin (or a thermosetting resin solutionized with an organic solvent or the like) is placed in an appropriate container or the like, and one surface of the flip chip 10 is pressed against the liquid resin (that is, Stamping), the chip 10
The liquid resin is transferred to one surface of the substrate. At this point, a liquid resin film 5 is formed. Further, the chip 10 to which the liquid resin film 5 has been transferred is heated or dried to semi-cur the resin, whereby the semi-cured resin film 5 is formed. Thus, the interface between the wiring pad 2 and the protruding electrode 4 is covered and protected by the resin film 5.
【００２０】なお、この第１の工程においては、適当な
マスクを用い、フリップチップ１０の一面のうち配線パ
ッド２及び突起状電極３の表面以外をマスキングして、
上記樹脂の転写を行っても良い。それによっても、少な
くとも配線パッド２及び突起状電極３の表面上を液状も
しくは半硬化状態の樹脂膜５にて被覆することができ、
上記界面が該樹脂膜５によって被覆保護される。In the first step, masking is performed on one surface of the flip chip 10 except for the surfaces of the wiring pads 2 and the projecting electrodes 3 by using an appropriate mask.
The transfer of the resin may be performed. This also allows at least the surfaces of the wiring pads 2 and the protruding electrodes 3 to be covered with the liquid or semi-cured resin film 5,
The interface is covered and protected by the resin film 5.
【００２１】次に、第２の工程では、図１（ｃ）に示す
様に、予め用意された、一面側にランド６及びこのラン
ド６上に半田７が配設された基板（例えばプリント基
板、セラミック基板等）８を用いる。ここで、半田７と
しては、クリーム半田、または固体状の半田を用いる。
そして、図１（ｃ）に示す様に、樹脂膜５が液状もしく
は半硬化状態のまま、フリップチップ１０の一面と基板
８の一面とを対向させ、突起状電極４の先端部を半田７
に押しつける（圧着させる）ことにより、樹脂膜５のう
ち突起状電極４の先端部表面に付着していた樹脂膜５ａ
を排除して、突起状電極４の先端部と半田７とを接触さ
せる。Next, in a second step, as shown in FIG. 1C, a board (for example, a printed board) on which a land 6 and a solder 7 are disposed on one side, which is prepared in advance, is provided. , A ceramic substrate, etc.) 8. Here, cream solder or solid solder is used as the solder 7.
Then, as shown in FIG. 1C, one surface of the flip chip 10 and one surface of the substrate 8 face each other while the resin film 5 is in a liquid or semi-cured state, and the tip of the protruding electrode 4 is soldered.
The resin film 5a adhered to the surface of the tip of the protruding electrode 4 of the resin film 5
And the tip of the protruding electrode 4 is brought into contact with the solder 7.
【００２２】なお、この第２の工程において、樹脂膜５
を液状とした場合には、フリップチップ１０の一面と基
板８の一面とを対向させた状態のものを、加熱または乾
燥して樹脂膜５を半硬化状態とした後、突起状電極４の
先端部を半田７に押しつけて樹脂膜５ａを排除するよう
にしても良い。また、この第２の工程において、突起状
電極４の先端部の半田７への圧着は、常温または樹脂膜
５を軟化させるために加熱しながら（ただし、半硬化状
態を維持しながら）行うことができる。In the second step, the resin film 5
When the resin film 5 is in a liquid state, one surface of the flip chip 10 and one surface of the substrate 8 are opposed to each other, and the resin film 5 is heated or dried to a semi-cured state. The portion may be pressed against the solder 7 to remove the resin film 5a. In the second step, the tip of the protruding electrode 4 is pressed against the solder 7 at normal temperature or while heating to soften the resin film 5 (while maintaining a semi-cured state). Can be.
【００２３】次に、第３の工程では、まず、完全にフリ
ップチップ１０上の突起状電極４が半田７と接する状態
にしてから、更に樹脂膜５を加熱して硬化させ、半田７
を溶融しても突起状電極４と配線パッド２との界面（本
例ではＡｕ／Ａｌ界面）に付着させることの無いように
する。この時、樹脂膜５の硬化温度は、接合に使う半田
７の融点よりも低い温度で行うことが好ましい。通常、
半田７が電子部品に使用されるスズ・鉛系の共晶半田の
場合には、樹脂膜５の硬化温度は１８３℃以下である。Next, in a third step, first, the protruding electrodes 4 on the flip chip 10 are completely brought into contact with the solder 7, and then the resin film 5 is further heated and cured, and
Is not attached to the interface between the protruding electrode 4 and the wiring pad 2 (in this example, the Au / Al interface) even if the metal is melted. At this time, the curing temperature of the resin film 5 is preferably lower than the melting point of the solder 7 used for bonding. Normal,
When the solder 7 is a tin / lead eutectic solder used for an electronic component, the curing temperature of the resin film 5 is 183 ° C. or lower.
【００２４】その結果、突起状電極４と配線パッド２と
の界面近傍を硬化した樹脂によって完全に保護できる。
この後に、この第３の工程では、半田７による完全な接
合を行うために、リフロー炉やパルスヒート等による局
所加熱にて半田７を溶融（リフロー）させる。そして、
半田７を凝固させることにより、突起状電極４は半田７
によってランド６に接合される。こうして、フリップチ
ップ１０は基板８に電気的に接続され、チップ１０の基
板８への実装が終了する。ここまでが第３の工程であ
り、実装構造は図１（ｃ）にて図示される。As a result, the vicinity of the interface between the protruding electrode 4 and the wiring pad 2 can be completely protected by the cured resin.
Thereafter, in the third step, the solder 7 is melted (reflowed) by local heating using a reflow furnace, pulse heating, or the like in order to perform complete joining with the solder 7. And
By solidifying the solder 7, the protruding electrodes 4 become solder 7.
To the land 6. Thus, the flip chip 10 is electrically connected to the substrate 8, and the mounting of the chip 10 on the substrate 8 is completed. This is the third step, and the mounting structure is illustrated in FIG.
【００２５】なお、この第３の工程において、樹脂膜５
の硬化温度は、接合に使う半田７の融点と同程度か多少
高い温度であっても良い。その場合、樹脂膜５は半田７
の溶融時には完全に硬化しないが、硬化途中であって
も、溶融した半田７が上記界面まで流れない程度に硬化
できるものであれば良い。この場合、第３の工程におい
て、半田７を溶融させた後、さらに加熱を継続し、樹脂
膜５の硬化を終了させればよい。In the third step, the resin film 5
The curing temperature may be the same as or slightly higher than the melting point of the solder 7 used for bonding. In that case, the resin film 5 is
Is not completely cured at the time of melting, but may be any material that can be cured to the extent that the molten solder 7 does not flow to the interface even during the curing. In this case, in the third step, after the solder 7 is melted, the heating is further continued to terminate the curing of the resin film 5.
【００２６】ここで、上記実装方法により形成された本
実施形態の実装構造は、図１（ｃ）に示す様に、配線パ
ッド（配線部）２及び該パッド２上にワイヤボンディン
グ法により形成された突起状電極４を有するフリップチ
ップ（電子部品）１０と、ランド６及び該ランド６上に
配設された半田７を有する基板とを備え、突起状電極４
とランド６とが半田７により接合されており、配線パッ
ド２と突起状電極４との界面は樹脂膜５によって被覆さ
れて半田７から保護（ブロック）されたものとなってい
る。Here, as shown in FIG. 1C, the mounting structure of the present embodiment formed by the above mounting method is formed by a wiring pad (wiring portion) 2 and on the pad 2 by a wire bonding method. A flip chip (electronic component) 10 having the protruding electrode 4, and a substrate having a land 6 and a solder 7 disposed on the land 6.
And the land 6 are joined by the solder 7, and the interface between the wiring pad 2 and the protruding electrode 4 is covered with the resin film 5 and protected (blocked) from the solder 7.
【００２７】ところで、上記実装方法は、フリップチッ
プ１０において少なくとも配線パッド２及び突起状電極
４の表面上を液状もしくは半硬化状態の樹脂膜５にて被
覆する第１の工程と、樹脂膜５が液状もしくは半硬化状
態のまま、フリップチップ１０の一面と基板８の一面と
を対向させつつ、突起状電極４の先端部を半田７に押し
つけることにより樹脂膜５ａを排除して突起状電極４の
先端部と半田７とを接触させる第２の工程と、しかる
後、樹脂膜５を硬化させるとともに、半田７を溶融させ
て突起状電極４をランド６に電気的に接続する第３の工
程と、を備えている。The above mounting method includes a first step of covering at least the surfaces of the wiring pads 2 and the protruding electrodes 4 with the liquid or semi-cured resin film 5 in the flip chip 10; In the liquid or semi-cured state, the tip of the protruding electrode 4 is pressed against the solder 7 while the one surface of the flip chip 10 and the one surface of the substrate 8 are opposed to each other, thereby excluding the resin film 5 a to form the protruding electrode 4. A second step of bringing the tip into contact with the solder 7; and a third step of curing the resin film 5 and then melting the solder 7 to electrically connect the protruding electrode 4 to the land 6. , Is provided.
【００２８】この実装方法によれば、樹脂膜５を液状も
しくは半硬化状態とし、この状態で突起状電極４を半田
７に押しつけるから、樹脂膜５のうち突起状電極４の先
端部と半田７との間に位置する樹脂膜５ａを容易に排除
できる。そのため、当該間に樹脂が残らず、完全な半田
接合が実現でき、突起状電極４の接続性は確保できる。
また、半田７を溶融させる際、突起状電極４と配線パッ
ド２との界面は、硬化した状態もしくは硬化しつつある
状態の樹脂により半田７からブロックされているから、
当該界面に半田７が付着することはない。According to this mounting method, the resin film 5 is in a liquid or semi-cured state, and the protruding electrode 4 is pressed against the solder 7 in this state. Can be easily eliminated. Therefore, no resin is left between them, complete solder bonding can be realized, and the connectivity of the protruding electrodes 4 can be ensured.
When the solder 7 is melted, the interface between the protruding electrode 4 and the wiring pad 2 is blocked from the solder 7 by the resin in a hardened or hardening state.
The solder 7 does not adhere to the interface.
【００２９】また、上記実装方法によれば、樹脂膜５に
よって被覆する第１の工程は、樹脂の転写にて実行で
き、従来のウェハプロセスにおける蒸着やスパッタとい
った工程に比べて安価であり、これらウェハプロセス工
程を用いて突起状電極を形成する場合や、上記した従来
のバリアメタル形成の場合に比べて、製造コストのアッ
プが小さい。よって、上記実装方法によれば、コストア
ップを極力抑えつつ、突起状電極４と配線パッド２との
界面に半田７が付着するの防止することができ、突起状
電極４と配線パッド２との接続信頼性を確保することが
できる。Further, according to the above mounting method, the first step of coating with the resin film 5 can be performed by transferring the resin, and is inexpensive as compared with the steps of vapor deposition and sputtering in the conventional wafer process. The increase in manufacturing cost is smaller than in the case of forming a protruding electrode using a wafer process or in the case of forming a conventional barrier metal. Therefore, according to the mounting method described above, it is possible to prevent the solder 7 from adhering to the interface between the protruding electrode 4 and the wiring pad 2 while minimizing the cost increase. Connection reliability can be ensured.
【００３０】ここで、上記実装方法において、樹脂膜５
に用いる樹脂は、半田リフロー時には、半田溶融温度に
なるため、高温に耐える種類の物が好ましい。例えば、
ビスフェノールを主成分とした液状エポキシ樹脂（硬化
温度は１００〜１５０℃程度）や加熱硬化タイプのシリ
コーン樹脂（硬化温度は１４０℃程度）、ポリイミド樹
脂（硬化温度は１８０〜２００℃程度）等がある。な
お、これら熱硬化性樹脂を半硬化状態とすることは、硬
化時間を適宜調整する（例えば短めにする等）ことによ
り実施可能である。Here, in the above mounting method, the resin film 5
As the resin used for the above, the temperature at which the solder melts at the time of solder reflow is used, and therefore, a resin that can withstand high temperatures is preferable. For example,
Liquid epoxy resin containing bisphenol as a main component (curing temperature is about 100 to 150 ° C.), heat-curable silicone resin (curing temperature is about 140 ° C.), polyimide resin (curing temperature is about 180 to 200 ° C.), and the like. . The thermosetting resin can be brought into a semi-cured state by appropriately adjusting (for example, shortening) the curing time.
【００３１】（他の実施形態）なお、上記実施形態で
は、樹脂膜５は、フリップチップ１０の一面側のみに付
着し基板８側には付着していないが、図２の概略断面図
に示す様に、樹脂膜５は、チップ１０と基板８との間を
埋めるように充填し、チップ１０と基板８とを接着する
形状であっても構わない。従って、樹脂膜５の他の供給
方法としては、チップ１０に転写する以外にも、基板８
上に予め樹脂を塗布したり、半硬化状態のフィルム状の
樹脂を供給することによっても問題なく実施できる。(Other Embodiments) In the above embodiment, the resin film 5 adheres only to one surface side of the flip chip 10 and does not adhere to the substrate 8 side, but is shown in the schematic sectional view of FIG. As described above, the resin film 5 may be filled so as to fill the space between the chip 10 and the substrate 8 and may be shaped to bond the chip 10 and the substrate 8. Therefore, as another supply method of the resin film 5, besides the transfer to the chip 10,
It can be carried out without any problem by previously applying a resin thereon or supplying a film-shaped resin in a semi-cured state.
【００３２】これら他の供給方法によっても、フリップ
チップ１０において少なくとも配線パッド２及び突起状
電極４の表面上を液状もしくは半硬化状態の樹脂膜にて
被覆した状態のまま、チップ１０及び基板８の両一面を
対向させ、突起状電極４の先端部を半田７に押しつける
ことにより該樹脂膜を排除して突起状電極４の先端部と
半田７とを接触させることができる。According to these other supply methods, the chip 10 and the substrate 8 are kept in a state where at least the surfaces of the wiring pads 2 and the protruding electrodes 4 in the flip chip 10 are covered with a liquid or semi-cured resin film. By opposing the two surfaces and pressing the tip of the protruding electrode 4 against the solder 7, the resin film can be eliminated and the tip of the protruding electrode 4 can be brought into contact with the solder 7.
【００３３】なお、樹脂膜５に用いる樹脂としては、熱
硬化性樹脂以外にも、例えば紫外線等にて硬化する光硬
化性樹脂を用いても良い。また、本発明は半導体チップ
（半導体装置）の実装に限定されるものではなく、ワイ
ヤボンディング法により形成された突起状電極を有する
電子部品を基板上に実装するにあたって、該突起状電極
と基板のランドとを半田接合する電子部品の実装方法一
般に適用可能である。The resin used for the resin film 5 may be, for example, a photocurable resin that is cured by ultraviolet rays or the like, in addition to the thermosetting resin. Further, the present invention is not limited to the mounting of a semiconductor chip (semiconductor device), and when mounting an electronic component having a protruding electrode formed by a wire bonding method on a substrate, the protruding electrode and the substrate The present invention can be generally applied to a mounting method of an electronic component for soldering a land.
【図１】本発明の実施形態に係る実装方法を示す工程図
である。FIG. 1 is a process chart showing a mounting method according to an embodiment of the present invention.
【図２】本発明の他の実施形態を示す概略断面図であ
る。FIG. 2 is a schematic sectional view showing another embodiment of the present invention.
【図３】（ａ）は従来のフリップチップの概略断面図、
（ｂ）はウェハプロセスによってバンプが形成されたチ
ップの概略断面図、（ｃ）は（ａ）に示すチップの実装
状態を示す概略断面図である。FIG. 3A is a schematic cross-sectional view of a conventional flip chip,
(B) is a schematic sectional view of a chip on which bumps have been formed by a wafer process, and (c) is a schematic sectional view showing a mounted state of the chip shown in (a).
２…配線パッド、５…樹脂膜、６…ランド、７…半田、
８…基板、１０…フリップチップ。2 wiring pads, 5 resin films, 6 lands, 7 solders,
8: substrate, 10: flip chip.
Claims (2)
にワイヤボンディング法により形成された突起状電極
（４）を有する電子部品（１０）と、一面側にランド
（６）及びこのランド上に配設された半田（７）を有す
る基板（８）とを用意し、 前記電子部品において少なくとも前記配線部及び前記突
起状電極の表面上を液状もしくは半硬化状態の樹脂膜
（５）にて被覆した状態のまま、前記電子部品の前記一
面と前記基板の前記一面とを対向させ、前記突起状電極
の先端部を前記半田に押しつけることにより前記樹脂膜
を排除して前記突起状電極の先端部と前記半田とを接触
させる工程と、 しかる後、前記樹脂膜を硬化させるとともに、前記半田
を溶融させて前記突起状電極を前記ランドに電気的に接
続する工程と、を備えることを特徴とする電子部品の実
装方法。An electronic component (10) having a wiring part (2) on one surface side and a protruding electrode (4) formed on the wiring part by a wire bonding method, a land (6) on one surface side and a land (6). A substrate (8) having a solder (7) disposed on a land is prepared, and a liquid or semi-cured resin film (5) is formed on at least the surface of the wiring portion and the protruding electrodes in the electronic component. In the state covered with the above, the one surface of the electronic component and the one surface of the substrate are opposed to each other, and the tip of the protruding electrode is pressed against the solder to remove the resin film and remove the protruding electrode. Contacting the tip with the solder, and then hardening the resin film and melting the solder to electrically connect the protruding electrodes to the lands. Features and Implementation method of the electronic component that.
が前記半田（７）の溶融温度よりも低いものを用いるこ
とを特徴とする請求項１に記載の電子部品の実装方法。2. The electronic component mounting method according to claim 1, wherein the resin film has a curing temperature lower than a melting temperature of the solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26433399A JP2001085471A (en) | 1999-09-17 | 1999-09-17 | Method of mounting electronic component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26433399A JP2001085471A (en) | 1999-09-17 | 1999-09-17 | Method of mounting electronic component |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001085471A true JP2001085471A (en) | 2001-03-30 |
Family
ID=17401732
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26433399A Pending JP2001085471A (en) | 1999-09-17 | 1999-09-17 | Method of mounting electronic component |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001085471A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008219039A (en) * | 2008-04-21 | 2008-09-18 | Nec Electronics Corp | Semiconductor package and method of manufacturing the same |
| US7707716B2 (en) | 2006-05-10 | 2010-05-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing build-up printed circuit board |
| JP2010258045A (en) * | 2009-04-21 | 2010-11-11 | Fujitsu Ltd | Semiconductor device and method of manufacturing semiconductor device |
-
1999
- 1999-09-17 JP JP26433399A patent/JP2001085471A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7707716B2 (en) | 2006-05-10 | 2010-05-04 | Samsung Electro-Mechanics Co., Ltd. | Method of manufacturing build-up printed circuit board |
| JP2008219039A (en) * | 2008-04-21 | 2008-09-18 | Nec Electronics Corp | Semiconductor package and method of manufacturing the same |
| JP2010258045A (en) * | 2009-04-21 | 2010-11-11 | Fujitsu Ltd | Semiconductor device and method of manufacturing semiconductor device |
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