JP2001085430A - Wiring forming method for semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the flattening characteristics of CMP(chemical-mechanical polishing) by forming a metal film so that a half value width of rocking curve of the preference orientation plane of a metal film is controlled to a specified value or smaller. SOLUTION: An insulating film 2 is formed on a semiconductor substrate 1, and a wiring channel 5 is formed on the surface of insulating film 2, with a thin linear material 3 being formed on the surface of insulating film 2 as well as the inner surface of wiring channel 5. On the laminated film like this, a metal film 4 is deposited, and the surface of metal film 4 is polished with a polishing cloth 10. The linear material 3 and the metal film 4 except for in the wiring channel 5 are removed so that an embedded wiring 6 is formed inside the wiring channel 5. The metal film 4 constituting the wiring 6 is so formed that a half value width of the rocking curve for the preference orientation plane of the metal film 4 is controlled to 7 or less.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for digging a groove in an insulating film formed on a semiconductor substrate in the form of a wiring pattern, and further forming a metal film on the insulating film including the inside of the groove. The present invention relates to a method for forming a wiring in which an excess portion is removed to bury a wiring in a groove.

[0002]

2. Description of the Related Art With the increase in the density of semiconductor devices, the design rules have been reduced, and buried interconnects that are advantageous for the reduction have been frequently used. The buried wiring is formed by forming a wiring groove or a wiring groove and a connection hole in an interlayer insulating film by a reactive ion etching method or the like, and burying a conductive material such as a metal therein, so-called damascene (Da).
masses) step.

[0003]

As described above, when a metal film is buried in a wiring groove, a contact hole, or the like in a method of forming a buried metal wiring in an insulating film, the burying property is improved and a silicon oxide film (SiO ₂ film) is formed. In order to improve the adhesion to the metal film, a thin metal film (hereinafter, referred to as a liner material) different from this metal film is attached to the wiring groove, the contact hole, and the like, and then the metal film is embedded. Then, the metal film other than the one embedded in the wiring groove or the contact hole is subjected to CMP (Chemi
The buried wiring is formed by removing it by cal mechanical polishing. The orientation of the formed metal film is strongly affected by the liner material itself, the treatment after the liner material is formed, or the treatment before the metal film is formed. The polishing rate of CMP is strongly affected by the orientation of the metal film. Therefore,
The polishing rate of the CMP greatly differs depending on the conditions for forming the metal film, and as a result, the planarization characteristics also vary greatly.
The present invention has been made under such circumstances,
Provided is a wiring forming method for a semiconductor device, in which the orientation of a metal film polished by a CMP method is controlled to improve planarization characteristics of the CMP and form a uniform buried wiring.

[0004]

According to the present invention, a wiring groove or a wiring groove and a connection hole are formed in a wiring pattern on an insulating film formed on a semiconductor substrate. A metal film is deposited on this insulating film including the above, and an extra portion of the metal film is polished (polished).
In a wiring forming method for removing and embedding a wiring in a wiring groove or a wiring groove and a contact hole, a metal film is formed so as to control a half value width of a rocking curve of a preferential orientation plane of the metal film to 7 or less. And As described above, by defining the orientation of the metal film as the material of the embedded wiring, the polishing rate by the CMP method is increased, and the difference in the polishing rate between the convex portion and the concave portion on the semiconductor substrate is increased. And the surface of the insulating film in which the wiring is buried can be made a flat surface with few flaws.

That is, a method for forming a wiring of a semiconductor device according to the present invention comprises the steps of forming an insulating film on a semiconductor substrate, forming a wiring groove or a wiring groove and a connection hole by etching the insulating film; Depositing a metal film on the insulating film so as to be embedded in the wiring groove or the wiring groove and the connection hole; and polishing the metal film on the insulating film by polishing the metal film by a chemical mechanical polishing method. Removing and forming a buried metal wiring, and polishing the metal film having a rocking curve half-width of 7 or less of the closest surface of metal atoms of the metal film to 7 or less. The method for forming a wiring of a semiconductor device according to the present invention includes
Forming an insulating film on a semiconductor substrate, forming a wiring groove or a wiring groove and a connection hole by etching the insulating film, forming an adhesive layer on the insulating film, Depositing a first metal film on the adhesion layer so as to be embedded in the wiring groove or the wiring groove and the connection hole; and polishing the first metal film by a chemical mechanical polishing method. Removing the first metal film on the insulating film and embedding the metal film in the wiring groove or the wiring groove and the connection hole, wherein the half-width of the closest surface rocking curve of the first metal film is provided. The second feature is that a metal film having a value of 7 or less is polished.

[0006] The adhesion layer may be formed from a plurality of second metal films. When the second metal film is composed of two layers, the first layer may be composed of a titanium film, and the second layer on the first layer may be composed of a titanium nitride film. The film forming temperature for forming the first layer may be controlled to 250 ° C. or less. By controlling in this manner, the closest surface of the metal film can be formed, and as a result,
The polishing rate can be increased, and the planarization characteristics are improved.
Si, Al, Cu, Ag, Au, Ni,
Any one of Ti and Co can be included.
The metal film may include Al, W, Ti, TiN, Cu,
Nb, NbN, Ta, TaN, Ru, Ag, Au, WS
i can be applied.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 1 to FIG.
An example will be described. 1 is a cross-sectional view of a metal film for explaining a metal film polishing method by CMP, FIG. 2 is a perspective view for explaining a crystal structure of aluminum, and FIG. 3 is a metal film (Al-0.5% Cu film). FIG. 4 is a characteristic diagram showing the orientation dependency of the polishing rate on the crystal orientation, and FIG. 4 is a characteristic diagram showing the orientation plane dependence of the peak intensity (P) of the reflected light when the X-ray is inclined by 2θ with respect to the crystal plane. FIG. 4 is a process cross-sectional view illustrating a CMP method. A method for forming a wiring will be described with reference to FIG. For example, an insulating film 2 such as a silicon oxide film is formed on a semiconductor substrate 1 such as silicon. A wiring groove 5 is formed on the surface of the insulating film 2. A thin liner material 3 is formed on the surface of the insulating film 2 and the inner surface of the wiring groove 5. The liner material 3 is interposed in order to improve the embedding property of the metal film and to improve the adhesion with the silicon oxide film as the insulating film. In this embodiment, a laminated film of a Ti film and a TiN film formed thereon is provided. It is composed of

[0008] For example, Cu (0.5 w
(%) of a metal film 4 made of an aluminum alloy or the like. The surface of the metal film 4 is subjected to a CMP process (FIG. 5A). That is, the metal film 4 is polished using the polishing cloth 10, and the liner material 3 and the metal film 4 other than the wiring groove 5 are removed to form the buried wiring 6 inside the wiring groove 5 (FIG. 5B). In this method, the metal film forming the wiring 6 is formed so as to control the half width of the rocking curve of the plane having the preferred orientation direction of the metal film to 7 or less. Next, the influence of the orientation of the metal film on the CMP process will be described by changing the conditions for forming the metal film. The Al-0.5 wt% Cu film described above is used as the metal film. Then, this film is formed on an insulating film (SiO ₂ ) which is formed on a semiconductor substrate and does not form a wiring groove, via a liner material. The crystal lattice of the Al-0.5% Cu film is a face-centered cubic lattice, and the (111) plane is the closest plane as shown in FIG.
Al-0.5% C in which X-rays are inclined by a predetermined angle (2θ)
The magnitude (deg) of the half-width (P / 2) (half-width of the rocking curve) of the peak intensity (P) of the (111) plane obtained by irradiating the u film is the same as that of the Al-0.5% Cu film. (11
1) It is proportional to the degree of plane orientation.

The half width becomes smaller as the degree of orientation increases (see FIG. 4). This metal film is formed under various film forming conditions, and solid films of Al-0.5% Cu having different orientations are prepared. Each sample has a different half width. The half width of the peak of the (111) plane of sample 1 (S1) is 1.66, and the peak width of (11) of sample 2 (S2) is (11).
1) The half value width of the surface peak is 6.67, sample 3 (S
The half width of the (111) plane peak of 3) is 20.14, and the half width of the (111) plane peak of sample 4 (S4) is 3
7.58. Further, when the orientation of this sample is shown by the relative peak intensity ratio (the relative intensity ratio between the first preferred orientation orientation (111) and the other second orientation (311)), sample 1 (S1) shows that Relative intensity ratio ((111) / (31
1)) (= infinity), sample 2 (S2) has a relative intensity ratio ((111) / (311)) (= infinity), and sample 3 (S3) has a relative intensity ratio ((111) /
(311)) (= 96.3) and sample 4 (S
4) is the relative intensity ratio ((111) / (311)) (=
4.3).

As the CMP conditions, alumina (Al ₂ O 3)
₃ ) Use an abrasive in which particles are dispersed in 0.5 wt% pure water. Urethane foam with a thickness of 2 mm is used as the polishing cloth. The Al-0.5% Cu solid film prepared in this way is
Polishing was performed for 0 seconds, and the amount of polishing per minute (polishing rate) was measured. The measured polishing rate of the sample was the sample 1 (S
1) is 516.8 nm / min, sample 2 (S2) is 502.5 nm / min, and sample 3 (S3) is 42
2.4 nm / min, and 32 for sample 4 (S4)
6.0 nm / min. In FIG. 3 showing the orientation dependency of the polishing rate of the metal film, the vertical axis represents the polishing rate (nm / min), the horizontal axis represents the half-value width (P / 2) of the (111) plane peak, That is, it represents the half width (deg) of the rocking curve. From the above, the polishing rate is strongly affected by the orientation of the metal film, and
In the case of a% Cu film, the polishing rate tends to increase as the orientation becomes closer to the (111) plane which is the closest plane. In particular, when the half width becomes 7 or less, the polishing rate becomes 500 nm /
min, and a CMP method excellent in flattening can be performed.

The reason why the polishing rate is higher as the crystal is oriented to the (111) plane is as follows. First, as shown in FIG. 1, in the CMP mechanism of the Al-0.5% Cu film, first, the surface of the Al-0.5% Cu film is oxidized. Next, the formed oxide (Al ₂ O ₃ ) is peeled off by the abrasive particles. By repeating such operation, CM
P proceeds. On the other hand, the crystal lattice of Al-0.5% Cu is a face-centered cubic lattice as described above, and its (111)
The surface is the closest surface. Therefore, in the oxidation of the surface, which is the first stage of the CMP treatment, if the (111) plane, which is the closest surface, is exposed on the surface, the oxidation efficiency is increased and the polishing rate is increased. The (111) plane is a slip plane in a face-centered cubic lattice. Therefore, the surface becomes weak against shear stress. Since a strong shear stress is applied in CMP, the polishing speed increases as the surface to be polished is oriented to the (111) plane. As described above, by defining the orientation of the metal film as the material of the buried wiring, the polishing rate by the CMP method is increased, the planarization characteristics are improved, and the surface of the insulating film in which the wiring is buried is flattened with less flaws. Surface.

Next, the flattening process will be described with reference to FIGS. FIG. 6 is a cross-sectional view of a semiconductor substrate made of silicon or the like on which a metal film is deposited, FIG. 7 is a characteristic diagram showing a relationship between a step on the metal film and the amount of polishing of the convex portion, and FIG. FIG. 4 is a characteristic diagram showing the relationship of FIG. An insulating film 25 made of a SiO ₂ film having a thickness of about 400 nm is formed on the silicon semiconductor substrate 1. A wiring groove 26 having a wiring width of 0.2 μm and a depth of 400 nm is formed in the insulating film 25 by lithography. An Al-0.5% Cu film 27 is deposited thereon via a liner material (not shown). Al-0.5% Cu showing two types of orientation under different orientation conditions
A film is deposited on the liner material to a thickness of about 800 nm. These two types of metal films having different orientations are referred to as samples A and B, respectively (see FIG. 7). At this time, Al-0.5% C
The step d after the formation of the u film was 40
It was 0 nm. Then, the polishing rate and 4
The relationship between the protrusion polishing amounts required until the 00 nm step is alleviated is measured (FIG. 7). The polishing rate of sample A was 4
50 nm / min, polishing rate of sample B was 150 n
m / min. Looking at the relationship between the step (d) and the polishing amount of the projections shown in FIG. 7 under these conditions, it was found that the higher the polishing rate, the smaller the polishing amount required until the surface was flattened.

To explain the reason, as shown in FIG. 8, a high polishing rate means that the polishing rate has a large load dependency. As for the planarization mechanism of CMP, the planarization proceeds due to the difference in polishing rate between the convex portions and the concave portions. Therefore, the greater the load dependency of the polishing rate, the greater the difference in the polishing rate between the convex and concave portions, and the flattening phenomenon in which the difference between the two is eliminated proceeds more rapidly.

Next, a second embodiment will be described with reference to FIGS. 9 to 12 and FIG. 9 is a schematic cross-sectional view of a CMP apparatus, FIG. 10 is a characteristic diagram showing the dependence of the polishing rate of a tungsten film on the half width of a rocking curve, FIG. 11 is a cross-sectional view illustrating CMP polishing of a tungsten film, and FIG. Is a perspective view showing the crystal structure of tungsten, FIG.
FIG. 3 is a sectional view of a tungsten film formed on a semiconductor substrate. In this embodiment, unlike the aluminum-based metal film of the first embodiment, a tungsten-based metal film composed of Sample 1 and Sample 2 is used. A method for forming the tungsten film samples 1 and 2 will be described with reference to FIG. In this embodiment, a blanket when a Ti / TiN film is used as an adhesion layer as a liner material
This shows that, when a tungsten film is formed by a tungsten CVD method, heating at an appropriate temperature during the formation of the varimetallic Ti results in favorable W orientation. An insulating film 42 such as a silicon oxide film is formed on a semiconductor substrate 41 such as silicon. The wiring groove 45 is formed on the surface of the insulating film 42.
On the inner surface of the substrate is a thin Ti / Ti
An N film 43 is formed.

The Ti / TiN film 43 is interposed for improving the burying property of the metal film and for improving the adhesion to the silicon oxide film as the insulating film. A tungsten film 44 (Sample 1 or Sample 2) is deposited on this laminated film. The surface of the tungsten film 44 is subjected to a CMP process. Sample 1 has a relative intensity ratio ((11) between the first preferred orientation (110) and the other second orientation (100).
0) / (100)) (= 300), sample 2
Is the relative intensity ratio ((110) / (100)) (= 10)
have.

FIG. 9 is a schematic sectional view of a CMP apparatus.
The polishing plate 9 supported by the rotating shaft 8 supports and fixes a polishing cloth 10 made of polyurethane or the like on the surface. A silicon wafer (semiconductor substrate) is provided on the main surface of the polishing cloth 10.
1 are facing each other. The wafer 1 is fixed with a main surface exposed by a support 11 supported by a rotating shaft 12. CMP polishing is performed using a rotating polishing cloth 10.
, The wafer 1 rotating starts to contact. Polishing is performed while the abrasive 13 is injected into the action point. Polishing by this CMP method includes iron nitrate,
An abrasive 13 in which 0.5 wt% alumina (Al ₂ O ₃ ) particles are dispersed in pure water is used. The polishing cloth 10 is 2 mm thick.
Use a polishing cloth. The prepared tungsten (W) solid film is subjected to CMP polishing, and a change in the weight is captured, thereby measuring an end point and measuring a polishing amount per minute (polishing rate). The polishing rate is strongly affected by the orientation of the metal film. That is, sample 1 is 260n
Sample 2 had a polishing rate of 160 m / min.
It has a polishing rate of m / min. And (11
The polishing rate for tungsten tends to increase as the crystal is oriented in the 0) plane.

Further, the orientation plane of the tungsten film (110)
The magnitude (deg) of the half width of the rocking curve with respect to
Sample 1 is 1.54 and sample 2 is 9.5. Polishing rate (nm / m) of tungsten film on orientation surface (110)
FIG. 10 shows the relationship between the “in” and the half width (deg) of the rocking curve. As shown in FIG. 10, the polishing rate of the tungsten film is equal to the half width (de) of the rocking curve.
The polishing rate can be maintained at 200 nm / min if g) is smaller and the half width is about 7 or less. The polishing rate of the tungsten film increases as the orientation plane is oriented to the (110) plane for the following reason. FIG.
As shown in the figure, the polishing mechanism of tungsten is
First, the surface of the tungsten film is oxidized. Next, the formed oxide (W ₂ O ₃ ) is peeled off by the abrasive particles. By repeating this, CMP polishing proceeds.

On the other hand, the crystal lattice of tungsten is shown in FIG.
As shown in the figure, it is a body-centered cubic lattice, and the (110)
The surface is the closest surface. Therefore, the first stage of CMP,
In the oxidation of the surface, if the (110) plane, which is the closest surface, is exposed on the surface, the oxidation efficiency increases and the polishing rate increases. The (110) plane is a body-centered cubic lattice,
It becomes a slip surface. Therefore, the surface is weak against shear stress. In CMP, a strong shear stress is applied (11
The polishing rate increases as the orientation increases in the 0) plane.

Next, a third embodiment will be described with reference to FIGS. The tungsten film formed on the semiconductor substrate shown in FIG. 14 has been described in the second embodiment and will not be described. The surface of the tungsten film 44 formed here has C
Perform MP processing. By continuously forming a Ti film and a TiN film and performing annealing, a barrier metal serving as a tungsten adhesion layer is formed. This Ti film has a (011) plane as its preferred orientation direction. In addition, by performing heating during the Ti film formation, energy is applied during the Ti film formation, and it is possible to preferentially orient Ti (011). However, if the temperature is too high,
It can be seen that the preferred orientation is destroyed. Further, since Ti (011) and TiN (111) have almost the same lattice constant,
The iN (111) orientation can be preferentially oriented. T
The i orientation and the tungsten orientation are closely related, and the tungsten orientation can be changed to (110) by heating during Ti film formation.
It becomes possible to break in the direction.

FIG. 15 shows the relationship between the Ti film formation temperature and tungsten orientation. When the Ti film formation temperature is set to, for example, 2
It is understood that the tungsten orientation can be increased by setting the temperature to 50 ° C. or lower. As described above, by setting the Ti film forming temperature to 250 ° C. or lower, the relative intensity ratio (ratio between the (110) plane and the (100) plane of tungsten) is reduced to 5%.
It can be 0 or more. By doing so, the number of (110), which is the closest surface, increases, so that the polishing rate can be increased. When the polishing rate is increased, the polishing rate for the convex portions of the metal film is increased, so that the flattening characteristics are improved.

Next, a fourth embodiment will be described with reference to FIG. FIG. 13 is a characteristic diagram illustrating the relationship between the CMP time and the number of scratches on the silicon oxide film. As in the second embodiment, a silicon oxide film (SiO ₂ ) is formed on a silicon semiconductor substrate, and a metal film is formed on the silicon oxide film by changing the film forming conditions. Samples 1 and 2 which are solid films are prepared.
Alumina in CMP (Al ₂ 0 ₃₎ particles 0.5 wt%
Use an abrasive dispersed in pure water. Polishing cloth is 2m thick
Use a urethane foam polishing cloth of m. The prepared tungsten film is subjected to CMP polishing until it is completely removed from the silicon oxide film in the wafer surface. The polishing rate of Sample 1 was 260 nm / min, and the polishing rate of Sample 2 was 1
It was 60 nm / min. Sample 1 required 20 seconds from the beginning of the disappearance of part of the tungsten in the wafer surface to the disappearance of all the tungsten. Sample 2 required 60 seconds. The number of scratches on the silicon oxide film after the CMP is measured by an optical defect detector. Sample 1 had 11 scratches and Sample 2 had 260 scratches. This indicates that the higher the polishing rate, the smaller the number of scratches applied to the silicon oxide film.

This is for the following reason. A sample in which a silicon oxide film (SiO ₂ ) was formed on a silicon semiconductor substrate was prepared and subjected to the above-mentioned CMP conditions for 20 seconds.
CMP polishing is performed for c, 40 sec, and 60 sec, respectively, and the number of scratches after the CMP is measured. FIG.
As shown in the figure, it was found that the number of scratches increased exponentially with an increase in the CMP time. Therefore,
The shorter the time from when some tungsten in the wafer surface begins to disappear to when all the tungsten disappears, the shorter the number of scratches applied to the silicon oxide film decreases. According to the present invention, the same effect can be obtained even when the interlayer insulating film surface is subjected to CMP. As mentioned above,
By improving the orientation of the metal film, the planarization characteristics of the CMP can be improved.

[0023]

As described above, by improving the orientation of the metal film, the planarization characteristics of the CMP can be improved, and as a result, the buried wiring on the semiconductor substrate whose surface has been effectively planarized can be improved. Can be formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of an aluminum film for explaining a method of polishing an aluminum film by CMP according to the present invention.

FIG. 2 is a perspective view showing a crystal structure of aluminum.

FIG. 3 is a characteristic diagram showing the orientation dependency of the CMP rate of the aluminum film according to the present invention.

FIG. 4 is a characteristic diagram showing an orientation plane dependence of a peak intensity (P) of reflected light when an X-ray is inclined by 2θ with respect to a crystal plane.

FIG. 5 is a process sectional view for explaining the CMP method of the present invention.

FIG. 6 is a cross-sectional view of a semiconductor substrate such as silicon on which a metal film of the present invention is deposited.

FIG. 7 is a characteristic diagram showing a relationship between a step on a metal film and a polishing amount of a convex portion.

FIG. 8 is a characteristic diagram showing a relationship between a polishing rate and a pressing load.

FIG. 9 is a schematic sectional view of a CMP apparatus illustrating the present invention.

FIG. 10 is a characteristic diagram showing the dependence of the polishing rate of a tungsten film on the half width of the rocking curve for explaining the present invention.

FIG. 11 is a cross-sectional view illustrating CMP polishing of a tungsten film.

FIG. 12 is a perspective view showing a crystal structure of tungsten.

FIG. 13 is a characteristic diagram illustrating a relationship between a CMP time and the number of scratches on a silicon oxide film.

FIG. 14 is a cross-sectional view of a tungsten film formed over a semiconductor substrate for explaining the present invention.

FIG. 15 is a characteristic diagram showing a relationship between a Ti deposition temperature and tungsten orientation in the present invention.

[Explanation of symbols]

1 ... semiconductor substrate (silicon wafer), 2, 25,
42 ... insulating film, 3 ... liner material, 4 ... metal film, 5, 26, 45 ... wiring groove, 6 ... wiring,
8, 12: rotating shaft, 9: polishing machine, 10
... Abrasive cloth, 11 ... Support, 13 ...
Abrasive, 27... Al-0.5% Cu film, 41.
..Semiconductor substrate, 43... Ti / TiN film, 44
... Tungsten film.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Atsushi Shigeta, 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Masako Kinoshita, 8-8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa (72) Inventor Hiroshi Kosukegawa, Inventor Hiroshima, Kanagawa Pref., 8-8, Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa Prefecture (72) Inventor Katsumi Yamamoto, 8-8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa, Japan Toshiba Corporation Inside the Yokohama Office (72) Inventor Keiichi Watanabe 8-8 Shinsugitacho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Yoshikuni Tateyama 8-8 Shinsugitacho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Yokohama Co., Ltd. In-house (72) Inventor Hirokazu Ezawa 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Toshiba Corporation Beach business-house F-term (reference) 5F033 HH04 HH05 HH06 HH07 HH09 HH11 HH13 HH14 HH17 HH18 HH19 HH21 HH28 HH32 HH33 JJ04 JJ05 JJ06 JJ07 JJ09 JJ11 JJ13 JJ14 JJ17 JJ18 JJ19 JJ21 JJ28 JJ32 JJ33 LL07 MM01 MM12 NN06 PP06 QQ48 RR04 WW03

Claims (5)

[Claims] A step of forming an insulating film on a semiconductor substrate;
Forming a wiring groove or a wiring groove and a connection hole by etching the insulating film; and depositing a metal film on the insulating film so as to be embedded in the wiring groove or the wiring groove and the connection hole; Polishing the metal film by a chemical mechanical polishing method to remove the metal film on the insulating film,
Forming a buried metal wiring, wherein the half-value width of the rocking curve of the closest surface of metal atoms of the metal film is 7
A method for forming a wiring in a semiconductor device, comprising polishing a metal film controlled as follows. A step of forming an insulating film on the semiconductor substrate;
Forming a wiring groove or a wiring groove and a connection hole by etching the insulating film; forming an adhesive layer on the insulating film; and forming the wiring groove or the wiring on the adhesive layer on the insulating film. Depositing a first metal film so as to be buried in the groove and the connection hole, and removing the metal film on the insulating film by polishing the first metal film by a chemical mechanical polishing method; Forming a buried metal wiring, and polishing the metal film in which the half value width of the rocking curve of the closest surface of the metal atoms of the first metal film is controlled to 7 or less. Wiring formation method. 3. The method according to claim 2, wherein the adhesion layer is formed from a plurality of second metal films. 4. When the second metal film is composed of two layers, the first layer is composed of a titanium film and the second layer on the first layer is composed of a titanium nitride film. 4. The method for forming a wiring of a semiconductor device according to claim 1. 5. The method according to claim 4, wherein a film forming temperature for forming the first layer is controlled to 250 ° C. or lower.