JP2001077238A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, capable of preventing disconnection of regular wirings by allowing dummy wirings to block the growth of cracks, and preventing crackings and subsequent disconnections of the wirings by eliminating stress concentrations at peeled-off portions. SOLUTION: A BGA(ball grid array) surface-mount package is of a molded structure 2, where a chip is mounted on a substrate and sealed with a sealing material. Dummy metallized wirings 16 are provided, in order to prevent breake of regular metallized wirings 13 (13a to 13d) on a fourth layer on the underside of the substrate 2. The wirings 16 are provided on both sides or on one side along the conductors 13, or so as to fill the clearances between the wirings 13, or the wirings 13 and 16 are formed to be relatively large in width. Furthermore, a resist is provided with openings which are formed in a first layer of the surface of the substrate 2, at locations where the resist and the sealing material are easily peeled off.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packaging technology for a semiconductor device, and more particularly, to a method for mounting a resist for insulation on a front surface and a back surface of a substrate, and sealing a chip mounted on the substrate with a plastic resin. The present invention relates to a technique which is effective when applied to a semiconductor device having a mold structure.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventor, in a package having a mold structure in which a chip mounted on a substrate is sealed with a plastic resin, generally,
2. Description of the Related Art For the purpose of insulating electrically exposed portions such as wirings provided on a substrate, a technique of applying an insulating film of a resist on the surface of the substrate has been used. As a technique related to such a package, there is a technique disclosed in Japanese Patent Application Laid-Open No. H11-17099 in which four chips are mounted on a substrate.

[0003]

By the way, in the above-mentioned package technology for providing an insulating film of a resist on the surface of a substrate, the resist generally has a larger coefficient of linear expansion than the substrate itself, and a resin material to be sealed. It is known that the adhesiveness with the plastic resin used for the resin is not so good. As a result, the following can be considered.

(1) The resist is easily cracked due to the difference in expansion coefficient between the resist and the substrate itself, which can be developed by the temperature cycle of the environment in which the product is used, spread to the wiring under the resist, and lead to the disconnection of the wiring. There is.

(2) When bending and cutting the plastic resin at the injection port after molding, stress concentrates on the tip of the peeling of the resist and the plastic resin, causing the resist to crack, which is the same as in the above (1). There is a possibility that the wiring may be disconnected.

Accordingly, an object of the present invention is to pay attention to the occurrence of the cracks in the resist leading to the disconnection of the wiring as described above, and to prevent the propagation of the crack by the dummy wiring to prevent the disconnection of the regular wiring. It is another object of the present invention to provide a semiconductor device capable of preventing a crack and subsequent wiring disconnection by eliminating stress concentration at a peeling portion.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the present invention, a chip provided with a plurality of pads electrically connected to a predetermined circuit, and a plurality of pads electrically connected to respective pads on the chip are provided on a surface thereof. A plurality of external terminals electrically connected to each pad on the front surface are provided on the back surface, and a substrate on which an insulating film is attached is provided on the front surface and the back surface, and the chip is mounted on the substrate, The present invention is applied to a semiconductor device having a mold structure sealed with a sealing material and has the following features.

In other words, the semiconductor device of the present invention relates to a regular wiring for electrically connecting each pad on the front surface and each external terminal on the rear surface with respect to the back surface of the substrate, and is arranged around the wiring. Dummy wiring for preventing disconnection of wiring is provided. In this configuration, the dummy wiring is provided so as to fill the gap between the regular wirings, and the regular wiring and the dummy wiring are provided with a relatively large wiring width. Thus, the break of the regular wiring can be prevented by the dummy wiring obstructing the progress of the crack.

In another semiconductor device of the present invention, an opening which does not cover the insulating film is provided in a portion of the surface of the substrate where the insulating film and the sealing material are easily peeled off. In this configuration, the opening is provided at a corner of the substrate in a direction in which the sealing material is injected. As a result, stress concentration at the peeled portion can be eliminated, and cracks and subsequent disconnection of the wiring can be prevented.

Further, another semiconductor device according to the present invention relates to wiring of a substrate, wherein an end face is provided in a separated / curved shape in order to prevent disconnection of the wiring. This makes it difficult for cracks to extend, thereby preventing disconnection of regular wiring.

In the configuration of the semiconductor device described above,
The insulating film is made of resist, the sealing material is made of plastic resin, and each chip is composed of a plurality of chips on each of which a memory circuit is formed. The present invention can be applied to a memory package configured by mounting on a memory device.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 to 3 are diagrams for explaining a schematic configuration of a semiconductor device according to an embodiment of the present invention, FIGS. 4 to 8 are diagrams for explaining a structure of a substrate in detail, and FIG. 9 is a semiconductor device. FIG. 4 is a diagram for explaining an assembly flow of FIG.

First, a schematic configuration of an example of the semiconductor device according to the present embodiment will be described with reference to FIGS. 1 is a plan view, FIG. 2 (a) is a front view, FIG. 2 (b) is a side view, FIG. 2 (c) is a bottom view, and FIG. 3 is a cross section taken along line AA 'in FIG. FIG.

The semiconductor device according to the present embodiment has, for example, B
Four chips 1 on which a memory circuit is formed, a surface mount package of a GA (Ball Grid Array), a substrate 2 on which the four chips 1 are mounted, and pads and chips 1 on the substrate 2 A wire 3 for connecting the upper pad; a solder ball 4 provided on the back surface of the substrate 2; and a sealing material 5 for molding the chip 1 and the wire 3 mounted on the substrate 2.
It is composed of As shown in FIG. 1, a mark 6 indicating the direction of the package is provided at one corner of the surface of the package.

Each of the four chips 1 has, for example, 6
4M-SDRAM (Synchronous Dynamic Random Acces)
s Memory) is formed, and a plurality of pads electrically connected to the storage circuit are provided on the surface.
With these four 64M-SDRAM chips 1, 25
A 6M-SDRAM MCP (Multi Chip Package) is configured.

The substrate 2 has, for example, a four-layered multi-layer wiring structure made of a glass epoxy material having a metal thin film such as copper (Cu) applied to each layer, and has a die bonding material such as an epoxy resin on its surface. Chip 1 through 7
Are mounted, and a plurality of pads which are electrically connected to respective pads on the chip 1 via wires 3 are provided on the surface. Each pad on this surface is electrically connected to a solder ball connection land on the back surface via a wiring pattern of each layer and a through hole filled with a conductive material penetrating each layer. Each layer of the substrate 2 is shown in FIGS.
The function and structure are as shown in FIG.

The wire 3 is made of a metal wire (bonding wire) such as gold (Au), and the pads on the substrate 2 and the pads on each chip 1 are electrically connected by wire bonding using the wire 3. Is done.

The solder ball 4 is made of, for example, lead / tin (P
b / Sn) and a plurality of solder balls 4 electrically connected to each land disposed on the back surface of the substrate 2 on the back surface of the substrate 2. I have.

The sealing material 5 is made of, for example, a resin material such as a plastic resin. The sealing material 5 covers the electrically exposed portions such as the chip 1 and the wires 3 mounted on the substrate 2 and is molded. A BGA surface mount package structure is obtained.

Next, the structure of an example of the substrate 2 will be described in detail with reference to FIGS. FIG. 4 is a schematic plan view showing a state in which the chip 1 is mounted on the substrate 2 (the sealing material 5 is omitted), and FIG. 5 is a sectional view taken along the line BB ′ of FIG.
6 to 8 are plan views showing wiring patterns of each layer of the substrate 2, FIG. 6 shows a first layer, FIG. 7 shows a second layer, and FIG. 8 shows a fourth layer.

As shown in FIG. 4, four substantially rectangular chips 1 (1a, 1b,
1c, 1d) are mounted, and the four chips 1 are arranged in a matrix (lattice form) by two vertically (long side direction) / left and right (short side direction) in FIG. The four chips 1 are arranged symmetrically with respect to the center line in the long side direction of the substrate 2 on the upper side and the lower side. That is, the four chips 1 are provided with a pair of short side marks F attached to the index 8 made of gold plating or the like indicating the direction of the substrate 2 for indicating the direction of the chip 1 for explanation. Are arranged adjacent to each other.

In each chip 1, a plurality of pads 9 are arranged in substantially one line substantially on the center line in the short side direction.
The plurality of pads 9 arranged in substantially one line by a so-called center pad arrangement structure include address signal address pads 9a, control signal control pads 9b, input / output data input / output pads 9c, power supply voltage, and ground. A power supply pad 9d for voltage or the like is provided.

FIG. 5 is a sectional view taken along the line BB 'passing through the portion of the address pad 9a. As shown in FIG. 5, the substrate 2 has a four-layer wiring structure. The first layer, which is the uppermost layer, is the signal layer (1), the second layer is the ground voltage (VSS) layer of the power supply, and the third layer is the power supply layer. , And the fourth layer, which is the lowest layer, is assigned to the signal layer (2). The substrate 2 having the four-layer wiring structure has through holes 10 filled with a conductive material penetrating through each layer.
The desired wiring pattern of each layer is connected via the.
In addition, openings, pads,
A resist 11, which is an insulating film for electrically insulating except for each part of the land, is applied.

The first uppermost layer of the substrate 2 is as shown in FIG. As shown in FIG. 6, on the first layer of the substrate 2, a plurality of pads 12 electrically connected to the respective pads 9 on the chip 1 via the wires 3 at the center along the long side direction of the substrate 2. And two rows, one row on each side of the peripheral part. That is, the pads 12 are provided in two rows on the inner side and the outer side separately on both sides of the mounting area of the chip 1. Further, through holes 10 connected to the respective pads 12 by a wiring pattern are arranged in a mounting area of the chip 1, a peripheral portion of the substrate 2, and the like.

In the first layer of the substrate 2, an address wiring 13a and an address through hole 10a connected to the address pad 12a for each address signal, and a control line 12a connected to the control pad 12b for each control signal. Wiring 13b, control through hole 10b, input / output wiring 1 connected to input / output pad 12c for each input / output data
3c, an input / output through-hole 10c, a power supply wiring 13d connected to the power supply pad 12d of each power supply, and a power supply through-hole 10d.

In the first layer of the substrate 2, an opening 15 not coated with the resist 11 is provided in a portion where the resist 11 and the sealing material 5 are easily peeled off. For example, as shown by a thick line in FIG. 6, the opening 15 is provided at a corner of the substrate 2 in a direction in which the sealing material 5 is injected, at all four corners, or in a short side direction. By providing the resist 11 on the periphery or the like, the resist 11 is left open from the beginning, stress concentration at the peeled portion between the resist 11 and the sealing material 5 can be eliminated, and cracks can be prevented.
There is no disconnection of the wiring 13 (13a to 13d).

Subsequently, the second layer of the substrate 2 is as shown in FIG. As shown in FIG. 7, the second layer has a ground voltage (VS
This is a so-called solid wiring in which the power supply wiring 13d of S) is spread. That is, the second layer includes the power supply wiring 13 including the power supply through hole 10d for the ground voltage.
d, and the other through holes 10a to 10c for the power supply voltage, the address signal, the input / output data, and the control signal.
The periphery of 10c has no wiring 13d.

In the second layer of the substrate 2, in particular, the wiring 13
In order to prevent disconnection, the end face of the wiring 13d is provided in a separated and curved shape. For example, through hole 10
Are separated by a curved surface completely surrounding the peripheral portion of the through hole 10 to provide the wiring 13d, and the portion where the through hole 10 is close is a curved surface along the peripheral portion of the through hole 10. By providing the wiring 13d,
Since it is difficult to extend the crack, disconnection of the wiring 13 can be prevented.

The third layer of the substrate 2 is not shown,
As in FIG. 7, the power supply wiring 1 of the power supply voltage (VDD) is provided.
3d is a so-called solid wiring. That is, in the third layer, the power supply wiring 13d is laid, including the power supply through hole 10d for the power supply voltage, and the other ground voltage, address signal, input / output data,
The peripheral portions of the control signal through holes 10a to 10c have no wiring 13d. Similarly to the second layer, the end face of the wiring 13d is provided in a separated / curved shape in order to prevent disconnection of the wiring 13 in the third layer of the substrate 2 as well.

Next, the fourth lowermost layer of the substrate 2 is as shown in FIG. As shown in FIG. 8, on the fourth layer of the substrate 2, a plurality of lands 14 to which the solder balls 4 serving as external terminals are electrically connected are arranged in the peripheral portion of the substrate 2 except for the central portion. . That is, the lands 14 are 4 (up and down) × 9 (left and right) by 8 (in the long side direction of the substrate 2)
It is provided in a matrix of (up and down) x 9 (left and right), and 9 (up and down) x 2 (left and right) at the center is 9 (up and down) on the left and right sides.
It is provided in a matrix of × 4 (left and right). Therefore, the solder balls 4 bonded to these lands 14 are provided by the number of 108 pieces. The through holes 10 connected to the lands 14 by wiring patterns are arranged at the same positions as the above-described first to third layers.

In the fourth layer of the substrate 2, similarly to the first layer, the address lands 1 for each address signal are provided.
4a, an address wiring 13a for connecting to the address through hole 10a corresponding to the address, a control wiring 13b for connecting to the control through hole 10b corresponding to the control land 14b for each control signal, and input / output of each input / output data Wiring 13c for connecting the input / output through hole 10c corresponding to the power land 14c, and the power supply land 14d for each power supply
Wiring 1 for connecting the power supply through hole 10d to the power supply
3d are provided respectively.

In the fourth layer of the substrate 2, in addition to the regular wirings 13 (13a to 13d),
, And a dummy wiring 16 for preventing disconnection of the wiring 13 is provided. This dummy wiring 1
For example, as shown in FIG. 8, the dummy wiring 16 is provided on both sides or one side of the regular wiring 13 as shown in FIG. There is no disconnection.
Furthermore, the dummy wiring 16 is provided to extend in the direction in which the regular wiring 13 is vacant so as to fill the gap (shown as a blank), or the regular wiring 13 and the dummy wiring 16 are provided with a relatively large wiring width. This makes it even more difficult to break the regular wiring 13.

Next, referring to FIG. 9, the BGA of this embodiment will be described.
An example of an assembly flow of the surface mount package will be briefly described.

First, prior to assembling, a chip 1 on which an SDRAM diced from a wafer is formed, a substrate 2 having a four-layer wiring structure formed in a plurality of units such as six strips, an epoxy resin or the like. Die bonding material 7,
Wire 3 such as gold, sealing material 5 such as epoxy resin, lead /
A solder ball 4 such as tin is prepared.

As described above, in the substrate 2 having the four-layer wiring structure, the opening 11 of the resist 11 is provided in the first layer where the resist 11 and the sealing material 5 are easily peeled off. In the layer, the end face of the wiring 13d is separated and
In the fourth layer, a dummy wiring 16 is provided around a regular wiring 13 in the fourth layer.

First, in a die bonding step, a plurality of chips 1 are respectively mounted via a die bonding material 7 on a plurality of mounting regions on the substrate 2 formed in a strip shape (S1). Further, in the wire bonding step, each pad 9 on each of the plurality of chips 1 and each pad 12 on the substrate 2 are connected by the wire 3 (S
2).

Subsequently, in a sealing step, the strip-shaped substrate 2 on which the plurality of chips 1 are mounted is molded with the sealing material 5 so that the chips 1 and the wires 3 are not exposed (S3). At this time, the sealing material 5 is heated and plasticized by, for example, transfer molding, and is pressed into a heated mold to be molded. The opening 15 of the resist 11 provided on the substrate 2 is effective in this step.

Further, in the solder ball attaching step,
A solder ball 4 serving as an external terminal is bonded to the back surface of the substrate 2 (S4). Finally, in the board cutting step, the strip-shaped board 2 is cut off from the frame to be separated into individual packages (S5). Thereby, a BGA surface mount type package can be completed.

This BGA surface mount type package is, for example, a SODIMM (Small Outline Dual Inline Memory).
It is mounted on a substantially rectangular module substrate as a module, and is incorporated as a memory module in various devices such as a computer, for example, and is used as a main storage device for storing a large amount of data and the like.

Therefore, according to the BGA surface mount type package of the present embodiment, the following effects can be obtained.

(1) Dummy wiring 1 around regular wiring 13
The provision of 6 makes it difficult for the resist 11 to crack even with respect to the difference in the expansion coefficient between the resist 11 and the substrate 2, and also in the temperature cycle of the use environment as a product.
The crack does not extend to the wiring 13 below the resist 11, and the possibility of the wiring 13 being disconnected can be reduced.

Further, the dummy wiring 16 is replaced with the regular wiring 13.
By extending the wiring in the empty direction to fill the gap or providing the regular wiring 13 and the dummy wiring 16 with a relatively large wiring width, the possibility of the wiring 13 being disconnected can be further reduced. .

(2) An opening 1 where the resist 11 is not applied to a portion where the resist 11 and the sealing material 5 are easily peeled off.
When the sealing material 5 at the injection port is bent and cut after molding, the resist 11 and the sealing material 5 are provided.
Since the stress is not concentrated on the tip of the peeling, the resist 11
Is not caused, and the possibility of disconnection of the wiring 13 can be reduced.

(3) By providing the end face of the wiring 13d in a separated / curved shape, even if a crack is formed, it becomes difficult for the crack to extend, so that the wiring 13 may be further broken. Can be lowered.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, B
The GA surface mount type package has been described as an example.
(Land Grid Array), CSP (Chip Size Package)
There is no limitation on the package structure, for example, and the same applies to other packages having a mold structure in which an insulating film is applied to the front and back surfaces of a substrate and a chip mounted on the substrate is sealed. .

Further, the package structure is applied to a package structure in which a chip is mounted on a substrate by a face-down structure, and the chip and the substrate are flip-chip bonded by a metal ball. Located along opposite sides of the
It goes without saying that the arrangement of pads on a chip, the arrangement of pads and external terminals on a substrate, and the like, such as the so-called peripheral pad arrangement structure, can be variously modified.

The same effect can be obtained when not only four chips but also one, two, three, five or more chips are mounted on a substrate.

Further, the circuit formed on the chip is SD
Not limited to RAM, DRAM, SRAM (Static Random
It is needless to say that the present invention can be applied to a case where another storage circuit such as an access memory) or a logic circuit is formed.

The substrate is not limited to a four-layer wiring structure, but may be a single-layer or two-layer, three-layer, five-layer or more multilayer wiring structure. A tape having a multilayer wiring structure in which a metal thin film of copper (Cu) or the like is adhered can also be used.

As described above, the present invention is effective for all packages that use a substrate having an insulating film adhered to the surface to mount a chip on which a predetermined circuit is formed. It can be widely applied to all semiconductor devices using a large insulating film on the surface.

[0054]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) With respect to the back surface of the substrate, dummy wirings are arranged around regular wirings to prevent disconnection of the wirings, so that the dummy wirings can hinder the progress of cracks. In addition, it is possible to prevent disconnection of regular wiring.

(2) In the above (1), the dummy wiring is provided so as to fill the gap between the regular wirings, and the regular wiring and the dummy wiring are provided with a relatively large wiring width, so that the regular wiring is further increased. Disconnection of the wiring can be prevented.

(3) With respect to the surface of the substrate, by providing an opening in which the insulating film and the sealing material are easily peeled off, where the insulating film is not attached, stress concentration at the peeled portion can be eliminated. , Cracks and subsequent disconnection of the wiring can be prevented.

(4) In the above (3), by providing the opening at the corner of the substrate in the direction in which the sealing material is injected, cracks and subsequent disconnection of the wiring can be further prevented.

(5) Regarding the wiring of the substrate, by providing the end face of the wiring in a separated / curved shape, it is possible to make it difficult for cracks to extend, and it is possible to prevent disconnection of regular wiring. Become.

(6) According to the above (1) to (5), the insulating film is made of resist, the sealing material is made of plastic resin, and a plurality of chips each having a memory circuit or the like are arranged in a matrix on the substrate. By mounting a plurality of chips in one package, it is possible to realize a semiconductor device such as a memory package capable of improving the temperature cycle property.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

2 (a) to 2 (c) show one embodiment of the present invention.
3A to 3C are a front view, a side view, and a bottom view illustrating the semiconductor device.

FIG. 3 is a diagram showing an embodiment of the present invention;
It is sectional drawing of the A 'cutting line.

FIG. 4 is a schematic plan view showing a state in which a chip is mounted on a substrate (a sealing material is omitted) in one embodiment of the present invention.

FIG. 5 is a cross-sectional view of the embodiment of FIG.
It is sectional drawing of the B 'cutting line.

FIG. 6 is a plan view showing a first-layer wiring pattern of a substrate according to an embodiment of the present invention.

FIG. 7 is a plan view showing a second-layer wiring pattern of the substrate according to the embodiment of the present invention;

FIG. 8 is a plan view showing a fourth-layer wiring pattern of the substrate according to the embodiment of the present invention.

FIG. 9 is a flowchart showing a flow of assembling a package in one embodiment of the present invention.

[Explanation of symbols]

 1, 1a-1d Chip 2 Substrate 3 Wire 4 Solder Ball 5 Sealing Material 6 Mark 7 Die Bonding Material 8 Index 9 Pad 9a Address Pad 9b Control Pad 9c Input / Output Pad 9d Power Supply Pad 10 Through Hole 10a Address Through hole 10b Control through hole 10c Input / output through hole 10d Power supply through hole 11 Resist 12 pad 12a Address pad 12b Control pad 12c Input / output pad 12d Power supply pad 13 Wiring 13a Address wiring 13b Control wiring 13c Input / output wiring 13d Power supply wiring 14 Land 14a Address land 14b Control land 14c Input / output land 14d Power supply land 15 Opening 16 Dummy wiring

Claims (8)

[Claims] 1. A chip on which a predetermined circuit is formed and a plurality of pads electrically connected to the circuit are provided, and a plurality of pads electrically connected to each pad on the chip are provided on a surface. A plurality of external terminals electrically connected to the respective pads on the front surface are provided on the back surface, and a substrate having an insulating film adhered on the front surface and the back surface is provided. It has a mold structure mounted on a substrate and sealed with a sealing material. On a back surface of the substrate, regular wiring for electrically connecting each pad on the front surface and each external terminal on the back surface is provided. When,
A semiconductor device, wherein a dummy wiring is provided around the regular wiring to prevent disconnection of the regular wiring. 2. The semiconductor device according to claim 1, wherein the dummy wiring is provided so as to fill a gap between the regular wirings. 3. The semiconductor device according to claim 1, wherein said regular wiring and said dummy wiring are provided with a relatively large wiring width. 4. A chip on which a predetermined circuit is formed and a plurality of pads electrically connected to the circuit are provided, and a plurality of pads electrically connected to each pad on the chip are provided on a surface. A plurality of external terminals electrically connected to the respective pads on the front surface are provided on the back surface, and a substrate having an insulating film adhered on the front surface and the back surface is provided. It has a mold structure mounted on a substrate and sealed with a sealing material. On the surface of the substrate, an opening that does not cover the insulating film is provided on a portion where the insulating film and the sealing material are easily peeled off. A semiconductor device, which is provided. 5. The semiconductor device according to claim 4, wherein the opening is provided at a corner of the substrate in a direction in which the sealing material is injected. 6. A chip on which a predetermined circuit is formed and a plurality of pads electrically connected to the circuit are provided, and a plurality of pads electrically connected to each pad on the chip are provided on a surface. A plurality of external terminals electrically connected to the respective pads on the front surface are provided on the back surface, and a substrate having an insulating film adhered on the front surface and the back surface is provided. A semiconductor, comprising a mold structure mounted on a substrate and sealed with a sealing material, wherein the wiring of the substrate is provided with an end face separated and curved in order to prevent disconnection of the wiring. apparatus. 7. The semiconductor device according to claim 1, wherein said insulating film is a resist,
The semiconductor device, wherein the sealing material is a plastic resin. 8. The method of claim 1, 2, 3, 4, 5, 6, or 7.
4. The semiconductor device according to claim 1, wherein the chip includes a plurality of chips each having a storage circuit formed thereon, the plurality of chips are arranged in a matrix on the substrate, and the plurality of chips are mounted in one package. A semiconductor device comprising a memory package configured as described above.