JP2001075502A - Active matrix array and liquid crystal display device using same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize TFT characteristics, to improve reliability, and to improve the throughput of an exposing device by equalizing channel directions of at least (n) channel thin-film transistors among the thin-film transistors constituting a scanning-side driving circuit and a data-side driving circuit. SOLUTION: Gate electrode 5 of (n) channel TFT of the scanning-side driving circuit 2 are arranged in a Y direction and then the channel directions are the same X direction as the channel direction of (n) channel TFTs of the data- side driving circuit 3, so that all the (n) channel TFTs have the same channel direction. Consequently, an ON current and an OFF current depending upon the length of an LDD area of an injection area for low-density impurities and variance in characteristics regarding reliability are reduced since the channel directions of the (n) channel TFTs of the scanning-side driving circuit 2, the data-side driving circuit 3, and a display electrode driving circuit which mixed before are integrated. Then the (n) channel TFTs which have stable TFT characteristics and high reliability can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix array and a liquid crystal display using the same.

[0002]

2. Description of the Related Art In recent years, there has been a strong demand for active matrix liquid crystal display devices using thin film transistors to have high definition and low cost. Thin Film Transistor (hereinafter “TFT”) using polycrystalline silicon for the active layer
Is abbreviated as T) in which conventional amorphous silicon is used for the active layer.
Since the mobility is at least two orders of magnitude higher than FT, the device size can be reduced and high definition can be achieved. In addition, since a driving circuit of a liquid crystal display device can be formed over the same substrate, attention has been paid to a technique capable of realizing cost reduction.

FIG. 3 shows a conventional active matrix array using polycrystalline silicon and n-channel TFs of a scanning side driving circuit, a data side driving circuit, and a display electrode driving circuit.
FIG. 4 is a plan view showing an example of T. In FIG. 3, 11
Denotes an active matrix array, 12 denotes a scanning side driving circuit, 13 denotes a data side driving circuit, and 14 denotes a display area.
12a, 13a, and 14a are scanning-side drive circuits 12,
FIG. 2 is an enlarged view showing a part of an n-channel TFT in a data-side driving circuit 13 and a display region 14. 15 is a gate electrode, 16 is polycrystalline silicon, 17 is an LDD mask,
18 is the length of the LDD region, 19 is the contact hole, 2
0 indicates a source / drain electrode.

In an n-channel TFT, an LDD (Lightly-Doped-Drain) structure having a lightly doped impurity-doped region between a channel region and a source / drain region reduces an electric field intensity to reduce a leak current. It is introduced for the purpose of improving reliability. Therefore, the characteristics of the TFT (electron mobility, leak current, device reliability, and the like) are greatly affected by the length 18 of the LDD region. Therefore, in order to obtain stable TFT characteristics, it is important to control the alignment accuracy of the exposure device in the LDD mask.

[0005]

Problems to be Solved by the Invention A typical L shown in FIGS.
The ON current, the OFF current, and the mobility retention ratio characteristics with respect to the DD length are shown, and a measurement system of each characteristic is shown by an equivalent circuit. The channel width and the channel length are both 10 μm.

FIG. 4A is a graph showing the ON current characteristics with respect to the LDD length. The horizontal axis indicates the LDD length. FIG.
As shown in (B), the drain current Id when the drain voltage Vd = 6V and the gate voltage Vg = 10V are applied.
Is plotted. LD which is a low concentration impurity region
As the length of the D region increases, the parasitic resistance between the source and the drain increases, and the ON current decreases.

FIG. 5A is a graph showing the OFF current characteristic with respect to the LDD length, and the horizontal axis shows the LDD length. FIG.
As shown in (B), the drain current I when a drain voltage Vd = 6 V and a gate voltage Vg = −10 V are applied.
The value of d is plotted. As the length of the LDD region increases, the parasitic resistance between the source and the drain increases, as does the ON current, and the OFF current decreases.

FIG. 6A is a graph showing mobility retention ratio characteristics with respect to LDD length. Here, the mobility retention ratio U is
As shown in FIG. 6B, 1 MHz, ± 16
V, the mobility change rate when AC stress of 50% duty is applied for a certain period of time, where U = μ / μ0, where μ0 is the initial mobility and μ is the mobility after stress is applied. .

Since the electric field strength between the source / drain and the gate is reduced by the LDD region, the mobility retention increases as the length of the LDD region increases, and a highly reliable TFT can be obtained.

As described above, TFT characteristics and reliability are L
If the length of the LDD region is too short, the OFF current increases and the reliability of the device becomes poor. If the length of the LDD region is too long, a sufficient ON current cannot be obtained. Therefore, it is necessary to optimize the design in accordance with the purpose of use, and it is important to control the alignment accuracy of the exposure apparatus that maintains the design dimensions.

In the structure of the conventional example shown in FIG. 3, in the n-channel TFT in the scanning circuit or the data driving circuit, the channel direction connecting the source electrode and the drain electrode is X.
Direction and Y direction are mixed.
In order to secure the production yield of the FT, there is a problem that high alignment accuracy is required in both the X and Y directions in the LDD mask alignment process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and has as its object to stabilize TFT characteristics, improve reliability, and improve throughput of an exposure machine.

[0013]

In order to achieve this object, an active matrix array according to the present invention has a display electrode, a gate line and a source line arranged in a matrix, and the display electrode, the gate line and the source line are arranged. In an active matrix array in which a display region connected to a display electrode driving thin film transistor and a display region driving circuit for driving the display region are provided on the same substrate, the display region driving circuit includes n-type and p-type thin film transistors. Formed in an integrated CMOS configuration,
The n-channel thin film transistor has an LDD (Lightly-Doped-Drain) structure having a low concentration impurity injection region between a channel region and a source / drain region. Of the thin film transistors forming at least n
The channel direction of the channel thin film transistor is the same.

Preferably, at least the channel direction of the n-channel thin film transistor of the thin film transistors forming the display electrode driving circuit is the same as the channel direction of the display electrode driving thin film transistor.

The liquid crystal display device of the present invention has a structure in which a liquid crystal is sandwiched between two translucent substrates, and uses, as one of the substrates, a substrate on which an active matrix array having any one of the above structures is formed.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view for explaining a first embodiment of the present invention, wherein 1 is an active matrix array, 2 is a scanning side driving circuit, and 3 is a data side driving circuit. Numeral 4 indicates a display area. 2a, 3a and 4a are enlarged views of a part of the n-channel TFT in the scanning side driving circuit 2, the data side driving circuit 3, and the display area 4, respectively. 5 is a gate electrode, 6 is polycrystalline silicon, 7 is an LDD mask, 8 is the length of the LDD region, 9 is a contact hole, and 10 is a source / drain electrode. The scanning side driving circuit 2 and the data side driving circuit 3 are generally composed of C-type integrated n-type and p-type thin film transistors.
It is composed of a MOS circuit.

In this embodiment, in the n-channel TFT of the scanning-side drive circuit 2, the gate electrode 5 is set to the Y direction, so that the channel direction is set to n of the data-side drive circuit 3.
The X direction is the same as the channel direction of the channel TFT,
All n-channel TFTs have the same channel direction.

As described above, according to this embodiment, since the channel directions of the n-channel TFTs of the scanning-side driving circuit, the data-side driving circuit, and the display electrode driving circuit, which have conventionally been mixed, are unified, O depending on the length 8 of
Variations in characteristics relating to N current, OFF current, and reliability are reduced, and an n-channel TFT having stable TFT characteristics and high reliability can be obtained. Further, according to the above configuration, in mask alignment of the exposure apparatus, only the alignment accuracy in the channel direction needs to be thoroughly managed, and the throughput of the exposure apparatus can be improved.

Although the channel direction is set to the X direction here, the same effect can be obtained when the channel direction is set to the Y direction.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating an example of a configuration of a liquid crystal display device manufactured using the active matrix array substrate having the configuration illustrated in FIG. It is a thing. 5 is a gate electrode, 6a is a channel region, 6b is an LDD region, 6c is a source / drain region, 8 is the length of the LDD region, 21 is a gate insulating layer, and 22 and 23 are interlayer insulating layers. A liquid crystal 27 is held between an active matrix substrate formed on a glass substrate 24 and a counter substrate 25 via an alignment film 26. The display electrode 28 is driven by using the thin film transistor as a switching element to charge the liquid crystal. Pixel display is performed. 29 is a black matrix, 30 is a polarizing plate, 31 is a color filter, and 32 is a transparent conductive layer.

Since this liquid crystal display uses an active matrix array substrate having the structure shown in FIG. 1, the channel directions of all n-channel TFTs are unified. LDD, which greatly affects TFT characteristics
When controlling the length of the area, it is only necessary to thoroughly control the alignment accuracy of one side in the X and Y directions when aligning the mask of the exposure apparatus, and it is possible to reliably and easily achieve improvement in the exposure apparatus throughput and image quality. And a highly reliable liquid crystal display device can be provided.

[0023]

As described above, according to the present invention, by unifying the channel direction of the n-channel TFT in the scanning-side driving circuit, the data-side driving circuit and the display electrode driving circuit, which are conventionally mixed, the TFT characteristics can be improved. LD that greatly affects
It is easy to make the length of the D region practically uniform for all the n-channel TFTs, stabilizing the TFT characteristics,
It is possible to improve the reliability.

Further, in order to control the length of the LDD region, it is only necessary to thoroughly control only the alignment accuracy in the channel direction in aligning the mask of the exposure apparatus, thereby improving the exposure apparatus throughput.

[Brief description of the drawings]

FIG. 1 is a diagram showing an outline of a configuration of an active matrix array and an n-channel TFT according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a liquid crystal display device using an active matrix array for a liquid crystal display device according to an embodiment of the present invention.

FIG. 3 is a diagram for explaining a conventional active matrix array and an n-channel TFT.

FIG. 4 illustrates a typical active matrix array O
The graph shows N current-LDD length characteristics, and FIG.
(B) is an equivalent circuit diagram showing a measurement system of the characteristic.

FIG. 5 shows a typical active matrix array O
FF current-LDD length characteristics are shown, (A) is a graph thereof,
(B) is an equivalent circuit diagram showing a measurement system of the characteristic.

FIG. 6: Typical active matrix array A
FIG. 6A shows C retention-LDD length characteristics, and FIG.
(B) is an equivalent circuit diagram showing a measurement system of the characteristic.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 active matrix array 2 scan-side drive circuit 3 data-side drive circuit 4 display area 5 gate electrode 6 polycrystalline silicon 6 a channel region 6 b low-concentration impurity implantation region (LDD region) 6 c high-concentration impurity implantation region (source and drain regions) 7) LDD mask 8 Length of LDD region 9 Contact hole 10 Source / drain electrode 10a Source electrode 10b Drain electrode 21 Gate insulating layer 22, 23 Interlayer insulating layer 24 Glass substrate 25 Counter substrate 26 Alignment film 27 Liquid crystal 28 Display electrode 29 Display electrode 29 Black Matrix 30 Polarizer 31 Color filter 32 Transparent conductive layer

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (Reference) H01L 29/78 616A F term (Reference) 2H092 GA59 JA25 JA29 KA04 KA07 KA10 MA16 MA27 NA24 PA06 5C094 AA21 AA31 BA03 BA43 CA19 DA13 EA04 EA05 EA07 EB02 ED02 ED14 ED15 FB12 FB15 5F110 BB01 BB02 BB04 CC02 EE28 GG02 GG13 HM15 NN77 NN80

Claims (3)

[Claims] A display region having a display electrode driving thin film transistor connected to the display electrode, the gate line, and the source line, wherein the display electrode, the gate line, and the source line are arranged in a matrix; In the active matrix array provided with the display region driving circuit on the same substrate, the display region driving circuit is configured by a CMOS circuit in which n-channel and p-channel thin film transistors are integrated, and the n-channel thin film transistor And an LDD (Lightly-Doped-Drain) structure having a low-concentration impurity injection region between the source region and the drain region. In the display region drive circuit, a thin film transistor forming a scan-side drive circuit and a data-side drive circuit , At least the channel of the n-channel thin film transistor An active matrix array wherein the directions of the tunnels are the same. 2. The active matrix according to claim 1, wherein at least the channel direction of the n-channel thin film transistor and the channel direction of the display electrode driving thin film transistor among the thin film transistors forming the display region driving circuit are the same. array. 3. A liquid crystal display device comprising a liquid crystal sandwiched between two light-transmitting substrates, wherein one of the substrates is one of the substrates.
A liquid crystal display device, characterized in that it is a substrate on which the active matrix array according to (1) is formed.