JP2001067816A - Disk-reproducing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce effects by local defects and reproduction failures at a training data field where reproduction clocks are corrected in phase. SOLUTION: The apparatus includes a clock-generating means 110 for generating clocks on the basis of phase information, a clock phase-correcting means 113 for correcting a phase of the clock signal from the clock-generating means 110, a first correction amount-calculating means 111 for calculating a first correction amount to correct a phase difference of the corrected clock signal corrected by the block-correcting means 113 and data recorded to a recording area, and supplying the first correction amount to the clock-correcting means 113, and a second correction amount-calculating means 112 for calculating a second correction amount. When data are not favorably reproduced by the clock signal corrected based on the first correction amount, the second correction amount is supplied to the clock-correcting means 113, so that the corrected clock signal is generated on the basis of the second correction amount.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk reproducing apparatus which generates an external clock based on a reproduction signal of phase information recorded in advance on a disk, and reproduces data using the external clock.

[0002]

2. Description of the Related Art Conventionally, in a disk medium such as a magneto-optical disk, phase information (mark) such as a clock bit and a clock mark is previously formed on a recording track. It is generated based on a signal obtained by reproducing a bit or a clock mark.

FIG. 2 is a diagram showing an example of a magneto-optical disk on which clock marks have been formed in advance. In such a disk, spiral grooves (grooves) are formed at a predetermined pitch, and data is recorded on this groove and a plane portion (land) between adjacent grooves.

As shown in FIG. 2, clock marks (FCM: Fine Clock Mark) are formed on the groove and the land so as to be radially arranged. Of these, FC on the groove
M is the same plane as the land, and FCM on the land is a depression having the same depth as the groove.

When recording or reproducing data, the FCM
Is scanned by the light beam, the intensity of the reflected beam changes in a pulse shape, and as a result, a pulse signal is generated at the output of the sensor that receives the reflected beam. The external clock is generated by a PLL (Phase Locked Loop) circuit based on the pulse signal.

However, when the clock is generated based on the external phase information as described above, the phase between the generated clock and the reproduced signal is changed due to the temperature characteristics of the disk, the recording conditions, and various variations in the characteristics of the disk recording / reproducing apparatus. Deviation may occur.

[0007] Therefore, one clock mark and one or more data areas (Segment) sandwiched between the clock marks are used as a recording unit, and the recording unit (the area managed by one address recorded in advance on the disk) is used. Record the training data synchronized with the data at the beginning of),
The phase of the external clock is corrected based on the reproduced signal of the training data.

[0008] This point will be further described. As shown in FIG. 2, a groove and a land are formed on the disk in the shape of a butterfly, and a fine clock mark (FCM) is formed on the groove and the land at a constant rotation angle. Have been. Here, a segment from one FCM to the next FCM is defined as a segment, and is defined as one recording unit. Then, one series is composed of 39 series of segments, and one block is composed of 16 series of frames. Further, an error correction code is added to the block and recorded for the purpose of correcting or detecting an error in the reproduced data.

FIG. 3 is a diagram showing the configuration of the above-mentioned block (Block). Each segment is composed of 532 DCB (Data Cloc).
k Bit). The FCM field to which the FCM is assigned is set to 12 DCB.

The first segment (Segment) in each frame
O) is for recording the address of the frame, and the address is recorded in the address field (Addr
In ess), the amplitude on one side of the groove or land in the radial direction of the disk according to the address value (wobble)
This is done by letting The segment (Se
In the address field of gment O), data recording / reproduction by the magneto-optical effect is not performed, and only address recording by the wobble is performed.

The second to 39th segments from the top (Segment 1 to Segment 38) are for recording a header and user data. An FCM field (FCM), a pre-write field (Pre-Write), a header field (Header), a data field (Data), and a post-write field (Post-Write) are allocated to the second segment (Segment 1). . Also,
The third to 39th (Segment2 to Segment38) fields include an FCM field (FCM) and a prewrite field (Pr
e-Write), a data field (Data), and a post-write field (Post-Write). The number of data clock bits in each field is as shown.

A pre-write field (Pre-Write), a header field (Header), and a data field (Dat
a) In the post-write field (Post-Write), data is recorded using the magneto-optical effect.

In each of the above fields, a pre-write (Pre-
In the (Write) field, a fixed pattern for indicating writing of data, for example, data of “0011” is recorded. The post-write (Post-Write) field is a fixed pattern for indicating the end of data, for example, data of "1100" is recorded. Further, a data field in which an error correction code is added to user data from an external source and digital modulation is performed is recorded in the data field. In the header field, a fixed pattern for confirming the start position of the data field and a fixed pattern for performing phase correction of the reproduction clock are recorded. A fixed pattern (training data) for phase correction is formed by repeating data "1100" a predetermined number of times. When the training data is reproduced at the time of reproducing the data, as shown in FIG.
A sine-wave reproduction RF signal having a B cycle is obtained. The phase correction of the reproduction clock is performed by the reproduction R of the training data.
This is performed based on the F signal.

Next, the principle of the phase correction will be described with reference to FIGS.
This will be described with reference to FIG.

The waveform signal shown in each figure is a reproduced RF signal when the above-mentioned training data is reproduced, and a circle indicates a generation timing of a reproduced clock.

FIG. 5 shows a case where the clock phase is proper, FIG. 6 shows a case where the clock phase is ahead of the reproduced RF signal, and FIG. 7 shows a case where the clock phase is delayed with respect to the reproduced RF signal. Xi-1, Xi, and Xi + 1 are reproduction RFs sampled at the clock generation timing.
This is the sample value of the signal. H Level, C Level, L Level
Is the reproduced RF at the peak, center, and bottom, respectively.
This is the expected value of the signal level.

ERR is the sample value Xi near the center and the expected value C Level in the reproduced RF signal of the training data.
(ERR = Xi-C Level), and indicates the phase shift amount between the reproduced RF signal and the clock. That is, when the clock phase is appropriate (FIG. 5), ERR = 0, and the amount of phase shift between the two is zero. On the other hand, when the clock phase is ahead of the reproduced RF signal (FIG. 6), the ER
R <0, and conversely, ERR> 0 when the clock phase is delayed with respect to the reproduced RF signal (FIG. 7).

Therefore, if ERR <0, the clock is controlled in the direction of delaying the clock, and if ERR> 0, the clock is controlled in the direction of clock advance so as to approach the state shown in FIG. You will be able to synchronize.

However, when a dropout occurs due to a local defect or the like in the training data area and the reproduced RF signal is deformed as shown in FIG. 8, ERR is disturbed accordingly. For example, FIG. 8 shows that dropout occurs when the clock phase precedes the reproduced RF signal (corresponding to FIG. 7 above). In this case, ERR <0, and the dropout occurs. The polarity will be exactly opposite to ERR when it does not occur.

Also, the reproduction RF of the training data area
If the signal characteristic becomes poor, the signal is deformed as shown in FIG. This is because the clock phase is delayed with respect to the reproduced RF signal (corresponding to FIG. 8 above) and a DC component remains, but in this case, ERR> 0 despite the phase delay, and The polarity will be exactly opposite to the original ERR.

[0021]

As described above, in the method of adjusting the phase of the external clock signal by using the training data, the phase of the external clock signal is rather deteriorated due to a defect in the recording portion of the training data or deterioration of the quality of the reproduced signal. In some cases, phase correction is performed so as to promote deviation.

For this reason, in the above-mentioned conventional technique, there is a problem that data in a data area in which phase correction is not performed cannot be satisfactorily reproduced.

Therefore, the present invention seeks to perform phase correction that can reproduce data satisfactorily.

[0024]

Means for Solving the Problems In order to solve the above problems, the present invention has the following features.

According to the first aspect of the present invention, there is provided a disk in which phase information serving as a reference for clock generation is formed on a track and training data synchronized with data is recorded at the head of each data area on the track. A disk reproducing apparatus for reproducing, comprising: a clock generating unit that generates a clock based on the phase information; a clock phase correcting unit that corrects a phase of a clock signal from the clock generating unit; A first correction amount calculating unit that calculates a first correction amount for correcting a phase shift between the corrected clock signal and the data recorded in the data area, and supplies the first correction amount to the clock correction unit; And a second correction amount calculating means for calculating
When the data is not properly reproduced by the correction clock signal corrected based on the correction amount, the second correction amount is supplied to the clock correction unit, and the correction clock signal is corrected based on the second correction amount. Is generated.

The invention according to claim 2 is characterized in that the second correction amount is a correction amount for a data area recorded before the data area.

According to a third aspect of the present invention, the disk is
A data area including at least one or more training data is recorded by forming a block to which an error correction code is added, and the disc reproducing apparatus corrects a data error based on the error correction code and An error correction means for performing detection is provided, and the quality of reproduction of the data is determined based on a result of the error correction means.

According to a fourth aspect of the present invention, the second correction amount is an average value of the first correction amount calculated based on training data in a block reproduced before the block. And

According to a fifth aspect of the present invention, the second correction amount is an integrated value obtained by leak-integrating the first correction amount calculated based on the reproduced training data.

According to a sixth aspect of the present invention, the second correction amount is an integrated value obtained by leak-integrating all or a part of the first correction amount calculated based on the training data in the block. It is characterized by.

According to a seventh aspect of the present invention, the clock generation means is constituted by a phase locked loop including a voltage controlled oscillator (VCO), and the clock correction means is controlled by the VCO.
Means is provided for giving an offset to the control voltage to the CO, and the means for giving the offset is adapted to give an offset according to the first correction amount or the second correction amount.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, reference numeral 101 denotes the magneto-optical disk described with reference to FIG. 2, which employs PR (partial response) as a signal transmission method. This is the magneto-optical disk 10
When the recording density of 1 is increased, intersymbol interference occurs between adjacent reproduced RF signals. However, a method of transmitting a signal while maintaining intersymbol interference without preventing such intersymbol interference is a partial response system. is there. Therefore, the magneto-optical disk 10
1 reproduced RF signal is a PR system [for example, PR (1,
1) Method], a reproduced waveform having inter-symbol interference is obtained according to the above method. Therefore, in order to obtain binary reproduced data of “1” and “0” from the reproduced RF signal, the sample value of the reproduced RF signal will be described later. This is achieved by performing Viterbi decoding after waveform equalization of (multi-valued) so as to approach the interference waveform.

Reference numeral 102 denotes a pickup, which optically scans the magneto-optical disk 101 to obtain a reproduced RF signal,
It outputs a tangential push-pull signal (TPP). Among them, the reproduction RF signal is a signal corresponding to the Kerr rotation angle of the reproduction beam due to the magneto-optical effect, and follows the PR (partial response) method. Further, the TPP signal is a signal corresponding to the intensity distribution in the scanning line direction in the reflected beam reflected from the disk (the intensity distribution in the longitudinal direction in the groove or the land).

Reference numeral 103 denotes a band pass filter (BPF).
Then, a low-frequency component due to eccentricity and a high-frequency component that is turned back to a low frequency in sampling described later are removed.

Reference numeral 104 denotes an AD converter which samples the output of the band-pass filter 103 by using a correction clock RCLK, which will be described later, and outputs sampled (multi-valued) data.

Numeral 105 denotes a waveform equalizer, which is composed of, for example, a transversal filter that performs filtering so as to approximate an interference waveform of the PR system. In the waveform equalizer 105, the reproduced RF signal becomes data having a known reproducible intersymbol interference characteristic.

Numeral 106 denotes a Viterbi decoding circuit which binarizes the signal based on the Viterbi algorithm which is a decoding algorithm for estimating a statistically most probable value depending on the decoding state before the data identification time by utilizing the characteristic of the waveform interference of the PR system. A decision is made and binary data is output. In addition, the Viterbi decoding circuit 106 converts “1” to “0” in the decoded data.
The timing signal TN is output at the timing of change to.

Reference numeral 107 denotes a header detection circuit which detects the position of the header field of the segment (Segment) 1 from the binary data decoded by the Viterbi decoding circuit 106 and outputs a timing signal to each signal processing unit. . The header field is detected by detecting a unique pattern (fixed pattern for confirming the start position of the data field) recorded in the header-field.

Numeral 108 denotes a data demodulation circuit which digitally demodulates data of a data field of each segment in accordance with a timing signal from the header detection circuit 107.

An error correction circuit 109 detects and corrects the error of the demodulated data by using an error correction code added to the demodulated data. Output to Note that the error correction circuit 109 also determines whether or not an error that exceeds the correction capability of the error correction code has occurred, and outputs to the controller 114 whether or not there is an error and whether or not correction is possible.

Reference numeral 110 denotes a PLL circuit, which is an FCM detection circuit 41 for detecting an FCM from a TPP signal as shown in FIG.
, A phase comparator 42 and a voltage controlled oscillator (VCO) 43
And a 532-base counter 44 for dividing the output of the VCO 43 by 532. T from pickup 102
Reproduction clock P synchronized with FCM reproduction signal in PP signal
Generate CLK. Since the TPP signal including the FCM (see FIG. 11) has a sine waveform at the timing when the reproduction light beam scans the FCM, the FCM detection circuit 41 outputs a detection signal FA which rises at the time of the zero crossing of the sine waveform. The phase of the signal FA is compared with the output signal FB from the 532-base counter 44 for dividing the output signal of the VCO 43 by 532 in the phase comparator 42. Signal FA and signal F
When a phase difference is generated between B and B, the integrated DC voltage is supplied to the VCO to adjust the phase of the output signal (reproduced clock signal) of the VCO 43. Thereby, the PLL circuit 1
Reference numeral 10 generates a reproduced clock PCLK whose phase is synchronized with the center edge of the sine waveform.

A correction amount calculation circuit 111 calculates a phase shift amount ERR from the output of the waveform equalizer 105 based on the timing signal TN from the Viterbi decoding circuit 106, and a PLL circuit according to the calculated phase shift amount ERR. A first correction amount SEL1 for performing a phase correction on the reproduction clock PCLK from 110 is output.

The calculation of the phase shift amount is executed during the period when the training data of the header field of the segment (Segment) 1 is being reproduced. The timing signal TW indicating the reproduction period of the training data is output from the header detection circuit 107 and the timing signal CW of the training data.
Change the value of Level from H Level to L Level
Is input from the Viterbi decoding circuit 106 as a timing signal TN. The sample point (Xi) corresponds to a transition point of the binary data in the Viterbi decoding circuit 106 from “1” to “0”. Therefore, E
RR is obtained at the timing when the timing signal TW indicating the reproduction period and the timing signal TN indicating the change timing of the binary data from “1” to “0” are input.

Numeral 112 denotes an averaging circuit serving as a second correction amount calculating means.
A correction amount obtained by averaging EL1 over the entire period or a predetermined period is calculated, and is output as a second correction amount SEL2 indicating a constant value in one error correction block. An error correction block start timing signal BP for updating the second correction amount SEL2 and a frame cycle timing signal FP for capturing the first correction amount SEL1 are input from a controller 114 described later.

Reference numeral 113 denotes a clock phase correction circuit, which receives a selection signal MODE from a controller to be described later and receives a first correction amount SEL1 from the correction amount calculation circuit 112 and a second correction amount output from the averaging circuit 112. Of the quantity SEL2,
Either is selected, the phase of the reproduced clock PCLK from the PLL circuit 110 is corrected, and the corrected clock RCLK is output.

A controller 114 is constituted by a microprocessor or a DSP (Digital Signal Processor) or the like, and performs overall control in the magneto-optical disk reproducing apparatus.

When there is a data reproduction request from the outside, the controller 114 instructs each unit in the disc reproducing apparatus to reproduce the requested block.
The clock phase correction circuit 113 is instructed by the selection signal MODE to obtain a correction clock RCLK phase-corrected by the first phase correction amount SEL1 calculated based on the recorded training data.

Reproduction of such data is terminated if there is no error in the block or if there is an error but the block can be corrected.

On the other hand, when the presence of an uncorrectable error is detected based on the output from the error correction circuit 109, the controller 114 instructs to reproduce (retry) the block again. At this time, the controller 1
Reference numeral 14 denotes a correction in which the phase of the reproduction clock RCLK is determined to be inappropriate due to a defect in the training data, a reproduction defect, or the like, and the selection signal MODE is inverted and corrected by the second correction amount SEL2 output from the averaging circuit 112. The clock RCLK is output.

The controller 114 outputs to the averaging circuit 112 a timing signal BP indicating the beginning of the block and a frame timing signal FP for taking in the first correction amount SEL1.

According to the embodiment shown in FIG. 1, at the timing when the disc reproducing apparatus is reproducing the training data, for example, as shown in FIG. 8 or FIG. By being done,
If the data has not been successfully reproduced, the reproduction clock PCLK is stored in the averaging circuit 112 in accordance with the second correction amount SEL2 (the average value of the correction amounts of the clocks that could be reproduced successfully before the block). , And a good clock output can be realized in the block. When the training data is not disturbed, the first correction amount SEL1 from the correction amount calculation circuit 111 is selected, and the phase of the reproduction clock PCLK is corrected according to the first correction amount SEL1 obtained for each frame. You.

FIG. 12 is a diagram showing an example of the correction amount calculation circuit 111, in which 51 is a subtractor, 52 is a gate, 53 is a level judgment circuit, 54 and 55 are gates, 56 is an up / down counter, and 57 and 58. Is a comparator for determining the match / mismatch with the values "m" and "0", respectively, and 59 is an edge detection circuit.

A subtractor 51 subtracts a DC component (C Level) from the input sample data Din and outputs a phase shift amount ERR. Reference numeral 52 denotes a gate, which receives as input a timing signal TN indicating a change point of the sampling data Din from “1” to “0” from the Viterbi decoding circuit 106 and a timing signal TW indicating a training data field from the header detection unit 107. , And outputs a timing signal indicating the position of Xi in FIGS. Reference numeral 53 denotes a level determination circuit which operates according to the timing signal output from the gate 52, and determines whether the phase shift amount ERR is within a predetermined range (that is, within a range that does not affect data reproduction), or It is determined whether it is above or below the range.

For example, the A / D converter 104 has 8-bit precision, and the RF signal has an effective range of 8 bits of the A / D converter 104.
Assuming that the input is at about 0% and the amplitude ratio of nT: 2T (n ≧ 3) is about 5: 4 (80%), the predetermined range within which the correction clock falls within ± 10 degrees is | ERR |
≦ 16.

The operation signal is output to the gates 54 and 55 only when the phase shift amount ERR is out of the predetermined range. At this time, if the ERR is smaller than the predetermined range, an up command (UP) is issued to the up / down counter 56 via the gate 54, and if the ERR is larger than the predetermined range, the up / down counter is supplied via the gate 55. 56
Issue a down command (DOWN). 54 is a gate,
Up command from the level judgment circuit 51 and the comparator 58
When the signal from is at a high level (mismatch, <m), an up command is output to the up / down counter 56.

Reference numeral 55 denotes a gate, which is a down command from the level judgment circuit 51 and an up / down counter 5 when the signal from the comparator 57 is at a high level (mismatch,> 0).
A down command is output to 6.

Reference numerals 57 and 58 denote comparators which output the results of comparison between the value "m", which is the upper limit of the correction amount that can be corrected by the clock phase correction circuit 113, and the value "0", which is the lower limit. Each comparator functions as a limiter for preventing the value of the up / down counter 56 from deviating from the range of 0 to m, and when the value of the counter 56 reaches the value “m” or “0”. Outputs control signal. Reference numeral 56 denotes an up / down counter which counts up or down by 1 when an operation command signal is input from the gate 52 and an up command or a down command is input from the level determination circuit 53. A certain first
Is output as the correction amount SEL1.

An edge detection circuit 59 generates a timing signal preceding the timing signal TW and supplies it to the INIT terminal of the up / down counter 56. The up / down counter 56 includes an edge detection circuit 59 at the INIT terminal.
Is input, the initial value (an integer value near m / 2)
Is set. That is, each time a training data field is detected, an initial value is set.

The operation will be described with reference to FIG. 13 showing a change in the first correction amount and a change in ERR.

When the timing signal from the edge detection circuit 59 is supplied to the INIT terminal of the up / down counter 56, an initial value (an integer near m / 2) is set as the first correction amount SEL1. Then, the ERR level is determined according to the timing signal indicating the position of Xi in FIGS. 5 to 7, and the count value of the up / down counter 56 is changed. As is clear from the figure, in this case,
As the first correction amount SEL1 decreases, the ERR converges to zero.

FIG. 12 shows an example of a correction amount calculation circuit using a counter. Instead, a configuration using a loop filter, a phase determination based on an average phase shift amount, or the like is adopted. Is also possible. Further, an up / down counter that operates cyclically for a clock period (clock phase of 360 degrees) as a phase correction amount may be employed instead of the up / down counter 55 in FIG. In this case, the gates 54 and 55 and the comparator 5
The limiter function realized by 7, 58 becomes unnecessary.

FIG. 14 shows an example of an averaging circuit, in which 60 is a normalizing circuit, and 61 and 62 are (1-
a) times, a times (a≪1) multiplier, 63 is an adder, 6
Reference numerals 4 and 65 are flip-flops. Such a multiplier 6
1, 62, an adder 63, and a flip-flop 63 constitute a leak integrating circuit, and the normalized first correction amount SE
Average L1.

The input first correction amount SEL1 is normalized by a normalization circuit 60 to a correction amount for one clock cycle. For example, if the clock frequency is 25 MHz
Then, since one cycle is 40 nsec (360 degrees), a correction value exceeding 40 nsec can be treated as a correction within 40 nsec. That is, 50 nsec
(405 degree) delay is 10 nsec delay (45 degree)
Becomes

The flip-flop 65 has a second correction amount S
This is a flip-flop that holds EL2 for one block period, and operates with a block timing signal BP.

FIG. 15 shows another example of the configuration of the averaging circuit, in which 70 is a normalizing circuit, 71 is an adder, 72 is a flip-flop with a clear function, and 73 is a bit shifted down by 4 bits. The shift circuits 74 and 75 are flip-flops. The timing signal BP1 is a timing signal generated based on the result of the error correction circuit 109, and is input from the controller 114 with a predetermined time delay from the block timing signal BP. The normalization circuit 70 performs the same processing as the normalization circuit 60 in FIG. This circuit calculates an average value of all the first phase correction amounts SEL1 in one block, that is, an average value of the 16 first correction amounts SEL1, and sets the average value as a second correction amount SEL2. It is initialized to “0” by the block start timing signal BP input to the clear terminal CL of the flip-flop 71. The adder 71 adds the value held in the flip-flop and the first correction amount SEL1 obtained for each frame. The addition result is held by updating the flip-flop 72 according to the timing signal FP for each frame, and cumulative addition is performed. The result of the cumulative addition is shifted downward by 4 bits in the bit shift circuit 73, that is, divided by 1/16. When 16 frames are cumulatively added, the flip-flop 74 holds the 1/16 accumulated value, that is, the block average value, in accordance with the timing signal BP. Further, the output of the flip-flop 74 is held by the flip-flop 75 for one block period in accordance with the timing pulse BP1 having a block cycle delayed by a predetermined time from the timing signal BP, and is output as the second correction amount SEL2.

When the error correction circuit 109 determines that there is an error and that correction is impossible, the timing signal BP1 is not generated.

FIG. 16 shows a specific configuration example of the clock phase correction circuit 113. In the figure, reference numeral 81 denotes a switch, which is a selection signal MOD from the controller 114.
E, the first correction amount SEL1 and the second correction amount SE
One of L2 is selected and output to a selector 82 described later as correction control data. Reference numeral 82 denotes a selector, and a delay clock CL according to the correction amount SEL from the switch 81.
One of K0-CLKm is selected and the correction clock RC
Output as LK. Here, the correction control data is n
(0 ≦ n ≦ m), the delay clock CLK0
CLKn will be selected from .about.CLKm. 8
Reference numeral 3 denotes a delay line, which receives the reproduced clock PCLK as input, and has m + 1 types of delay clocks CLK0 to CLK0, which are delay amounts at equal intervals.
CLKm is output.

The phase correction circuit 113 can be variously modified in addition to the configuration shown in FIG. For example, it is also possible to adopt a configuration in which the second PLL is multiplied based on the reproduction clock PCLK and the phase is adjusted according to the first correction amount SEL1 or the second correction amount SEL2. Also, PL
It is also possible to adjust the phase by adding an offset to the control voltage of the VCO in L110.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and various other modifications are possible.

More specifically, the averaging circuit 112 shown in FIG.
Instead, the second correction amount may be determined by the controller. An example of such a configuration is shown in FIG. FIG.
, A controller 115 has the same function as the controller 114 in FIG. 1 and additionally incorporates an algorithm for determining the second correction amount SEL2. By executing the determination of the second correction amount SEL2 by the controller 115, it is possible to determine the second correction amount SEL2 on a more complicated basis. For example, the average correction amount of the first correction amount SEL1 in a frame with good data reproduction in the same block within a block with an error and that cannot be corrected, and the first correction amount SEL1 in the previous and next frames in a frame with good data reproduction. , The first correction amount SEL1 of the immediately preceding frame, a predetermined fixed value, or the like.

Here, good data reproduction means, for example,
It is also conceivable that the determination is made based on the reproduction rate of the remaining header, prewrite, postwrite, etc. after completion of the phase correction process, which is a known pattern recorded in each segment constituting the frame and synchronized with the data.

The waveform equalizer 105 is connected to the AD converter 10
4, and may be equalized to the PR characteristic by analog waveform equalization.

Although the PR (1, 1) type magneto-optical disk has been described as an example, the present invention is also applied to a magneto-optical disk of another data transmission type and a recording / reproducing apparatus of a phase change type disk. be able to.

[0075]

As described above, according to the present invention, even if proper phase correction is not performed due to a local defect or defective reproduction of the disc in the area where the training data is recorded, the data can be reproduced with a proper clock. Playback can be performed.

When a defect or defective reproduction occurs,
Since the correction amount for the data area reproduced before that is used, variation in clock correction is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration example of a magneto-optical disk.

FIG. 3 is a diagram showing an example of a data configuration in a magneto-optical disk.

FIG. 4 is a diagram showing a reproduced RF signal waveform of training data.

FIG. 5 is a waveform chart for explaining the principle of detecting a phase shift;
FIG. 3 is a diagram illustrating a state in which a reproduction RF signal and a clock are synchronized.

FIG. 6 is a waveform chart for explaining the principle of detecting a phase shift;
FIG. 4 is a diagram illustrating a state where a reproduction RF signal is ahead of a clock signal.

FIG. 7 is a waveform chart for explaining the principle of detecting a phase shift;
FIG. 9 is a diagram showing a state where a reproduction RF signal is being sent more than a clock signal.

FIG. 8 is a waveform chart for explaining the principle of detecting a phase shift;
FIG. 7 is a diagram illustrating a state when a defect occurs in a training data area.

FIG. 9 is a waveform diagram for explaining the principle of detecting a phase shift;
FIG. 6 is a diagram illustrating an example of a state when reproduction RF signal characteristics are defective.

FIG. 10 is a diagram illustrating a configuration example of a clock generation circuit.

FIG. 11 is a diagram showing a reproduction waveform of a clock mark and a signal waveform of each part of a clock generation circuit.

FIG. 12 is a diagram illustrating an example of a correction amount calculation circuit according to the present invention.

FIG. 13 is a diagram for explaining a relationship between a first correction value and ERR.

FIG. 14 is a diagram illustrating an example of an averaging circuit according to the present invention.

FIG. 15 is a diagram showing another example of the averaging circuit according to the present invention.

FIG. 16 is a diagram illustrating an example of a phase correction circuit according to the present invention.

FIG. 17 is a block diagram showing another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 101 magneto-optical disk 102 pickup 103 waveform equalizer 104 AD converter 106 Viterbi decoding circuit 107 header detection circuit 108 data demodulation circuit 109 error correction circuit 110 PLL circuit 111 correction amount calculation circuit 112 averaging circuit 113 clock phase correction circuit 114 controller

Claims (7)

[Claims] 1. A disc reproducing apparatus for reproducing a disc in which phase information serving as a reference for clock generation is formed on a track and training data synchronized with the data is recorded at the beginning of each data area on the track. Clock generating means for generating a clock based on the phase information; clock phase correcting means for correcting the phase of the clock signal from the clock generating means; and a corrected clock signal corrected by the clock correcting means; A first correction amount calculating unit that calculates a first correction amount for correcting a phase shift from data recorded in the data area and supplies the first correction amount to the clock correction unit; and a second correction amount calculating unit that calculates a second correction amount. Providing a correction amount calculating means,
When the data is not properly reproduced by the correction clock signal corrected based on the first correction amount, the second correction amount is supplied to the clock correction unit, and the second correction amount is supplied to the clock correction unit.
A disk reproducing apparatus for generating a correction clock signal based on the correction amount of the data. 2. The disk reproducing apparatus according to claim 1, wherein the second correction amount is a correction amount for a data area recorded before the data area. 3. The disc reproducing apparatus according to claim 1, wherein the disc is formed by forming a block in which an error correction code is added to a data area including at least one or more of the training data. 2. The disk reproducing apparatus according to claim 1, further comprising: an error correction unit configured to correct and detect a data error based on a code, and determining whether the data is reproduced properly based on a result of the error correction unit. . 4. The apparatus according to claim 3, wherein the second correction amount is an average value of the first correction amounts calculated based on training data in a block reproduced before the block. Disk playback device. 5. The disk reproducing apparatus according to claim 3, wherein the second correction amount is an integrated value obtained by leak-integrating the first correction amount calculated based on the reproduced training data. . 6. The apparatus according to claim 1, wherein the second correction amount is an integrated value obtained by leak-integrating all or a part of the first correction amount calculated based on training data in the block. 3. The disc reproducing apparatus according to 3. 7. The clock generating means is constituted by a phase locked loop including a voltage controlled oscillator (VCO), and the clock correcting means includes means for giving an offset to a control voltage to the VCO. 7. The disk reproducing apparatus according to claim 1, wherein the giving means gives an offset according to the first correction amount or the second correction amount.