JP2001053281A - Soi semiconductor device and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a full depleted SOI semiconductor device provided with a back gate electrode, where a semiconductor layer (SOI layer) just under a gate electrode is small in thickness, and other semiconductor layers other than the SOI layer are large in thickness and low in resistance. SOLUTION: An SOI semiconductor device consists of an interlayer film 18 formed on a support substrate 20, an insulating layer 14 formed on the interlayer film 18, a semiconductor layer 10A formed on the surface of the insulating layer 14 and surrounded with the insulating layer 14, source/drain regions 34 and a channel forming region 35 formed in the semiconductor layer 10A, a gate electrode 31 formed on the channel forming region 35 through the intermediary of a gate insulating film 30, a groove 15 extended inside the semiconductor layer 10A penetrating through the insulating layer 14, a back gate electrode 17 which is formed of conductive material and filled in the groove 15, and an oxide film 16 formed between the back gate electrode 17 and the semiconductor layer 10A.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art An L-type MOS transistor is used.
With the increasing integration and performance of SI, SOI (Semiconduc
Attention has been focused on SOI semiconductor devices having a (tor-On-Isolator) structure. This SOI semiconductor device is formed in a semiconductor layer (also referred to as an SOI layer) formed on an insulating layer. Therefore, complete element isolation can be achieved, and furthermore, occurrence of soft errors and latch-up phenomena can be suppressed, and high reliability can be obtained even in highly integrated LSI. In addition, since the junction capacitance of the source / drain regions can be reduced, charging / discharging accompanying switching is reduced, which is advantageous for high speed and low power consumption.

[0003] The SOI semiconductor device generally has two operation modes. In one operation mode, a depletion layer induced in a channel formation region (also referred to as a body portion) immediately below a gate electrode reaches an interface between an insulating layer and an SOI layer during operation of an SOI semiconductor device. The other operation mode is a partial depletion type in which the depletion layer does not reach the interface between the insulating layer and the SOI layer, and a neutral region remains.

In a fully depleted SOI semiconductor device,
During operation, the thickness of the depletion layer immediately below the gate electrode is limited by the insulating layer, the amount of depletion charge is significantly reduced as compared with the partially depleted SOI semiconductor device, and the amount of mobile charge that contributes to the drain current increases instead. As a result, there is an advantage that a steep subthreshold characteristic (S value) can be obtained.
Further, since a steep sub-threshold characteristic is obtained, the threshold voltage can be reduced while suppressing the off-leak current, and the drain current can be ensured even at a low operating voltage. That is, it is possible to manufacture a semiconductor device which operates with 1 volt or less (threshold voltage is 0.3 volt or less) and consumes very little power.

However, when fabricating a fully depleted SOI type semiconductor device, the SOI
Since the thickness of the layers must be very thin and uniform, the difficulty of the manufacturing process increases. In particular,
The thickness of the SOI layer for manufacturing a fully depleted SOI semiconductor device of the 0.13 μm generation or later needs to be about 20 nm.

Therefore, in the future, when manufacturing an LSI composed of a fully depleted SOI semiconductor device which is highly integrated, has high performance, and consumes very low power, a very thin SOI layer (for example, , 20 nm or less)
It is extremely important to establish a process that can form a film with good quality and good controllability.

As a method of forming an SOI layer, SIMOX is used.
(Separation by IMplanted OXygen) method and a substrate bonding method. The SIMOX method is a method in which high-concentration oxygen ions are deeply implanted into a semiconductor substrate and then heat-treated to form a buried oxide film inside the semiconductor substrate. The portion of the semiconductor substrate above the buried oxide film corresponds to the SOI layer. This SI
The MOX method is excellent in the uniformity of the thickness of the SOI layer, but has a problem in particular in the crystallinity of the SOI layer near the buried oxide film. Therefore, when the SIMOX method is used, a fully-depleted SOI semiconductor device having high reliability is required to have a very thin S
It is difficult to form an OI layer.

On the other hand, after the semiconductor substrate and the supporting substrate are bonded via an insulating layer, the semiconductor substrate is ground and polished from the back surface, and the remaining semiconductor layer of the semiconductor substrate is formed on the insulating layer.
In the substrate bonding method left as an OI layer, the crystallinity of the SOI layer near the insulating layer is good. However, after laminating the semiconductor substrate and the support substrate via the insulating layer, the semiconductor substrate must be ground and polished from the back surface, and it is difficult to obtain a thin SOI layer having a uniform film thickness.

As one of the substrate bonding methods, there is a substrate bonding method in which uniformity of the film thickness of the SOI layer can be achieved, and an element isolation region is also formed. A method for manufacturing an SOI semiconductor device based on the substrate bonding method will be described below with reference to FIGS. 6 to 8 which are schematic partial cross-sectional views of a semiconductor substrate and the like. The method for forming the element isolation region is as follows.
The LOCOS method or the trench isolation method may be used, but the method described below employs the trench isolation method.

[Step-10] First, the surface of the semiconductor substrate 10 is formed on the surface of the semiconductor substrate 10 based on a lithography technique and an etching technique.
A convex portion 11 and a concave portion (trench portion) 12 are formed (FIG. 6).
(A)).

[Step-20] Next, the semiconductor substrate 1 on which the convex portions 11 and the concave portions 12 are formed based on, for example, the CVD method.
The insulating layer 14 is formed on the surface of the insulating layer 14 and the surface of the insulating layer 14 is planarized (see FIG. 6B). Next, the semiconductor substrate 1
0 and the support substrate 20 are bonded together via the insulating layer 14 (see FIG. 7A).

[Step-30] Thereafter, the semiconductor substrate 10 is ground from the back surface, and the semiconductor substrate 10 is selectively polished from the back surface using the insulating layer 14 as a polishing stop layer. Layer (SOI layer) 10
A is obtained (see FIG. 7B). The protrusion 11 provided on the surface of the semiconductor substrate 10 becomes the semiconductor layer 10A. Also,
The recess 12 and the insulating layer 14 embedded in the recess 12
It functions as an element isolation region.

[Step-40] Next, based on the conventional method, the semiconductor layer 10A is formed above the channel forming region in the semiconductor layer 10A.
After the gate electrode 31 is formed with the gate insulating film 30 interposed therebetween, the gate sidewall 32 is formed on the side wall of the gate electrode 31.
Then, a source / drain region 34 and a channel formation region 35 interposed between the source / drain regions 34 are formed in the semiconductor layer (SOI layer) 10A (FIG. 8).
reference).

After the above [Step-10], the surface of the semiconductor substrate 10 is oxidized to form an oxide film (backside gate insulating film).
7 may be formed. FIG. 9A is a schematic partial cross-sectional view of a semiconductor device obtained by such a process. By providing the back gate electrode 17, SO
This is advantageous for controlling the threshold voltage and sub-threshold characteristics during operation of the I-type semiconductor device, and for suppressing the short channel effect.

As described above, in order to manufacture a fully depleted SOI semiconductor device, which will be important in the future, with good controllability, an SOI layer having good film quality is formed thinly and uniformly by selective polishing based on a substrate bonding method. In addition, a technique for providing a back gate electrode is promising.

[0016]

In order to manufacture a fully depleted SOI semiconductor device, it is necessary to form a thin SOI layer having a thickness of, for example, about 20 nm as described above. However, when the SOI layer is thinned in this way, not only the channel formation region 35 below the gate electrode 31 but also the source / drain region 34 and the extension region 33 (the region of the semiconductor layer below the gate sidewall 32). As a result, the sheet resistance increases. Therefore, there arises a problem that the parasitic resistance at the time of operation of the fully depleted SOI semiconductor device is increased, and the driving capability is reduced.

Although the resistance can be reduced by silicidizing the source / drain regions 34, if the thickness of the SOI layer 10A is less than 20 nm, S
It is difficult to form a uniform, low-resistance silicide layer thinner than the OI layer 10A. Further, when the entire source / drain region 34 is silicided, the contact resistance between the silicide layer and the extension region 33 increases, and the problem also arises that the driving capability of the fully-depleted SOI semiconductor device decreases.

As a solution to such a problem, a source / drain region 34 is formed based on a selective epitaxial growth technique.
A silicon layer on top of the source / drain region 34
A technology for increasing the thickness of the semiconductor device (elevated source / drain technology) has been studied, but a sufficiently stable process has not yet been established. Alternatively, by forming the entire SOI layer thicker, selectively oxidizing only the SOI layer portion in the channel formation expected region, and etching the oxidized portion, the SOI in the channel formation expected region is etched.
A technique of reducing the thickness of only the I layer (reset channel technique) is also being studied. FIG. 9B is a schematic partial cross-sectional view of a semiconductor device obtained by this technique. However, according to this technique, not only the number of steps is increased, but also a stress is generated at the time of selective oxidation in a region of the SOI layer 10A where a gate insulating film requiring high reliability is to be formed,
As a result, there is a problem that the leak current between the source / drain regions increases.

Therefore, an object of the present invention is to provide a semiconductor device (SOI layer) directly under a gate electrode having a small thickness and a thin portion of the other semiconductor layers without causing a problem such as generation of leakage current due to stress. It is an object of the present invention to provide a fully depleted SOI semiconductor device having a large thickness, low resistance, and a back gate electrode, and a method for manufacturing the same.

[0020]

In order to achieve the above object, a method of manufacturing an SOI semiconductor device according to the present invention comprises:
Forming a convex portion on the surface of the semiconductor substrate; (b) forming an insulating layer on the surface of the semiconductor substrate having the convex portion formed thereon; and (c) forming the insulating layer on the semiconductor substrate by penetrating the insulating layer. A step of forming a groove having a depth D (where D <H) extending from the top surface of the protrusion to the inside of the protrusion (height is assumed to be H); and (d) exposing in the groove. A step of oxidizing the surface of the portion of the semiconductor substrate, and (e) filling the groove with a conductive material,
Forming a back gate electrode, (f) forming an interlayer film on the entire surface, (g) bonding a semiconductor substrate and a supporting substrate via the interlayer film, and (h) stopping the polishing of the insulating layer. Selectively polishing the semiconductor substrate from the back surface as a layer to obtain a semiconductor layer composed of the remaining portion of the semiconductor substrate and surrounded by the insulating layer; Forming a gate electrode through a film, then forming source / drain regions in the semiconductor layer, and forming a channel forming region (body portion) sandwiched between the source / drain regions. It is characterized by.

In the method of manufacturing an SOI semiconductor device according to the present invention, the step (b) includes, after forming an insulating layer on the surface of the semiconductor substrate having the convex portions formed thereon, for example, by a chemical / mechanical polishing method ( It is preferable to include a step of flattening the surface of the insulating layer based on the CMP method). Step (d)
Forming a sacrificial oxide film by oxidizing the surface of the portion of the semiconductor substrate exposed in the trench before oxidizing the surface of the portion of the semiconductor substrate exposed in the trench; and removing the sacrificial oxide film. It is preferable that the oxide film (a back gate insulating film) be improved in quality of the obtained oxide film (rear gate insulating film). In the step (d), as a method for oxidizing the surface of the portion of the semiconductor substrate exposed in the groove, a thermal oxidation method, or a combination of the thermal oxidation method and the thermal nitridation method can be mentioned. In the step (h), a chemical / mechanical polishing method (CMP
Method).

The SO according to the present invention for achieving the above object.
The I-type semiconductor device includes (a) an interlayer film formed on a support substrate, (b) an insulating layer formed on the interlayer film, and (c) formed on a surface of the insulating layer and surrounded by the insulating layer. A semiconductor layer, a (d) source / drain region formed in the semiconductor layer, a channel forming region sandwiched between the source / drain regions, and (e) a gate insulating film on the channel forming region. An SOI type semiconductor device comprising: a gate electrode formed; (f) a groove penetrating through the insulating layer and extending to the inside of the semiconductor layer; and (g) a back gate made of a conductive material embedded in the groove. It further comprises: an electrode; and (h) an oxide film formed between the back gate electrode and the semiconductor layer.

In the SOI semiconductor device or the method of manufacturing the same according to the present invention, the groove extends from the convex portion or the semiconductor layer provided on the semiconductor substrate to a part of the insulating layer adjacent to the convex portion or the semiconductor layer. Accordingly, a structure in which the back gate electrode extends from below the channel formation region to a part of the insulating layer can be obtained. It is desirable that the width of the groove is substantially equal to the width of the channel forming region (body portion).

In the SOI semiconductor device of the present invention or the method of manufacturing the same, various semiconductor substrates such as a silicon semiconductor substrate can be used as the semiconductor substrate and the supporting substrate. A substrate on which a layer or a Si—Ge layer is formed can also be used. The semiconductor layer (SOI layer) corresponds to the rest of various semiconductor substrates such as a silicon semiconductor substrate. SiO ₂ , S
Silicon-based insulating materials such as iN, SiON, and SiOF can be given. The insulating layer may have a laminated structure. As a material constituting the interlayer film, SiO ₂ , Si
Silicon-based insulating materials such as N, SiON, and SiOF can be used. The interlayer film may have a laminated structure of a film made of these insulating materials and a polysilicon film. As a gate insulating film or an oxide film (back gate insulating film) formed between the back gate electrode and the semiconductor layer, a silicon oxide film (SiO ₂ ), a laminated structure of a silicon oxide film and a silicon nitride film are exemplified. be able to.

As a conductive material forming the back gate electrode or a material forming the gate electrode, boron (B),
Polysilicon containing impurities such as arsenic (As) and phosphorus (P), tungsten (W), tantalum (Ta),
Refractory metal materials such as titanium (Ti), WSi ₂ , M
metal silicides such as oSi ₂ , TiSi ₂ , CoSi ₂ , and NiSi; metal nitrides such as WN, TaN, and TiN;
Alternatively, these laminates can be mentioned. The method of filling the groove with a conductive material depends on the conductive material to be used, and examples thereof include a CVD method and a sputtering method.

The method for forming the element isolation region may be the LOCOS method or the trench isolation method. In consideration of the problem of stress occurring in portions, in order to manufacture a highly integrated LSI, it is desirable to use a trench isolation method as a method for forming an element isolation region. However, in the present invention, the method for forming the element isolation region is not limited to the trench isolation method.

The method for manufacturing an SOI semiconductor device according to the present invention may include a step of silicidizing the surface of the source / drain region subsequent to the step (i). In this case, although not limited, a metal layer is formed on the entire surface,
By performing a heat treatment, the atoms constituting the semiconductor layer are reacted with the atoms constituting the metal layer to form a metal silicide layer on the surface of the source / drain region, and thereafter, the unreacted metal layer is removed. It is preferable to form a metal silicide layer. In the SOI semiconductor device of the present invention, it is preferable that a metal silicide layer is formed on the surface of the source / drain region in order to reduce the resistance. The metal layer may be made of any metal as long as it can form a metal silicide layer. For example, in the formation of CoSi ₂ , NiSi, PtSi, etc., during the reaction between these metals and Si, Since these metals mainly move into the semiconductor layer, their Co, N
It is desirable to be made of a metal such as i or Pt.

The operation mode of the SOI semiconductor device manufactured by the method of manufacturing the SOI semiconductor device of the present invention or the SOI semiconductor device of the present invention is induced in the channel forming region (body portion) immediately below the gate electrode. The depletion layer is a complete depletion type that reaches the interface between the insulating layer and the semiconductor layer (SOI layer).

In the present invention, since the groove is formed to reach the inside of the projection formed on the semiconductor substrate, only the thickness of the channel forming region (body portion) is small, and the thickness of the source / drain region is large. Structure can be obtained.

[0030]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, an SOI semiconductor device according to the present invention and a method for manufacturing the same according to the embodiments of the present invention (hereinafter abbreviated as embodiments) will be described below.

FIG. 4B is a schematic partial cross-sectional view of a fully depleted SOI semiconductor device according to the present invention. This SO
The I-type semiconductor device is formed on the surface of (a) the interlayer film 18 formed on the support substrate 20, (b) the insulating layer 14 formed on the interlayer film 18, and (c) the insulating layer 14; Insulation layer 1
4, (d) a source / drain region 34 formed in the semiconductor layer 10A, a channel formation region 35 interposed between the source / drain regions 34, and (e) a channel formation. A gate electrode 31 formed on the region 35 via the gate insulating film 30;
(F) a groove 15 penetrating through the insulating layer 14 and extending to the inside of the semiconductor layer 10A; (g) a back gate electrode 17 made of a conductive material embedded in the groove 15; The semiconductor device further includes an oxide film 16 formed between the semiconductor layer 10A. Reference numeral 11 indicates a convex portion (corresponding to the semiconductor layer 10A) provided on the semiconductor substrate, reference numeral 12 indicates a concave portion (trench portion), reference numeral 13 indicates a silicon oxide film, and reference numeral 32. Indicates a gate sidewall provided on a side wall of the gate electrode 31, reference numeral 33 indicates an extension region, and reference numeral 36 indicates a metal silicide layer.

Hereinafter, a method of manufacturing the SOI semiconductor device shown in FIG. 4B will be described with reference to FIGS.

[Step-100] First, a silicon oxide film 13 having a thickness of about 10 nm is formed on the surface of a semiconductor substrate 10 composed of a silicon semiconductor substrate by a thermal oxidation method. 10
A convex portion 11 and a concave portion (trench portion) 12 are formed on the surface of the substrate. The thickness of the finally formed semiconductor layer (SOI layer) is determined by the depth of the concave portion 12. The depth of the recess 12 from the surface of the silicon oxide film 13 is set to 60 nm.
That is, the semiconductor substrate 1 after the formation of the silicon oxide film 13
0 is etched to a depth of 50 nm to form the protrusions 11 and the recesses 12. Table 1 below shows the etching conditions of the semiconductor substrate 10. After that, a silicon oxide film 13 having a thickness of 10 nm is formed on the side and bottom surfaces of the concave portion 12 by a thermal oxidation method. This state is shown in FIG.
In addition, the height (H) of the convex portion 11 formed on the semiconductor substrate 10
Is about 60 nm. Here, the height (H) of the protrusion 11 formed on the semiconductor substrate 10 is determined based on the interface between the silicon oxide film 13 formed on the bottom of the recess 12 and the semiconductor substrate 10. This is the height of the interface between the silicon oxide film 13 formed on the top surface and the projection 11.

[Table 1] Working gas: C ₄ F ₈ / O ₂ / Ar = 5/4/100 sccm Pressure: 5.3 Pa RF power: 400 W Substrate temperature: 10 ° C.

[Step-110] Next, an insulating layer 14 made of SiO ₂ and having a thickness of 0.4 μm is formed on the surface of the semiconductor substrate 10 on which the convex portions 11 and the concave portions 12 are formed based on the LP-CVD method. After that, the insulating layer 14 is subjected to an annealing process. Next, the surface of the insulating layer 14 is planarized based on the CMP method (see FIG. 1B). Convex part 11 after flattening process
The thickness of the insulating layer 14 above is 0.3 μm. Insulation layer 1
Table 2, Table 3, and Table 4 below respectively illustrate the formation conditions based on the LP-CVD method, the annealing conditions of the insulating layer 14, and the planarization processing conditions of the insulating layer 14 based on the CMP method.

[Table 2] Conditions for forming insulating layer 14 based on LP-CVD method Gas used: SiH ₄ / O ₂ / N ₂ = 250/250/100 sccm Pressure: 13.3 Pa Substrate heating temperature: 520 ° C.

[Table 3] Annealing condition of insulating layer 14 Annealing temperature: 1000 ° C Annealing time: 30 minutes

[Table 4] Flattening treatment condition of insulating layer 14 based on CMP method Polishing pressure: 300 g / cm ² Number of rotations: Surface plate: 30 rpm Polishing head: 30 rpm Polishing pad: Product name IC-1000 Slurry used: NH ₄ OH (containing fumed silica) 100 cm ³ / min Temperature: 25-30 ° C

[Step-120] Thereafter, a groove portion 15 penetrating through the insulating layer 14 and extending to the inside of the convex portion 11 formed on the semiconductor substrate 10 is formed. Specifically, based on the lithography technique and the dry etching technique, a groove is first formed in the insulating layer 14 using the protrusion 11 as an etching stopper, and then a groove is further formed in the protrusion 11.
In the formation of the groove in the protrusion 11, since there is no etching stopper, the depth (D) of the groove from the top surface of the protrusion 11 is defined by controlling the etching time. The etching conditions of the insulating layer 14 and the etching conditions of the protrusion 11 are illustrated in Tables 5 and 6 below. still,
The depth (D) of the groove from the top surface of the protrusion 11 is set to 20 nm. Here, the depth (D) of the groove formed in the protrusion 11
Is the depth of the groove with reference to the interface between the silicon oxide film 13 formed on the top surface of the protrusion 11 and the protrusion 11. Thus, the state shown in FIG. 1C can be obtained.

[Table 5] Etching conditions for insulating layer 14 Gas used: C ₄ F ₈ / CO / Ar = 10/100/200 sccm Pressure: 6 Pa RF power: 1.6 kW Substrate temperature: 20 ° C.

[Table 6] Etching conditions for convex portion 11 Gas used: CF ₄ / Ar = 100/900 sccm Pressure: 105 Pa RF power: 600 kW Substrate temperature: 10 ° C. Etching time: 12 seconds

[Step-130] Next, the surface of the portion of the semiconductor substrate 10 exposed in the groove 15 (part of the top surface of the projection 11) is oxidized (see FIG. 2A). Specifically, first, in order to remove a damaged portion in the convex portion 11,
After the surface of the portion of the semiconductor substrate exposed in the groove 15 is oxidized to form a sacrificial oxide film having a thickness of 10 nm, the sacrificial oxide film is removed by dilute hydrofluoric acid treatment. Thereafter, the surface of the portion of the semiconductor substrate 10 exposed in the groove 15 (part of the top surface of the convex portion 11) is oxidized based on a thermal oxidation method to have a thickness of 10 n.
An oxide film (back gate insulating film) 16 of m is formed. The height (T) of the projection 11 below the groove 16 is about 20 nm. Here, the height (T) of the convex portion 11 below the groove portion 16 refers to the oxide film 16 formed on the bottom of the concave portion 12 with respect to the interface between the silicon oxide film 13 and the semiconductor substrate 10.
The height (T) of the convex portion 11 below the groove 16 corresponds to the thickness of a channel forming region (body portion) to be formed later.

[Step-140] Next, the inside of the groove 15 is filled with a conductive material to form the back gate electrode 17 (FIG. 2).
(B)). Specifically, a polysilicon layer is deposited on the insulating layer 14 including the inside of the groove 15 by an LP-CVD method, and then the polysilicon layer on the insulating layer 14 is removed by an etch-back method. After that, an impurity such as boron (B) or phosphorus (P) is implanted into the polysilicon layer buried in the trench 15 by an ion implantation method, and the impurity is activated and annealed. The conditions for forming the polysilicon layer and the conditions for etching back the polysilicon layer are shown in Tables 7 and 8 below. Further, the arrangement relationship between the back gate electrode 17 and the protrusion 11 (finally constituting the semiconductor layer 10A) is as follows.
FIG. 5 schematically shows this. The contact hole located in the extension of the back gate electrode 17 shown in FIG. 5 electrically connects the extension of the back gate electrode 17 to, for example, the extension of the gate electrode 31 in a later step. This is a contact hole provided for the In some cases, the trench 15 is filled with a conductive material with a polysilicon layer containing impurities,
The back gate electrode 17 may be formed, or an impurity may be introduced into the polysilicon layer by a solid phase diffusion method instead of the ion implantation method.

[Table 7] Conditions for forming polysilicon layer Gas used: SiH ₄ / N ₂ / He = 100/200/400 sccm Pressure: 70 Pa Substrate heating temperature: 610 ° C.

[Table 8] Etch-back conditions for polysilicon layer Gas used: C ₂ Cl ₃ F ₃ / SF ₆ = 60/10 sccm Pressure: 1.3 Pa RF power: 150 W Substrate temperature: 20 ° C.

[Step-150] Thereafter, the interlayer film 1 is formed on the entire surface.
8 (see FIG. 2C). The interlayer film 18 is made of Si
Table 2 consisting of O ₂ and described in [Step-110]
Under the LP-CVD conditions described above.
After the formation of the interlayer film 18, it is desirable to planarize the surface of the interlayer film 18 by the CMP method. When the planarization of the interlayer film 18 made of SiO ₂ is insufficient, an SiO ₂ film is formed on the entire surface, a polysilicon film is further formed on the SiO ₂ film, and the surface of the polysilicon film is subjected to CMP. It may be flattened by a method. In this case, the interlayer film 18 is composed of two layers of the SiO ₂ film and the polysilicon film.

[Step-160] Next, the surfaces of the semiconductor substrate 10 and the support substrate 20 are cleaned, and the semiconductor substrate 10 and the support substrate 20 are bonded together with the interlayer film 18 interposed therebetween. The bonding conditions were 1000 ° C. in an oxygen gas atmosphere.
An example is 30 minutes.

[Step-170] Thereafter, the semiconductor substrate 10 is selectively polished from the back surface using the insulating layer 14 as a polishing stop layer, and a semiconductor layer (SOI layer) composed of the remainder of the semiconductor substrate and surrounded by the insulating layer 14 is formed. ) Obtain 10A. Specifically, until the semiconductor substrate 10 is left above the bottom 12A of the concave portion 12 by a few μm so that grinding damage does not remain on the semiconductor layer 10A which is the SOI layer, first, the semiconductor substrate 10 Is mechanically ground from the back surface (see FIG. 3A). Thereafter, the semiconductor substrate 10 is selectively polished by a chemical / mechanical polishing method (CMP method) until the bottom 12A of the concave portion 12 is exposed. Recess 1
2 functions as a polishing stop layer, and the remaining semiconductor layer 10A of the semiconductor substrate 10
It is left as an OI layer (see FIG. 3B). The concave portion 12 formed in the semiconductor substrate 10 is in a state where the insulating layer 14 is buried, and functions as an element isolation region. CM
The polishing conditions of the semiconductor substrate 10 based on the P method are shown in Table 9 below.
An example is shown below. Above the back gate electrode 17, a thickness of about 2
The semiconductor layer 10A of 0 nm is left, and the thickness of the other semiconductor layers is about 50 nm.

[Table 9] Polishing pressure: 300 g / cm ² Number of rotations: Surface plate: 60 rpm Polishing pad: Wet foamed nonwoven fabric type cloth (trade name: Suba 800) Slurry: 0.0005% ethylenediamine aqueous solution 60 cm ³ / min Temperature: 25-30 ° C

[Step-180] Next, based on the conventional method, the semiconductor layer 10A is formed above the channel formation expected region.
After the gate electrode 31 is formed with the gate insulating film 30 interposed therebetween, the gate sidewall 32 is formed on the side wall of the gate electrode 31.
Then, a source / drain region 34 and a channel formation region 35 interposed between the source / drain regions 34 are formed in the semiconductor layer (SOI layer) 10A (FIG. 4).
(A)). Specifically, after a gate insulating film 30 made of SiO ₂ having a thickness of 3 nm is formed on the surface of the semiconductor layer 10A based on a thermal oxidation method, a polysilicon layer is deposited on the entire surface under the conditions exemplified in Table 7. Then, the gate electrode 31 is formed by patterning the polysilicon layer. After that, ions are implanted into the semiconductor layer 10A to form the extension region 33, an insulating material layer is formed on the entire surface by a CVD method, and then the insulating material layer is etched back, so that the insulating material layer is etched back. The gate sidewall 32 is formed. Thereafter, the source / drain regions 34 are added to the semiconductor layer 10A by ion implantation.
And a channel formation region 35 sandwiched between the source / drain regions 34 is formed.

[Step-190] Thereafter, cobalt silicide (CoSi ₂ ) is formed on the surface of the source / drain region 34.
The layer 36 is formed (see FIG. 4B). In particular,
A cobalt layer is deposited on the entire surface by a sputtering method whose conditions are shown in Table 10 below. Next, the silicon atoms and the cobalt atoms of the semiconductor layer 10A constituting the source / drain regions 34 are caused to react with each other by a heat treatment based on the RTA (Rapid Thermal Annealing) method whose conditions are shown in Table 11 below. A cobalt silicide layer 36 is formed on the surface of. Cobalt atoms mainly move into the semiconductor layer 10A. The cobalt silicide layer 36 is also formed on the top surface of the gate electrode 31 made of polysilicon. The gate layer 32 and the cobalt layer on the insulating layer 14 are not reacted and remain as they are. Next, the unreacted cobalt layer is removed in a mixed solution of sulfuric acid, hydrogen peroxide and pure water, and the conditions are again illustrated in Table 12 below.
The resistance of the cobalt silicide layer 36 is reduced by a heat treatment based on the TA method.

[Table 10] Process gas: Ar = 100 sccm Pressure: 0.4 Pa DC power: 0.8 kW Substrate heating temperature: 450 ° C.

[Table 11] Atmosphere: 100% N ₂ atmosphere or N ₂ / Ar atmosphere Pressure: Atmospheric pressure Substrate heating temperature: 550 ° C Heating time: 30 seconds

[Table 12] Atmosphere: 100% N ₂ atmosphere or N ₂ / Ar atmosphere Pressure: Atmospheric pressure Substrate heating temperature: 700 ° C Heating time: 30 seconds

The cobalt silicide layer 36 is formed by consuming a silicon layer about 3.64 times as thick as the cobalt layer. Therefore, when a cobalt silicide layer is formed based on a 5 nm cobalt layer, the source / drain regions 3
The semiconductor layer 10A in No. 4 will disappear by about 18.2 nm. In order to lower the contact resistance between the silicide layer and the semiconductor layer 10A, it is necessary that the semiconductor layer 10A remains to some extent under the silicide layer, and the formation of the gate insulating film and the formation of the sacrificial oxide film are taken into consideration. Then, [Step-
170], the thickness of the source / drain region formation region of the semiconductor layer 10A is required to be about 30 nm or more. On the other hand, the thickness of the channel formation scheduled region of the semiconductor layer 10A upon completion of [Step-170] is required to be about 20 nm. Therefore, the method for manufacturing an SOI semiconductor device of the present invention is a very appropriate method for forming a silicide layer on the surface of a source / drain region.

Thereafter, an interlayer insulating layer is formed on the entire surface, and if necessary, the source / drain regions 34 and the gate electrodes 3 are formed.
1, an opening is formed in the interlayer insulating layer above the extending portion, and an opening is formed in the interlayer insulating layer and the insulating layer 14 above the extending portion of the back gate electrode 17, and the inside of these openings is formed. Various wirings are formed by forming a wiring material layer on the interlayer insulating layer including the wiring layer and patterning the wiring material layer on the interlayer insulating layer.

Although the present invention has been described based on the embodiments of the present invention, the present invention is not limited to these embodiments. Various conditions and materials used in the embodiments are merely examples, and can be changed as appropriate. For example, in the embodiment, the gate electrode 3 is formed of a polysilicon layer.
1 and a so-called full salicide structure in which a silicide layer is simultaneously formed on the top surface of the gate electrode 31 and the surface of the source / drain region 34 is provided.
It may have a polycide structure or a so-called metal gate structure. The silicide layer is CoSi ₂
It is not limited to a layer, but may be composed of another metal silicide layer.

[0058]

According to the present invention, a thin channel forming region (body portion) is formed without causing stress in a portion of a semiconductor layer where a gate insulating film requiring high reliability is to be formed. In addition, an SOI semiconductor device having a back gate electrode can be manufactured without increasing the number of steps to the left. In addition, since the thickness of the semiconductor layer other than the channel formation region (body portion) can be increased, a fully depleted SOI semiconductor device having sufficiently low resistance in the source / drain region and the extension region can be obtained. Can be.

[Brief description of the drawings]

FIG. 1 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a method for manufacturing an SOI semiconductor device of the present invention.

FIG. 2 is a schematic partial cross-sectional view of a semiconductor substrate and the like for explaining the method for manufacturing an SOI semiconductor device of the present invention, following FIG. 1;

FIG. 3 is a schematic partial cross-sectional view of a supporting substrate and the like for explaining the method for manufacturing an SOI semiconductor device of the present invention, following FIG. 2;

FIG. 4 is a schematic partial cross-sectional view of a support substrate and the like for explaining the method for manufacturing the SOI semiconductor device of the present invention, following FIG. 3, and a schematic view of the SOI semiconductor device of the present invention. It is a fragmentary sectional view.

FIG. 5 is a diagram schematically showing an arrangement relationship between a back surface gate electrode and a convex portion (finally constituting a semiconductor layer).

FIG. 6 is a schematic partial cross-sectional view of a semiconductor substrate and the like for describing a method for manufacturing a conventional SOI semiconductor device.

FIG. 7 is a schematic partial cross-sectional view of a support substrate and the like for illustrating a method for manufacturing a conventional SOI semiconductor device, following FIG. 6;

FIG. 8 is a schematic partial cross-sectional view of a support substrate and the like for describing a conventional method for manufacturing an SOI semiconductor device, following FIG. 7;

FIG. 9 is a schematic partial sectional view showing a modification of the conventional SOI semiconductor device.

[Explanation of symbols]

Reference numeral 10: semiconductor substrate, 10A: semiconductor layer, 11.
..Protrusions (corresponding to semiconductor layers), 12 ... recesses, 1
3 ... silicon oxide film, 14 ... insulating layer, 15 ...
Groove, 16 oxide film, 17 back gate electrode, 18 interlayer film, 20 support substrate, 30
· Gate insulating film, 31 ··· Gate electrode, 32 ··· Gate side wall, 33 ··· extension region, 34 ··· source / drain region, 35 ··· channel formation region (body portion), 36 · ..Metal silicide layers

Continued on the front page F-term (reference) 5F110 AA03 AA18 DD05 DD12 DD13 DD14 DD15 DD24 EE01 EE04 EE05 EE09 EE14 EE30 EE32 EE44 EE45 FF02 FF03 FF09 FF23 GG02 GG12 GG13 GG22 HJ13 HK05 NN17 QNN NN23 QQ30

Claims (5)

[Claims] (A) forming a convex portion on the surface of the semiconductor substrate; (b) forming an insulating layer on the surface of the semiconductor substrate having the convex portion formed thereon; and (c) penetrating the insulating layer. Forming a groove extending to the inside of the convex portion (having a height H) formed on the semiconductor substrate and having a depth D (where D <H) from the top surface of the convex portion; (D) a step of oxidizing the surface of the portion of the semiconductor substrate exposed in the groove, (e) a step of filling the groove with a conductive material to form a back gate electrode, and (f) forming an interlayer film on the entire surface. (G) bonding the semiconductor substrate and the supporting substrate together with an interlayer film interposed therebetween; and (h) selectively polishing the semiconductor substrate from the back surface using the insulating layer as a polishing stop layer, and removing the remaining portion of the semiconductor substrate. Forming a semiconductor layer surrounded by an insulating layer; A gate electrode is formed above a region where a channel is to be formed, with a gate insulating film interposed therebetween, and then a source / drain region is formed in the semiconductor layer, and a channel formation region sandwiched between the source / drain regions is formed. A method for manufacturing an SOI semiconductor device. 2. The method according to claim 1, wherein the step (b) includes a step of forming an insulating layer on the surface of the semiconductor substrate on which the convex portions are formed, and then flattening the surface of the insulating layer. The manufacturing method of the SOI type semiconductor device described in the above. 3. In the step (d), before oxidizing the surface of the portion of the semiconductor substrate exposed in the trench, oxidizing the surface of the portion of the semiconductor substrate exposed in the trench to form a sacrificial oxide film. 2. The method according to claim 1, further comprising: removing a sacrificial oxide film. 4. The manufacturing method of an SOI semiconductor device according to claim 1, wherein the groove portion extends from the convex portion provided on the semiconductor substrate to a part of the insulating layer adjacent to the convex portion. Method. 5. An interlayer film formed on a support substrate, an insulating layer formed on an interlayer film, and an insulating layer formed on the surface of the insulating layer and surrounded by the insulating layer. A semiconductor layer; (d) a source / drain region formed in the semiconductor layer; a channel forming region sandwiched between the source / drain regions; and (e) a gate insulating film formed on the channel forming region. An SOI semiconductor device comprising: a gate electrode formed by: (f) a groove penetrating through the insulating layer and extending to the inside of the semiconductor layer; and (g) a back gate electrode made of a conductive material embedded in the groove. And (h) an SOI semiconductor device, further comprising: an oxide film formed between the back gate electrode and the semiconductor layer.