JP2001053271A - Field-effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field-effect semiconductor device which is improved in high-frequency and noise characteristics by a method, wherein holes caused by impact ionization are easily absorbed by a source electrode without increasing the field-effect semiconductor device in source resistance, and a kink effect is not caused by recombination of holes and a surface level. SOLUTION: An I-InAlAs buffer layer 32, an I-InGaAs channel layer 33, and an N-InAlAs delta doped layer 35 functioning as a first feed layer are al formed on a semi-insulating InP substrate 31 for the formation of an N- channel high electron mobility transistor, and furthermore a high electron mobility transistor is equipped with an N-GaAsSb region 33A, which is selectively formed in a source region as a finite region to form a type II heterostructure, together with the channel layer 33 and generates a high concentration electron storage layer 33B connected continuously to two-dimensional electron gas generated at the interface of the channel layer 33 with a delta-doped layer 35.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field-effect semiconductor device in which a kink effect in current-voltage characteristics is suppressed and high-frequency characteristics and noise characteristics are improved.

2. Description of the Related Art In general, a field effect semiconductor device is frequently used as a semiconductor device operated in a high frequency band. For example, a high electron mobility transistor (high electric transistor) is used.
Tron mobility transformer:
HEMT) or SOIMOSFET (silicic)
on on insulator metal oxi
de semiconductor field ef
and the like are known.

FIG. 15 shows a conventional InGaAs / InAlA.
It is a figure showing the field effect semiconductor device, such as s system HEMT and SOIMOSFET, (A) shows the principal part cut side of HEMT, and (B) shows the principal part cut side and energy band diagram of SOIMOSFET, respectively. ing.

In FIG. 15A, 1 indicates that the plane index is (0).
01) is a semi-insulating InP substrate, 2 is i-InAlA
s buffer layer, 3 is an i-InGaAs channel layer, 3A
Is a two-dimensional electron gas, 4 is an i-InAlAs electron supply layer,
4A is an n-InAlAs delta-doped layer, 5 is a source electrode, 6 is a drain electrode, 7 is a gate electrode, and 8 is an alloyed layer.

In FIG. 15B, 11 is a Si semiconductor substrate, 12 is an SiO ₂ insulating film, 13 is a Si semiconductor layer, 1
3S is a SiGe source region, 13D is a drain region, 1
4 is a gate insulating film, 15 is a source electrode, 16 is a drain electrode, 17 is a gate electrode, respectively.
Appended The energy band diagrams are those viewed in cross-section along a state of applying the drain voltage to the line X-X, E _V represents the upper end of the valence band, E _C is the bottom of the conduction band respectively ing.

By the way, InGaAs / InAlAs formed on an InP substrate 1 as shown in FIG.
In the system HEMT, a characteristic called kink is remarkably observed.

This kink is caused by various causes, but has a static characteristic, that is, a characteristic that the flat portion (saturated portion) in the drain current-source-drain voltage characteristic is bent. This is a phenomenon that appears and causes deterioration of high frequency characteristics and generation of noise.

[0008] InGaAs / InAlAs HEMT
Is time-division multiplexed at 40 GHz or higher (t
im-division multiplexin
g: TDM), which is considered to be a promising key device, and it is considered that suppression of the kink effect is important for realizing the key device.

In recent years, it has been reported that the time-dependent kink effect can be explained by an equivalent circuit analysis (if necessary, see "MH Somerville et. Al.
(IEDM98) ").

According to this, the electrons in the two-dimensional electron channel injected from the source are accelerated by the high electric field near the drain, and a collision ionization phenomenon occurs, and the electrons and holes generated by the collision are ionized. The pairs will travel in opposite directions depending on the electric field.

FIG. 16 is a diagram showing a HEMT and an energy band for explaining a problem. FIG.
15 (B) shows an energy band diagram, and the same symbols as those used in FIG. 15 represent the same portions or have the same meanings. In FIG. 16, the semi-insulating InP substrate 1 is omitted.

In the figure, S is a source, D is a drain,
G indicates a gate, white circles indicate holes, black circles indicate electrons,
And the asterisk indicates that collision ionization is occurring.

As can be seen from FIG. 16B, since the energy band is slightly raised near the source S, holes generated by impact ionization stay as shown in the drawing. And the accumulated holes are i-
It is said that the ions disappear by being recombined with the surface states in the InAlAs electron supply layer 4 and the kink effect is thereby generated.

By the way, the energy band gap of InGaAs is about 0.76 [eV].
s is about half of that in s, and the impact ionization rate generally tends to increase as the energy band gap decreases.

FIG. 17 is a diagram for explaining the dependence of the impact ionization rate on the electric field intensity.
C, Si, and Ge are shown, and in the same figure on the right, various compounds are shown. The abscissa indicates the electric field intensity, and the ordinate indicates the ionization rate (if necessary, "SM Sze, Physics of
Semiconductor Devices, 2nd
ed. , P. 47 ").

From the figure, it can be clearly seen that the semiconductor material having a smaller energy band gap has a higher impact ionization rate. Therefore, when the miniaturization of a device is advanced, it is not so large in a GaAs HEMT. For impact ionization that did not need to be considered, InGaAs
It will be appreciated that in s-based HEMTs a situation must be considered.

At present, InGaAs HEMTs include:
Since a prototype with a gate length of 30 [nm] is manufactured, its parasitic capacitance and parasitic inductance are optimized and
When the dimensions between the source and the gate and between the gate and the drain are reduced, it is possible to realize a structure with a distance between the source and the drain of about 0.1 μm.

In such a HEMT, when the source-drain voltage is about 1.5 [V] and the gate voltage is about 1 [V], the electric field in the channel direction is 150 [kV / c].
m], an electric field depending on the gate voltage is applied near the gate / drain, and the electric field intensity further increases.

In such a situation, as apparent from FIG. 17, the impact ionization in InGaAs becomes equal to or greater than the impact ionization due to electrons in Si, and the collision ionization rate increases as the electric field increases. Become.

The increase in the collision ionization rate described with reference to FIG. 16 is related to the HEMT. However, as a device causing holes to be generated in the vicinity of the source and causing the kink effect, the device shown in FIG. Fully depleted SOI MOSFET as shown in FIG.

Therefore, the MOSF shown in FIG.
In the ET, a source region 13S made of SiGe is formed by ion-implanting Ge into a portion of the Si semiconductor layer 13 where a source region is to be formed and annealing the portion.
A heterointerface is formed between the SiGe and the channel Si.

In general, the forbidden band of SiGe is smaller than that of Si, and the band discontinuity is hardly present in the conduction band and is generated in the valence band. 15 and recombine with the electrons there. (If necessary, "M. Yoshim
i et. al. , IEDM94 ").

Here, the MOSF shown in FIG.
The reason why the ET has been described is that it should be seen in the basic technical concept of the MOSFET, and the present invention partially utilizes the concept.

[0024]

According to the present invention, holes caused by impact ionization are easily absorbed by a source electrode without causing an increase in resistance at the source of the field effect semiconductor device. An attempt is made to improve high-frequency characteristics and noise characteristics by suppressing the generation of a kink effect due to recombination of holes and surface states.

[0025]

For example, it is known that GaAsSb forms a staggered band lineup, that is, a so-called type II heterojunction, in which forbidden bands overlap with each other while being shifted from each other, similarly to InGaAs lattice-matched to InP. (If necessary, "Y. Sugiyayama
et. al. , "InGaAs / GaAsSb He
terostructures Lattice-Ma
tched to InP Growth Mole
cultural Beam epitaxy ", J. Cry
sta.Growth 95 (1989) pp. 36
3-366) ").

The inventor of the present invention has adopted the above technology as InGaAs / I
It was speculated that the application to the source end in an nAlAs-based HEMT would make it possible to suppress the retention of holes.

However, in such a case, all the source / channel ends in the gate width direction are made of GaAsSb / In.
When a GaAs heterojunction is used, interface recombination at the hetero interface should be a problem, and n-Ga
Since the barrier height at the Schottky junction of AsSb is increased by the staggered band lineup, the contact resistance may increase.

In the present invention, at the source end of the source region, one or more n-GaAsSb regions are arranged, and the retained holes are absorbed by the n-GaAsSb region, where they recombine with electrons, which are majority carriers. By doing so, it is fundamental to suppress the kink effect due to recombination between holes and InAlAs surface states.

FIGS. 1A and 1B are explanatory views relating to a field-effect semiconductor device for explaining the principle of the present invention, wherein FIG. 1A shows a main part cut plane and FIG. 1B shows a main part cut side surface.

In the figure, 21 is a semi-insulating InP substrate having a plane index of (001), 22 is an i-InAlAs buffer layer, 23 is an i-InGaAs channel layer, and 23A is a source region of the channel layer 23. N- formed
GaAsSb region (second supply layer), 23B is i-In
A high-concentration electron accumulation layer formed on the channel layer 23 side at the hetero interface formed of GaAs and n-GaAsSb, and 23C is a channel formed on the channel layer 23,
4 is an i-InAlAs spacer layer, 25 is n-InAl
As delta-doped layer (electron supply layer: first supply layer),
26 indicates an i-InAlAs barrier layer, and 27 indicates a gate electrode.

FIG. 2 is an energy band diagram of a required section of the field-effect semiconductor device shown in FIG. 1, and FIG. 2A is an energy band diagram of a section along X1-X1 in FIG. -Diagram, (B) is an energy band diagram seen in a section along X2-X2 in Fig. 1, (C) is an energy band diagram seen in a section along Y-Y in Fig. 1 It is. Note that FIG.
And same symbols that are used at the 16 and or have the same meanings representing the same portion, also, E _F represents the Fermi level.

The cross section along the line X1-X1 in FIG. 1 is one in which the line connecting the source, gate and drain crosses the channel 23C made of InGaAs.
It is in exactly the same state as EMT and the corresponding FIG.
It is known from the energy band diagram shown in (A) that the conventional H described with reference to FIG.
Exactly the same as EMT.

The cross section along the line X2-X2 in FIG. 1 similarly crosses the channel 23C, but the cross section is the n-GaAsSb region 23 formed in the source region.
A, the source end, that is, n-GaAsS
Channel 23 composed of b region 23A and i-InGaAs
The interface with C forms a type II heterojunction structure, and has a structure in which holes easily fall as can be seen from the corresponding energy band diagram shown in FIG. 2B.

The cross section taken along the line YY in FIG.
The source region in the nGaAs channel layer 23 has n-G
Since the aAsSb region 23A is formed, i-In
Since the portion of the GaAs channel layer 23 and the n-GaAsSb region 23A are arranged in a line-and-space manner, and the interface thereof has a modulation doping structure, the interface is located on the i-InGaAs channel layer 23 side. In FIG. 2, an electron accumulation layer 23B (thick broken line) having a higher concentration than the surrounding, i.e., the i-InGaAs channel layer 23 is generated.
In the energy band diagram shown in (C), the electrons are GaAsSb / InGaAs due to the n-InAlAs delta-doped layer 25 as the first supply layer and the n-GaAsSb region 23A as the second supply layer. The accumulation at the interface is shown.

According to this configuration, it is possible to reduce the influence of interface recombination, and it is effective to suppress an increase in source resistance due to the regrowth of the n-GaAsSb region 23A in the source. FIG. 2C also shows the energy band (broken line) of the n-InAlAs delta-doped layer 25 as the first supply layer.

As described above, in the field-effect semiconductor device according to the present invention, (1) the substrate formed on the first compound semiconductor substrate (for example, the semi-insulating InP substrate 31); A buffer layer (for example, an i-InAlAs buffer layer 32) made of a second compound semiconductor of the same kind or having substantially the same lattice constant, and a third layer having substantially the same lattice constant as the substrate and having a smaller forbidden band width than the buffer layer. A channel layer made of a compound semiconductor (e.g., i-InGaAs channel layer 33) and a first supply layer made of a second compound semiconductor (e.g., n-InAlA) which forms a heterointerface with the channel layer
In the n-channel high electron mobility transistor including the s delta doped layer 35), the s delta doped layer is selectively formed in a finite region (for example, a source region) in a channel layer below a source electrode (for example, the source electrode 40S). A two-dimensional electron gas that forms a type II heterostructure between the first supply layer and the channel layer at the interface between the first supply layer and the channel layer and is continuous with the two-dimensional electron gas generated on the channel layer side A second supply layer (for example, n-GaAsSb) made of a fourth compound semiconductor that generates a gas (for example, high-concentration electron storage layer 33B)
Region 33A), or

(2) In the above (1), the finite region in the channel layer where the second supply layer is formed is a source region, and the second supply layer is a side surface. The upper surface is in contact with the channel layer and the upper surface is in contact with the first supply layer, and the first supply layer and the second supply layer are both n-type conductive, or

(3) In the above (1), one or more gate electrodes (for example, a gate electrode 39G) are provided, and the first compound semiconductor is InP and the second compound semiconductor is InA.
The GaAs and the third compound semiconductor are InGaAs and the fourth compound semiconductor or GaAsSb.

By adopting the above-mentioned means, holes caused by impact ionization are easily absorbed by the source electrode without staying near the source without causing an increase in resistance at the source of the field effect semiconductor device. As a result, the occurrence of a kink effect due to recombination of holes and surface levels is suppressed, and high-frequency characteristics and noise characteristics can be improved.

[0040]

FIG. 3 is an explanatory view for explaining a field effect semiconductor device (HEMT) according to an embodiment of the present invention, wherein FIG. Parentheses indicate the cut-away sides of the main part. (B) is (A)
2 shows a plane cut along the line XX.
Further, in FIG. 3 and the following drawings, in FIG. 3A showing a main part cutting plane, elements shown in FIG. 3B showing a main part cutting side face are omitted for simplicity. ) Is FIG.
A part of the semiconductor layer shown in FIG.

In the figure, 31 is a semi-insulating InP substrate having a plane index of (001), 32 is an i-InAlAs buffer layer, 33 is an i-InGaAs channel layer, and 33A is a source of the i-InGaAs channel layer 33. The n-GaAsSb region formed in the region, 33B is i-InGaAs
-InG at the hetero interface between n-GaAsSb and n-GaAsSb
The high-concentration electron accumulation layer generated on the aAs channel layer 33 side, 33C is a channel in the i-InGaAs channel layer 33, 34 is an i-InAlAs spacer layer, and 35 is an n-InAlAs delta-doped layer (electron supply layer: the first supply layer) 36 i-InAlAs barrier layer 37 is n ⁺ type InAlAs contact layer, 38 n ⁺ -ing
a contact layer made of aAs; 39G, a gate electrode;
0S indicates a source electrode, and 41D indicates a drain electrode.

FIGS. 4 to 14 are cutaway side views of essential parts at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3. FIG. 3 (B) shows a main part cut side surface along line XX in FIG. 3, and FIG. 3 (B) shows a main part cut side surface along line YY in FIG. 3. I do.

FIG. 4 4- (1) MBE (Molecular Beam Epitax)
y) By applying the method, the semi-insulating InP substrate 31
I-InAlAs buffer layer 32, i-InGaAs
s channel layer 33, i-InAlAs spacer layer 34,
n-InAlAs delta doped layer 35, i-InAl
As barrier layer 36, n ⁺ -InAlAs contact layer 3
7. An n ⁺ -InGaAs contact layer 38 is sequentially grown. 33C indicates a channel (two-dimensional electron gas).

The main data on the grown semiconductor layers is as follows. i-InAlAs buffer layer 32 thickness: 0.4 [μm] i-InGaAs channel layer 33 thickness: 10 [nm] i-InAlAs spacer layer 34 thickness: 5 [nm] n-InAlAs delta doped layer 35 thickness Thickness: 3 [nm] Impurity: Si Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ] i-InAlAs barrier layer 36 Thickness: 5 [nm] n ⁺ -InAlAs contact layer 37 Thickness: 10 [nm] Impurity concentration : 5 × 10 ¹⁸ [cm ⁻³ ] n ⁺ -InGaAs contact layer 38 Thickness: 10 [nm] Impurity concentration: 1 × 10 ¹⁹ [cm ⁻³ ]

In this case, the substrate temperature for growing each semiconductor layer is basically 520 ° C.
N-InAlAs such as delta doped layer is 480 [℃]
The n-InGaAs was grown at 420 ° C., respectively.

In this field-effect semiconductor device, when forming a gate in a recess, n ⁺ -InAl
If an InP layer is interposed between the As contact layer 37 and the i-InAlAs layer 36, the etching can be automatically stopped, and the formation of the recess can be performed accurately and easily. In this case, the gas source M
BE method and MOVPE (metalorganic va
A por phase epitaxy method may be applied.

FIG. 5 5- (1) CVD (Chemical Vapor Deposition)
The thickness is 200 [n] by applying the method.
m] of the SiO ₂ layer 51 is formed.

5- (2) At least one stripe opening 52A is formed in a portion where a source region is to be formed, or a line-and- Space-like stripe opening 5
A resist layer 52 having 2A is formed.

FIG. 6 6- (1) SiO ₂ layer 5 using resist layer 52 as a mask by applying a wet etching method using an etchant of NH ₄ F: HF = 10: 1 ammonium fluoride solution.
1 is formed to form an opening 51A having the same pattern as the stripe opening 52A.

FIG. 7 7- (1) After removing the resist film 52, a wet etching using a citric acid-based etching solution (for anisotropic etching) and a hydrofluoric acid-based etching solution (for isotropic etching) is performed. depending on applying the etching method, i from surface of the n ⁺ -InGaAs contact layer 38 of SiO ₂ film 51 as a mask
The etching reaching the interface between the -InGaAs channel layer 33 and the i-InAlAs buffer layer 32 is performed to form the hole 3
3H is formed. Note that, specifically, the citric acid-based etching solution is citric acid: H ₂ O ₂ : H ₂ O = 1: 3: 2
And specifically, as a hydrofluoric acid-based etching solution, H
F: H ₂ O ₂ : H ₂ O = 5: 80: 1800 was used, respectively. In addition, according to the citric acid-based etching solution, InGa
As can be selectively etched.

FIG. 8 8- (1) By applying the gas source MBE method, the natural oxide film on the semiconductor surface exposed in the hole 33A in an arsine (AsH ₃ ) atmosphere is removed. After removal, the subsequent application of the gas source MBE method resulted in holes 3
10 nm thick n- lattice matched to InP in 3H
A GaAsSb (n = 1 × 10 ¹⁸ [cm ⁻³ ]) region 33A is formed. Incidentally, the gas source MBE method is another film forming method, for example, MOVPE (metal organic vapor).
r phase epitaxy) method,
Alternative techniques may be used.

8- (2) Subsequently, the thickness 5 [n] is applied by applying the gas source MBE method.
m] i-InAlAs spacer layer, 3 nm thick n-InAlAs delta-doped layer, 5 nm thick i-InAlAs barrier layer, 10 nm thick n ⁺ −
InAlAs contact layer, 10 nm thick n ⁺ −
An InGaAs contact layer is selectively grown to fill the hole 33H and flatten. Each of the semiconductor layers grown here is made up of an i-InAlAs spacer layer 34, an n-InAlAs delta-doped layer 35, i
-InAlAs barrier layer 36, n ⁺ -InAlAs contact layer 37, and n ⁺ -InGaAs contact layer 38 are shown integrally.

9- (1) The SiO ₂ layer 5 is formed by applying a wet etching method using an ammonium fluoride solution as an etchant.
After removing 1, an insulating layer 53 made of SiO _{2 having} a thickness of about 100 [nm] is formed by applying a plasma CVD method.

Referring to FIG. 10, 10- (1) An EB (electron beam) exposure resist layer 54 having an opening 54A at a portion where a gate electrode is to be formed is formed by applying a resist process in lithography technology.

10- (2) The resist layer 54 is formed by applying a wet etching method using an etchant as an ammonium fluoride solution.
Is used as a mask to etch the SiO ₂ layer 53 to form an opening 53A having the same pattern as the opening 54A.

11- (1) A thickness of 20 is obtained by applying a sputtering method while leaving the resist layer 54 having the opening 54A as it is.
A WSi layer of 0 [nm] is formed.

11- (2) A gate electrode 39 is formed by patterning the WSi layer by applying a lift-off method of dissolving and removing the resist layer 54.
G is formed.

Referring to FIG. 12, 12- (1) EB exposure resist layer 56 having openings 56S and 56D is formed at portions where source and drain electrodes are to be formed by applying a resist process in lithography technology. I do.

13- (1) The resist layer 56 is formed by applying a wet etching method using an etchant as an ammonium fluoride solution.
Etched SiO ₂ layer 53 as a mask, to form openings 53S and the opening 53D of the same pattern as the opening 56S and the opening 56D.

Referring to FIG. 14, 14- (1) The thickness of 50 [nm] / 200 [nm] is obtained by applying a vacuum deposition method while leaving the resist layer 56 having the openings 56S and 56D as it is. An AuGe / Au layer is formed.

14- (2) The AuGe / Au layer is patterned by applying a lift-off method of dissolving and removing the resist layer 56 to form the source electrode 40S and the drain electrode 40D.

14- (3) An alloying heat treatment of the source electrode 40S and the drain electrode 40D is performed at a temperature of 400 ° C. and a time of 1 minute.

The HEMT obtained through the above steps exhibited good static characteristics with suppressed kink effect and excellent high frequency characteristics and noise characteristics.

The present invention is not limited to the above-described embodiment, and can realize many modifications without departing from the scope of the claims. For example, in the above-described embodiment, a double-gate HEMT is described. Although described, it goes without saying that a single gate may be used if necessary.

[0065]

In the field effect semiconductor device according to the present invention,
In an n-channel high electron mobility transistor, a finite region (source region) in a channel layer below a source electrode
Type II is selectively formed in and between the channel layer
A fourth compound semiconductor that generates a heterostructure and generates a two-dimensional electron gas that is continuous with the two-dimensional electron gas generated on the channel layer side at the interface between the first supply layer and the channel layer; And a second supply layer.

By adopting the above configuration, holes caused by impact ionization are easily absorbed by the source electrode without staying near the source without causing an increase in resistance at the source of the field effect semiconductor device. As a result, the occurrence of a kink effect due to recombination of holes and surface levels is suppressed, and high-frequency characteristics and noise characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram relating to a field-effect semiconductor device for explaining the principle of the present invention.

FIG. 2 is an energy band diagram of a required cross section of the field-effect semiconductor device shown in FIG.

FIG. 3 is an explanatory diagram for describing a field effect semiconductor device (HEMT) according to one embodiment of the present invention.

FIG. 4 is a fragmentary side elevation view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 5 is a fragmentary side elevation view at a key step for explaining the step of manufacturing the field-effect semiconductor device described with reference to FIG.

6 is a fragmentary side elevational view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 7 is a fragmentary side elevation view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 8 is a fragmentary side elevational view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

9 is a fragmentary side elevation view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 10 is a fragmentary side elevation view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 11 is a fragmentary side elevation view at a key step for explaining the step of manufacturing the field-effect semiconductor device described with reference to FIG.

FIG. 12 is a fragmentary side elevation view at an important point of the process for describing a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 13 is a fragmentary side elevation view at a key step for explaining the step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 14 is a fragmentary side elevation view at a key step for explaining a step of manufacturing the field-effect semiconductor device described with reference to FIG. 3;

FIG. 15 shows a conventional InGaAs / InAlAs-based HEM.
FIG. 3 is a diagram illustrating a field effect semiconductor device such as a T and SOI MOSFET.

FIG. 16 is a diagram showing HEMTs and energy bands for explaining a problem.

FIG. 17 is a diagram for explaining electric field intensity dependence of a collision ionization rate.

[Explanation of symbols]

31 semi-insulating InP substrate 32 i-InAlAs buffer layer 33 i-InGaAs channel layer 33A n-GaAsSb region 33B high concentration electron storage layer 33C channel 34 i-InAlAs spacer layer 35 n-InAlAs delta-doped layer (electron supply layer: (First supply layer) 36 i-InAlAs barrier layer 37 n ⁺ -InAlAs contact layer 38 n ⁺ -InGaAs contact layer 39G gate electrode 40S source electrode 41D drain electrode

Claims (3)

[Claims] 1. A buffer layer made of a second compound semiconductor, which is formed on a substrate made of a first compound semiconductor and has the same kind or a lattice constant substantially the same as that of the substrate, and a forbidden band whose lattice constant is substantially the same as that of the substrate. An n-channel height including a channel layer made of a third compound semiconductor having a width smaller than that of the buffer layer, and a first supply layer made of a second compound semiconductor that forms a heterointerface with the channel layer; In an electron mobility transistor, a type II heterostructure is selectively formed in a finite region in a channel layer below a source electrode to form a type II heterostructure with the first supply layer and the first supply layer. A second supply layer made of a fourth compound semiconductor that generates a two-dimensional electron gas continuous with the two-dimensional electron gas generated on the channel layer side at the interface with the channel layer. Field-effect semiconductor device according to. 2. A finite region in the channel layer where the second supply layer is formed is a source region, and the second supply layer is in contact with the channel layer on a side surface and has an upper surface which is the same as the source region. 2. The field effect semiconductor device according to claim 1, wherein the first supply layer and the second supply layer are in contact with the first supply layer, and both the first supply layer and the second supply layer have n-type conductivity. 3. A semiconductor device comprising one or more gate electrodes, wherein the first compound semiconductor is InP and the second compound semiconductor is InAl.
2. The field effect semiconductor device according to claim 1, wherein As and the third compound semiconductor are InGaAs and a fourth compound semiconductor or GaAsSb.