JP2001053016A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a shallow pn junction without leak current by forming a second conductivity reverse region with the solid phase diffusion of a second conductive second semiconductor in a first conductivity first conductor where an oxide film is removed by solution that is made of hydrogen fluoride with a specific concentration and a surface-active agent for coating with the surface- active agent. SOLUTION: A semiconductor substrate 2 as a first semiconductor is dipped into a solution 7 where a surface-active agent 8 of approximately 0.01 to 10 wt.% is added to a dilute fluoric acid solution containing hydrogen fluoride of approximately 0.1 to 10 wt.%. By the dilute fluoric acid treatment, an oxide film being formed on the surface of the semiconductor substrate 2 is removed for exposing the surface. At this time, the surface-active agent 8 is adsorbed onto the surface of the semiconductor substrate 2, thus reducing the number of hydrophobic deposits 4 being adsorbed to the surface of the semiconductor substrate 2 and an element isolation film 3. After that, a semiconductor layer 5 made of amorphous silicon as a second semiconductor is laminated for crystallizing, thus obtaining a p-type semiconductor layer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pn junction used in a semiconductor device.

[0002]

2. Description of the Related Art In recent years, a technique for forming a very shallow pn junction of 30 nm has been developed. One of them is Y. Mitani, I. Mizushima, S. Kambayashi, H.
Koyama, MT Takagi and M. Kashiwagi "Buried Sou
rce and Drain (BSD) Structurefor Ulta-shallow Junct
ion Using Selective Deposition of Highly Doped Amo
rphous Silicon "1996 Symposium on VLSI Technology
Digest of Technical Papers p.176. According to this document, p-type amorphous silicon is laminated on an n-type silicon substrate, the amorphous silicon is crystallized, and p-type impurities are solid-phase grown on the n-type substrate to form a p-type single crystal semiconductor layer. By forming, a shallow pn of 0.1 mm or less
Methods for forming the junction have been reported.

[0003]

The present inventor conducted an experiment for forming a pn junction on a semiconductor substrate having element isolation formed by this method. As a result, it has been found that a hydrophobic deposit is formed at the initial interface of the n-type semiconductor layer on which the p-type semiconductor layer is laminated, and a defect resulting from this causes a leak current between the pn junctions. Hereinafter, this problem will be described in detail.

FIG. 1 is a process flow for forming a pn junction described in the above-mentioned document. FIG. 2 is a view showing a dilute hydrofluoric acid treatment, and FIG. 3 is a view after depositing a second semiconductor layer and performing solid phase diffusion annealing.

First, arsenic or phosphorus was added at 10 ¹⁶ cm ^-3 .
An element isolation film 3 made of, for example, a silicon oxide film is formed on the surface of an n-type Si substrate 2, and a wafer having a partially exposed Si surface is prepared. On the surface of the Si substrate 2 in advance SiO ₂
A natural oxide film made of is usually formed. In addition, Di Butyl Phthala
te (DBP), Di Octyl Phthalate (DOP), Di Ethyl Phtha
phthalates such as late (DEP) and (CH ₃ ) ₃
SiOH, siloxane, and particles whose surface is coated with an organic substance adhere. These usually become hydrophobic adsorbates, and when adsorbed, there is a problem that they cause other hydrophobic adsorbates to be adsorbed.

Next, hydrochloric acid, hydrogen peroxide solution and pure water 1: 1: 6
Is kept at 70 to 95 ° C., and the substrate 2 is immersed for 1 to 100 minutes to remove metals such as Fe, Ni and Cu adhered to the surface of the natural oxide film. This treatment for removing the metal is necessary as a pretreatment for laminating the silicon, in order to reduce traps due to the metal and favorably form a pn junction having a small leak current.
However, this chemical is acidic, and the zeta potential of the silicon surface is negative, while the zeta potential of the organic substance and the particles is positive. Therefore, there is a problem that particles are more adsorbed on the silicon surface. When the semiconductor substrate 2 contains Si, the surface of the semiconductor substrate 2 is oxidized by this acidic oxidizing agent aqueous solution,
There is a problem of forming a chemical oxide film containing O ₂ .

Then, after rinsing the substrate, as shown in FIG. 2, a diluted hydrofluoric acid solution 1 containing hydrogen fluoride at a weight percentage of 0.1% to 10% and a temperature range of 1 ° C. to 90 ° C.
By immersing the semiconductor substrate 2 for 1 to 10 minutes, the chemical oxide film on the surface of the semiconductor substrate 2 is removed by etching. After the etching of the silicon-containing oxide film, the hydrophobic surface of the semiconductor substrate 2 and the hydrophilic surface of the element isolation film 3 made of the silicon oxide film are exposed in the aqueous solution.

At this time, in the experiment of the present inventor, when the hydrophobic adsorbent 4 originally attached to the surfaces of the semiconductor substrate 2 and the element isolation film 3 and the pure water rinse were diluted in the diluted hydrofluoric acid aqueous solution 1, Hydrophobic adsorbent 4 brought along with the chemical
In addition, the hydrophobic adsorbed substance 4 attached to the container of the diluted hydrofluoric acid aqueous solution 1 and the hydrophobic adsorbed substance 4 contained in the raw material of the diluted hydrofluoric acid aqueous solution are mixed into the aqueous solution 1 by etching the oxide film. It was found to disperse. It has been found that these hydrophobic adsorbents 4 are re-adsorbed on the surface of the semiconductor substrate 2 from which the surface oxide film has been removed, particularly in an acidic solution. In this case, in particular, the surface of the semiconductor substrate 2 is stronger in hydrophobicity than the surface of the element isolation film 3, so that the surface is more easily adsorbed.

Thereafter, the water remaining on the surface of the semiconductor substrate 2 is blown off and dried by rotating the semiconductor substrate 2 at a high speed, and the hydrophobic adsorbent 4 remains on the surface of the semiconductor substrate 2. became. After this, 10 ²¹
When a second semiconductor layer 5 made of amorphous silicon to which cm ^{-3 was} added was laminated to form a shallow pn junction, FIG.
As described above, a large number of the hydrophobic adsorbents 4 adhered to the boundary between the semiconductor substrate 2 and the second semiconductor layer 5, and a leak current occurred.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide a method for forming a shallow pn junction of 20 nm or less without a leak current.

[0010]

In order to achieve the above-mentioned object, the present invention provides a method of forming a first semiconductor of the first conductivity type containing silicon on a surface of hydrogen fluoride (0.1% to 10% by weight). ) And a surfactant (a weight percent of 0.01% or more and 10% or less), and an oxide film formed on the surface of the first semiconductor is removed to remove the surface of the first semiconductor. A step of coating with a surfactant; a step of depositing a second semiconductor of a second conductivity type on the surface of the first semiconductor coated with the surfactant; and a solid phase diffusion from the second semiconductor. Forming a second conductivity type inversion region in the first semiconductor by pn
A method for forming a bond is provided.

Further, the present invention provides a method of manufacturing a semiconductor device comprising the steps of forming a surface of a first semiconductor of a first conductivity type containing silicon with hydrogen fluoride (0.1% to 10% by weight) and a surfactant (0.01% to 10%).
The following weight percent) is immersed in an aqueous solution comprising: removing the oxide film formed on the surface of the first semiconductor;
A step of coating the surface of the first semiconductor with the surfactant, a step of depositing an amorphous semiconductor on the surface of the first semiconductor coated with the surfactant, and crystallizing the amorphous semiconductor. A method for forming a pn junction is provided, wherein a second conductivity type inversion region is formed in the first semiconductor.

The present invention also provides a method for forming a pn junction, wherein the surfactant comprises an alcohol containing an alkyl group and has a molecular weight of 50 to 90.

[0013] The present invention also provides a method for forming a pn junction, wherein the surfactant comprises propanol.

Further, in the present invention, the step of depositing the amorphous semiconductor is performed at a temperature of 400 ° C. or less.
A method for forming an n-junction is provided.

[0015] The present invention provides a method for forming a pn junction, wherein the step of crystallizing the amorphous semiconductor is performed at 750 ° C or lower.

The crystallized semiconductor region provides a method of forming a pn junction in which an impurity of the second conductivity type is added to the semiconductor solution at a temperature higher than the solid solubility in the step of crystallizing the amorphous semiconductor.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 4 shows a semiconductor device according to a first embodiment of the present invention.
4 shows a process flow of forming an n-junction. The present invention
Add a surfactant to the aqueous solution for dilute hydrofluoric acid treatment,
The surface of the semiconductor substrate is coated with a surfactant before the hydrophobic adsorbent adheres, a second semiconductor layer is deposited on the surface where the surfactant remains, and solid phase diffusion annealing is performed to form a pn junction This is characterized by the fact that a surfactant that does not increase the reverse leakage current of the pn junction is present.

The first embodiment will be described with reference to FIGS.

First, an element isolation film 3 made of, for example, a silicon oxide film is formed on a surface of a semiconductor substrate 2 made of n-type Si doped with, for example, 10 ¹⁵ to 10 ¹⁹ cm ^-3 arsenic, phosphorus, or antimony. First, a wafer having a partially exposed Si surface is prepared. FIG. 5 shows an example in which the trench element isolation 3 is formed. However, instead of the trench element isolation, for example, mesa etching or LOCOS element isolation may be used. This Si surface may have a structure covered with, for example, a silicon oxide film of 20 nm or less.

Before the treatment with hydrochloric acid and aqueous hydrogen peroxide, for example, a process of removing organic substances that have already adhered to the surface by using a 1: 1 mixed solution of sulfuric acid and aqueous hydrogen peroxide. A process of removing sulfuric acid and hydrogen peroxide by water rinsing may be added. Next, the water remaining on the surface of the semiconductor substrate 2 is blown off and dried by, for example, rotating the semiconductor substrate at a high speed.

At this time, before the step of exposing the semiconductor substrate to the atmosphere, the semiconductor substrate is contained in a clean room, for example,
Di Butyl Phthalate (DBP) and Di Octyl Phthalate (DO
P), phthalic acid esters such as DiEthyl Phthalate (DEP), and (CH ₃ ) ₃ SiOH and siloxane, and hydrophobic adsorbents 4 composed of particles whose surface is coated with an organic substance are deposited on the surface of the semiconductor substrate 2. It adheres and remains.

Next, a mixture of hydrochloric acid, aqueous hydrogen peroxide and pure water, for example, having a volume ratio of 1: 1: 6 to 1: 1: 8 is kept at 70-95 ° C. and immersed for 1-100 minutes. Then, metal such as Fe, Ni, and Cu contained in the surface of the semiconductor substrate 2 and the surface of the element isolation film 3 is etched. At this time, if the semiconductor substrate 2 contains Si, the semiconductor substrate 2
2 surface is oxidized, and the chemical oxide film containing SiO ₂
It is formed with a thickness of 5 nm. Thereby, the hydrophobic adsorbate 4
Is adhered on the chemical oxide film even if it is re-adhered, and the semiconductor substrate 2 containing Si does not come into direct contact with the hydrophobic adsorbent 4 to form a clean interface.

Next, by rinsing with pure water, hydrochloric acid and aqueous hydrogen peroxide are replaced and removed.

Next, as shown in FIG.
Dilute hydrofluoric acid solution containing in weight percent ranging from to 10%, for example, surfactant 8 consisting of 2-propanol
The semiconductor substrate 2 is immersed in an aqueous solution 7 added at a weight percentage ranging from 0.01% to 10%. This processing time
The temperature of the aqueous solution 7 is set between 1 and 80 ° C. for 10 seconds to 10 minutes.

In the immersion process, for example, cleaning may be performed by applying ultrasonic vibration or megasonic vibration. Here, in the diluted hydrofluoric acid aqueous solution 7, for example, the hydrophobic adsorbent 4 originally attached to the surfaces of the semiconductor substrate 2 and the element isolation film 3 is separated from the surface by etching of the oxide film, and Disperse in. In addition, the hydrophobic adsorbate 4 attached to the diluted hydrofluoric acid aqueous solution container and the hydrophobic adsorbent 4 contained in the raw material of the diluted hydrofluoric acid aqueous solution are also dispersed in the aqueous solution 7. The oxide film formed on the surface of the semiconductor substrate 2 as the first semiconductor is removed by the diluted hydrofluoric acid treatment,
The surface of the semiconductor substrate 2 is exposed. At this time, the surfactant 8 is adsorbed on the first semiconductor surface.

In FIG. 5, the hydrophobic group (lipophilic group) of the surfactant is indicated by □, and the hydrophilic group is indicated by ○. Surfactants are semiconductors
The hydrophobic groups are adsorbed by arranging hydrophobic groups on the hydrophobic surface side. Therefore, the hydrophilic group side is arranged on the aqueous solution side. As a result, on the surface of the semiconductor substrate 2 coated with the surfactant 8, the hydrophilic groups of the surfactant 8 are arranged, and the zeta potential of the hydrophobic deposit 4 and the semiconductor surface on which the surfactant 8 is adsorbed. 2, the difference between the zeta potential and the hydrophobic adhering substance 4 becomes less likely to be adsorbed on the surface by electrostatic force.

Furthermore, when the surfactant is added in an amount higher than the critical micelle concentration, aggregate micelles 8 'of the surfactant with the hydrophilic group directed outward are formed as shown in FIG. This shows that hydrophobic deposits 4 'dispersed in an aqueous solution are shown in FIG.
Around the hydrophobic group as in
Has an increased hydrophilicity and is easily emulsified or solubilized and easily dispersed in the aqueous solution 7. Therefore, the hydrophobic deposits 4 'are easily removed together with the rinsing liquid during the pure water rinsing in the subsequent step.

As shown in FIG. 5, when the surfactant 8 is adsorbed on the hydrophobic attachment 4 ″ attached on the element separation film 3, the hydrophilic group is directed to the aqueous solution 7 side. Therefore, the surface tension of the hydrophobic adhered substance 4 ″ is reduced, and it becomes easier to emulsify or disperse in the aqueous solution.

From the above effects, the number of hydrophobic deposits 4 adsorbed on the semiconductor surface 2 and the element separation film 3 can be reduced.

In particular, it is particularly important that the surfactant 8 of the present embodiment has a molecular weight not too large as compared with the conventional sulfonic acid-based surfactant. This will be described below.

By keeping the molecular weight of the surfactant 8 smaller than that of the hydrophobic deposit 4, the activation energy for diffusion can be kept small. Therefore, the diffusion rate on the semiconductor substrate surface 2 and the diffusion rate on the element isolation 3 are made larger than the hydrophobic deposit, and the surface of the oxide film is removed, and the surfactant is faster than the hydrophobic deposit. 8 can be covered and desirable. Thus, for example, the molecular weight of the surfactant 8 is smaller than that of a typical organic adsorption contaminant (CH ₃ ) ₃ SiOH, that is, 9
Desirably less than 0.12.

Further, when an organic substance having a large molecular weight such as DOP having a molecular weight of 390.6 adheres to the semiconductor surface, it remains as a carbide on the surface even in a process of 900 ° C. or more and deteriorates the device characteristics.
s, SSDM 1995, Yokohama, p.273. Therefore, the molecular weight of the surfactant needs to be smaller than 390.6.

On the other hand, when an R-OH type alcohol is used as a surfactant, the larger the molecular weight of the alkyl group R, the greater the polarization between the hydrophilic group OH and the hydrophobic group R, and the lowering of the surface tension. And the adsorption energy of the surfactant 8 on the semiconductor surface 2 can be increased, and the molecular weight is in a desirable range. In particular, we have found that by using 2-propanol as a surfactant, there is no increase in junction leakage despite the fact that the surfactant is believed to remain on the semiconductor surface 2 before the second semiconductor deposition. It has been newly found that a good pn junction can be formed.

It is necessary that the molar concentration 8 of the surfactant is larger than the molar concentration of the hydrophobic adsorbent 4.
It must be smaller than the solubility,
It is desirable to include between 0.01% and 10% by weight.

Thereafter, by performing pure water rinsing, the diluted hydrofluoric acid aqueous solution is replaced and removed.

Thereafter, the water remaining on the surface of the semiconductor substrate 2 is blown off and dried, for example, by rotating the semiconductor substrate at a high speed. This drying step may be replaced with a method in which the water on the wafer surface is replaced with 2-propanol and dried by, for example, 2-propanol vapor in a nitrogen atmosphere. Here, as the surfactant 8, the second
It is desirable that the semiconductor layer 5 remains on the exposed surface of the semiconductor region 2 after drying until the semiconductor layer 5 is deposited, maintains a hydrophilic surface, and makes it difficult for hydrophobic adsorbate in the atmosphere to be adsorbed. For this reason, it is desirable to use 2-propanol, which has a higher adsorption energy to the semiconductor wafer and is less likely to evaporate than methanol or ethanol. Since the surfactant is more easily adsorbed on the surface of the semiconductor substrate 2 than water, the surfactant is not replaced by water molecules even after drying, and the surfactant is coated on the semiconductor surface 2 as shown in FIG. State.

If the conventional process of diluting hydrofluoric acid without adding a surfactant and then drying the wafer with 2-propanol vapor in a nitrogen atmosphere is used, the effect of the present invention cannot be obtained. . This is because there is no effect of reducing the amount of the hydrophobic adsorbate 4 adhering to the surface of the semiconductor substrate 2 at the time of the dilute hydrofluoric acid treatment.
This is because, usually, the molecular weight is larger than that of 2-propanol and the adsorption energy is larger, so that it remains on the surface of the semiconductor substrate 2.

Next, as shown in FIG. 7, a second semiconductor layer 5 made of amorphous silicon to which, for example, boron is added at a concentration of 10 ²⁰ to 10 ²² cm ^-3 is laminated. At this time, for the purpose of forming a shallow pn junction, the film thickness of the semiconductor layer 5 is usually as thin as 1 mm or less, and it is important to control the thickness of the thin film. Therefore, the compound of the second semiconductor layer, for example, Si
Either a gas of H ₄ or Si ₂ H ₆ is supplied, or a vapor growth method of supplying Si atoms as a molecular beam is used.

For example, as a vapor phase growth method, for example, the above-mentioned semiconductor substrate is put in a quartz tube and heated in a range of 300 ° C. to 400 ° C., and then disilane or silane gas is fed for 50 to 300 seconds.
10-30 sc of diborane gas diluted with He to ccm and 10%
By flowing cm, B-doped amorphous silicon is deposited on the entire surface. In order to grow the semiconductor region 2 by supplying Si atoms as molecular beams, the substrate temperature must be at least 300 ° C. in order to cause sufficient migration on the semiconductor surface.
By then, the substrate temperature needs to be raised.

By forming amorphous silicon under such conditions, an amorphous silicon layer having a boron impurity density of 1 × 10 ²¹ cm ⁻³ to 2 × 10 ²¹ cm ⁻³ can be formed. At this time, the solid solubility of boron is 1
Since it is smaller than x10 ²⁰ cm ^-3 , boron exceeding the solid solubility is added to the second semiconductor layer 5.

Thereafter, the second semiconductor layer 5 may be patterned by lithography or etching.

Next, the second semiconductor layer 5 is crystallized by applying a heat treatment at 550 ° C. to 750 ° C. for 0.1 hour to 10 hours in an inert gas such as N ₂ or Ar. Obtain a p-type semiconductor layer. In particular, when the semiconductor substrate 2 is a single crystal, the second semiconductor 5 should be grown as a single crystal by solid phase growth from the semiconductor substrate 2 side, thereby lowering the resistance of the second semiconductor 5 and reducing the number of defects. Is desirable to reduce

At this time, as shown in FIG. 7, boron added to the second semiconductor layer 5 diffuses toward the semiconductor substrate 2 and
The changed region 6 is formed in the mold layer. The temperature of the heat treatment at this time needs to be suppressed to 750 ° C. or less so that boron that has entered supersaturation does not precipitate in the second semiconductor layer to form an inactive boron cluster. Further, the temperature needs to be 500 ° C. or higher in order to crystallize amorphous silicon by solid phase epitaxial growth.

FIG. 8 shows the cumulative distribution of the leak current of the pn junction formed as described above and the cumulative distribution of the leak current of the pn junction formed by the conventional method.

In this sample, the hydrofluoric acid concentration was 1% (% by weight), 2-propanol was added as a surfactant at a concentration of 1% (% by volume), and the solution was treated at room temperature. Here, the specific gravity of 2-propanol at room temperature (27 ° C.) is 0.8, and the amount of 2-propanol added is equivalent to 0.8% (% by weight). For the drying of the wafer, all the methods of blowing off and drying by rotating the semiconductor substrate at a high speed were used, and the drying method using 2-propanol vapor was not used. Except for the dilute hydrofluoric acid treatment, exactly the same two processes were used. In addition, As was used as the substrate impurity, and the concentration at the bonding interface was adjusted to be 6 × 10 ¹⁷ cm ⁻³ .

According to the present invention, the leakage current of the pn junction is smaller at all the cumulative frequencies in the dilute hydrofluoric acid treatment with the addition of 2-propanol. It has become smaller. It has been found that this leak current component is an isolated leak source scattered in the pn junction, which coincides with the model of a defective junction due to particles, and a decrease in leakage indicates that the number of isolated leak sources is reduced. Was.

Further, by forming a pn junction by the method of this embodiment, the junction depth is kept at 20 nm or less, and the leak current is suppressed to 1 × 10 ⁻⁸ A / cm ² or less at a failure rate of 1% or less. I could do it.

FIG. 9 shows a comparison example of the leak current between the present embodiment and the conventional example under various conditions of different prototype lots. Here, a point where the cumulative frequency becomes 95% is taken as the leak current, and the leak current caused by the isolated leak source is compared. Also, the vertical axis of FIG. 9 shows the leak current of the pn junction formed by the process flow of FIG. 8, and the horizontal axis shows the leak current of the pn junction formed by the conventional method. Also, ○ in the figure
Is a sample in which the leakage current on the vertical axis was treated by adding 0.2% (vol%) of 2-propanol as a surfactant, and the triangle in the figure indicates that the leakage current on the vertical axis was 2% as the surfactant. -
This is a sample treated by adding 1% (vol%) of propanol. Further, the annealing time and the temperature of the solid-phase diffusion are shown in the figure. Here, the dotted line is an eye guide when the leakage current of the embodiment and the conventional example are equal,
It was found that the example was able to reduce the leak current as compared with the conventional example.

FIG. 9 demonstrates that when 2-propanol was used as the surfactant, the leakage current was reduced in the range of 0.2% to 1% by weight. Also,
It was demonstrated that the solid-state diffusion annealing temperature was reduced between 600 ℃ and 700 ℃. In this example, an example using 2-propanol as the surfactant was shown.However, alcohols having a molecular weight of 2-propanol or less, that is, 1-propanol, methanol, and ethanol may be used as the surfactant. it can. Furthermore, even if these alcohols remain on the semiconductor surface 2 during the deposition of the second semiconductor layer 5, the interface products have the same or low molecular weight as in the case of 2-propanol. Not bring.

In the pn junction formed in this embodiment, the etching amount of the semiconductor substrate 2 is suppressed to 3 nm or less, which is enough to be consumed for forming a chemical oxide film with a mixed solution of hydrochloric acid and hydrogen peroxide solution. It can be formed by a heat process at 750 ° C. or lower throughout the entire bonding process of this embodiment.

On the other hand, the conventional ion implantation method requires an amorphous layer on the surface to prevent channeling, and requires a heat treatment at 850 ° C. or higher to eliminate ion implantation defects. Therefore, unlike the ion implantation, the method of the present embodiment can create a pn junction without significantly changing the substrate impurity profile and the substrate shape.

Further, in the method of the present embodiment, for example, an alkaline cleaning liquid is not used in a state where the semiconductor substrate 2 is exposed, unlike the treatment with an ammonia-hydrogen peroxide aqueous solution. Therefore, a pn junction can be formed without etching the semiconductor substrate 2. Furthermore, there is no problem that the wafer becomes cloudy when the second semiconductor layer 5 is deposited, which is a problem with the alkaline processing liquid.

Further, the amount of 2-propanol to be added is 2
-Less than a propanol wafer dryer, and less waste load on the environment.

In the pn junction formed in this embodiment, the number of the hydrophobic adsorbents 4 attached to the boundary between the semiconductor substrate 2 and the second semiconductor layer 5 can be reduced. Since the hydrophobic adsorbent 4 is made of, for example, carbon atoms and has a bond length different from the lattice constant of the semiconductor, the crystallinity of the semiconductor deteriorates. Therefore, for example, the lattice mismatch is introduced to be a source of an oxygen-induced stacking fault (Oxidation Induced Stacking Fault) -like stacking fault or a dislocation crystal defect. However, in this embodiment, the generation of the defect can be suppressed. Furthermore, Fe
Adsorbate 4 containing metallic impurities such as Ni and Ca
Can be reduced, and the formation of defect levels in the forbidden band of the semiconductor can be prevented. Therefore, even if the depletion layer end of the pn junction reaches the region of the hydrophobic adsorbate 4, for example,
Like a generated recombination current, an increase in leak current through a defect level can be suppressed.

In the portion where the hydrophobic adsorbate is adsorbed,
Although the segregation coefficient and impurity diffusion rate of the solid-phase diffusion are different from those of the non-adsorbed portion, the diffusion layer having a more uniform junction depth can be formed by reducing the number of hydrophobic adsorbates.

Further, since the surfactant is added, bubbles adhering to the surface of the semiconductor substrate 2 in the dilute hydrofluoric acid aqueous solution are easily released, and the etching residue of the silicon oxide film due to the bubbles is reduced. A pn junction can be formed more reliably. In fact, in the sample shown in FIG. 9, the probability of a pattern having an etching residue due to bubbles in the sample without the addition of the surfactant was 4%, whereas the etching residue in the sample with the addition of the surfactant was 1%. % Or less.

Since the surface of the semiconductor substrate 2 and the surface of the insulator substrate become hydrophilic similarly to the surface of the insulator substrate, even if the area of the silicon region is increased, a part of the cleaning water is rolled up when the wafer is dried, and the semiconductor 2 and the insulating film are removed. The problem that water remains near the interface with 3 is reduced. Therefore, defects in which organic substances and metals contained in the residual cleaning water adhere to the vicinity of the interface between the semiconductor 2 and the insulating film 3 are reduced. In fact, in the sample shown in FIG. 9, the probability of the pattern with water residue in the sample without the addition of surfactant is
The residual water was less than 1% in the sample to which the surfactant was added, compared with 14%.

In this example, the surfactant was
Any organic substance having a hydrophilic group with a large adsorption energy and a molecular weight of 90 or less may be used. Thus, for example, not only R-OH type alcohols where R is an alkyl group, but also, for example, acetic acid CH ₃ C
May be a OOH, may be other R-COOH carboxylic acid, it may be R-COONH _4.

Further, in this embodiment, an example was shown in which amorphous silicon was deposited as the second semiconductor region. However, for example, single crystal silicon, polycrystalline silicon, porous silicon, amorphous silicon, SiGe mixed crystal, SiGeC
Mixed crystal, GaAs, W, Ta, Ti, Hf, Co, Pt,
The metal of Pd or its silicide can be used as a solid-phase diffusion source, and it is clear that the treatment of the present embodiment reduces interface defects. (Embodiment 2) The present embodiment relates to a structure of a pn junction formed by, for example, solid-phase diffusion and capable of keeping a leakage current small even if the impurity concentration of the semiconductor substrate 2 is increased. . Conventionally, when boron exceeding the solid solubility is added to the second semiconductor layer 5 and the p-type diffusion layer 6 is formed by solid-phase diffusion of boron at a temperature of 750 ° C. or less, The impurity distribution of boron in diffusion layer 6 was not clear.

This time, for the first time, we succeeded in obtaining a solid-phase diffusion boron profile at 700 ° C. and 600 ° C. by diffusion for about several hours, and made it possible to design a device to reduce the leak current.

FIG. 10 shows measurement data of the depth and the boron concentration of a pn junction formed using the process described in the first embodiment as an example. The horizontal axis indicates the depth where the boundary between the semiconductor substrate 2 and the second semiconductor layer 5 is 0, and the direction into the semiconductor substrate 2 is positive, and the positive region is the semiconductor substrate 2.
Alternatively, the region 6 and the negative region indicate the second semiconductor layer 5.

In FIG. 10, x indicates data without annealing for solid phase growth, ● indicates data annealed at 600 ° C. for 2 hours,
□ indicates data obtained by annealing at 700 ° C. for 2 hours. Also, the thin solid line, thick solid line, and dotted line
The fitting curve is shown. The fitting curve displaces deeper from the interface at the same boron concentration as the annealing temperature increases, indicating that the profile of solid phase diffusion can be measured. Further, by extrapolating the fitting curve annealed at 700 ° C. for 2 hours to 0 nm, the diffusion of boron is increased by increasing the boron concentration (> 10 ²¹ cm ⁻³ ) of the second semiconductor layer 5 exceeding the solid solubility limit to the interface concentration. It has been found for the first time that a lower concentration of 10 ²⁰ cm ^-3 or less is diffused as an interface concentration, rather than as a diffusion.

In FIG. 10, a sample without annealing was used.
The reason that boron is observed in the positive region on the horizontal axis is due to the limit of the depth resolution of the measuring device. The resolution of this portion was corrected, and the actual profile was approximated by the complementary error function. It is.

FIG. 11 shows the semiconductor substrate 2 measured in the same manner.
The profile of the arsenic in it is also shown. From FIG. 11, assuming that the concentration of the substrate As is 6 × 10 ¹⁸ cm ⁻³ , the bonding depth is 8 nm in the heat treatment sample at 600 ° C. for 2 hours, and the bonding depth is 20 n in the heat treatment sample at 700 ° C. for 2 hours.
It can be seen that m is formed. These junction depths are
It has been found that a shallower junction can be formed, which is smaller than the minimum value (> 25 nm) of the reported example of the junction depth formed by conventional ion implantation.

Further, FIG. 11 and the results obtained by changing the diffusion time
From experiments, it was found that the boron impurity profile formed in the substrate 2 was
Il is given by C as depth x [m] and time t [s].₀* Erfc
[x / [2 (Dt)^0.5]]. here,
Erfc (z) is a complementary error function defined as Erfc (0) = 1.
C₀Is the interfacial boron concentration in the range of 600 ° C to 700 ° C,
3x10¹⁸cm^-3From 2x10¹⁹cm^-3Typical values up to
Has 1x10¹⁹cm^-3Becomes D is a diffusion constant, and 600
4x10 at ℃^{-twenty two}[m^Two/ s] to 3x10^{-twenty one}[m^Two/ s]
Typically 1x10^{-twenty one}[m^Two/ s]. Also, at 700 ℃
Diffusion coefficient is 4x10^{-twenty one}[m^Two/ s] to 9x10^{-twenty one}[m^Two/ s]
Typically between 6x10^{-2 1}[m^Two/ s]
You.

[0066] Using the above boron profile, if the concentration N _D of the semiconductor substrate 2 is given, the second semiconductor layer 5
When the junction depth Xj measured from the interface between the semiconductor substrate 2 and the semiconductor substrate 2 is set as follows, the end of the depletion layer of the pn junction is the hydrophobic adsorbate at the interface between the second semiconductor layer 5 and the semiconductor region 6. It can be designed not to reach the area of 4. 1) pn
The maximum value of the designed reverse bias of the junction is Vr, and the depletion layer width X _dep when Vr is applied to the pn junction is obtained from Vr and the impurity profile. 2) the donor surface-density that is included in the depletion layer in the case where the depletion layer to the interface is reached, N _D X _dep becomes, which the complementary error acceptor surface-density which is calculated from the function 0.5692 * C
_{Since 0} * 2 (Dt) ^0.5 is equal and C ₀ is given in advance as described above, the minimum required diffusion distance 2 (Dt) ^0.5 can be obtained. Incidentally, since the diffusion constant D is given in advance as described above, the minimum required diffusion time t can also be obtained. 3) N _D = C ₀ * Erfc [Xj / [2 (Dt) ^0.5 ]]
By solving, the minimum required Xj can be obtained. In practice, it is conceivable that Xj varies due to a decrease in the diffusion depth due to the hydrophobic deposit 4, for example,
It is desirable to design by increasing Xj from about 2 nm to about 10 nm.

FIG. 12 shows the relationship between the maximum value of the substrate impurity concentration required to prevent the depletion layer from reaching the interface and the minimum value of the junction depth, assuming a uniform doping structure of silicon. In this calculation, 5 × 10 ¹⁸ cm ⁻³ was used assuming that C ₀ is activated by half of the boron introduced into region 6. In the figure, the solid line shows the case where the reverse bias of the pn junction is 1 V, and the dotted line shows the case where the reverse bias is 3 V. As the bias voltage increases, the required junction depth also increases. Ten
^In the conventional diffusion calculation in which the impurity density exceeding the solid solubility limit of the second semiconductor layer 5 of ²¹ cm ⁻³ or more is considered to be equal to C _{0 of the} semiconductor region 6, the necessary junction depth Xj in FIG. As a result, the depletion layer reaches the interface between the second semiconductor layer 5 and the semiconductor region 6 and the leakage cannot be reduced.
The width of the depletion layer was also different. By using the diffusion constant D and the interfacial solid solubility C ₀ of this embodiment, the second
A defect that a depletion layer reaches the interface between the semiconductor layer 5 and the semiconductor region 6 to increase leakage can be more accurately reduced. Further, even if the impurity density of the semiconductor layer 5 is changed, the impurity concentration of the semiconductor region 6 is constant in a solid solution of C ₀ in the solid phase diffusion temperatures. For this reason, the concentration of the impurity layer in the semiconductor layer can be made more constant than in the ion implantation method,
The p-type diffusion layer 6 can be formed with more controllability.

The structure of the present embodiment is not limited to the structure formed by the dilute hydrofluoric acid pretreatment process using the surfactant as in the first embodiment, but also to the conventional dilute hydrofluoric acid to which no surfactant is added. It was verified that the same holds true for the solid-phase diffusion pn junction formed in the acid pretreatment process. Further, in the structure of the present embodiment, as shown in the profile of the sample annealed at 600 ° C. for 2 hours in FIG. 10, in the solid phase diffusion, the boron concentration is 10 ¹⁷ cm ⁻³ like the diffusion layer formed by ion implantation.
Defect enhancement due to excess interstitial Si atoms in the following regions
It was found for the first time that no significant increase in junction depth due to d Diffusion was observed. As a result, the junction depth can be kept smaller than in the case of pn junction formation by ion implantation, furthermore, dislocations and stacking faults caused by excessive interstitial atoms can be prevented, and pn junctions with less junction leak defects can be prevented. A bond can be formed. (Embodiment 3) In this embodiment, a very shallow pn junction formed by solid-phase diffusion described in Embodiments 1 and 2 is used for forming a MISFET.
The structure and manufacturing method used for a part of the source / drain electrode of FIG.

In this method, amorphous silicon doped with boron to a solid solubility or higher is deposited on the entire surface and selectively crystallized only on the substrate silicon, thereby selectively forming a high-concentration selective epitaxial growth film on the source and drain portions. It is characterized by forming.

FIG. 13 is a structural sectional view of a third embodiment of the present invention.

First, a gate insulating film 12 made of, for example, a silicon oxide film, an oxynitride film, or a silicon nitride film is formed on a semiconductor layer 15 made of, for example, single crystal n-type Si having a (100) plane orientation. Through, for example, poly Si,
A gate electrode 11 made of amorphous Si, TiN, W, Pt, RuO ₂ , IrO ₂ is formed. In the region of the semiconductor layer 15 on both sides of the gate electrode, for example, a source diffusion region and a drain diffusion region 21 formed by solid-phase diffusion of B or In having conductivity opposite to that of the semiconductor layer 15 are formed. Being p-type M
ISFET is formed. Further, in a deep portion of the semiconductor layer 15 below the p-type region 21 farther from the gate electrode, a semiconductor region having the same conductivity as the region 21 in contact with the region 21 in order to reduce the surface resistance of the source / drain region. 16 are formed.

Further, a single crystal semiconductor region 19 made of, for example, Si, SiGe, or SiGeC to which B or In is added is formed on the upper part of the 21 layer. This area is the gate insulating film
It is formed above the interface between the semiconductor layer 15 and the semiconductor layer 15 in the stacking direction, and has a so-called elevated source / drain structure. P-type impurity concentration of the semiconductor region 19, and a solid solubility or more, for example, in the case of boron, 10 ²⁰ cm ^-3 or more, in the case of indium and 2x10 ¹⁸ cm ^-3 or more. Further, an insulator film 13 made of, for example, a silicon oxide film or a nitride film is formed on a side wall of the gate insulating film 12 on which the gate electrode 11 is not formed. In addition, on the side wall of the insulating film 13,
An insulating film 22 made of a silicon oxide film or a nitride film is formed. Further, a conductor layer 23 made of, for example, cobalt silicide, nickel silicide, or titanium silicide is formed on the upper surface of the semiconductor region 19 where the insulating film 22 is not formed. The conductor layer 23 may be formed to reach the inside of the p-type source / drain semiconductor region 16. In this case, the conductor layer 23 is in contact with the n-type semiconductor layer 15 by covering the lower surface of the conductor layer 23 with the region 16. You need to avoid it. On the upper surface of the gate electrode 11, a conductor layer 23 'made of, for example, cobalt silicide, nickel silicide, or titanium silicide is formed. Further, in the region of the semiconductor layer 15 other than the p-type MISFET, for example,
An element isolation film 20 having an upper surface made of a silicon oxide film is formed.

Next, a manufacturing process of the semiconductor structure of this embodiment will be described with reference to FIGS.

First, for example, when the phosphorus concentration is 10^Fifteencm^-3N-layer
A semiconductor with a Si (100) plane as the main plane
Prepare region 15. Next, 1 phosphorus is added to the n-type semiconductor region 15.
0¹²~Ten^Fifteencm^-2Ion implantation and diffusion into the well
May be optimized. The energy of ion implantation is, for example,
50 eV or more and 1000 eV or less. The concentration of these well regions is 10
^Fifteencm^-3~Ten¹⁹cm^-3And it is sufficient.

Next, for example, an element isolation 20 composed of trench isolation or LOCOS isolation is formed. It is desirable that the upper surface of the element isolation film 20 be made of a silicon oxide film in order to selectively form the region 19. Next, phosphorus, arsenic, and antimony may be ion-implanted into the n-type semiconductor region 15 to diffuse the well and optimize the concentration.

Next, the surface of the semiconductor layer 15 is, for example, 0.5
The gate insulating film 12 is formed by oxidizing or nitriding
Polycrystalline silicon, amorphous silicon to become the gate electrode 11
Or a film 11 made of SiGe mixed crystal, for example, 10 to 200 n
m Deposit on the entire surface. The gate insulating film 12 and the gate electrode
Instead of the pole 11 forming step, for example, TiO_TwoAnd Al _TwoO_Three,is there
Or tantalum oxide film, strontium titanate or titanium
Gate made of barium titanate and lead zirconium titanate
An insulating film 12 is deposited on the entire surface to a thickness of 10 to 200 nm. further,
For example, poly Si, amorphous Si, TiN, W, Pt, RuO_TwoAlso
Is IrO_TwoGate electrode 11 consisting of 10 to 200 nm
May be stacked.

Further, after a silicon oxide film serving as the insulating film 14 is formed, for example, by depositing the entire surface of 2 to 100 nm or oxidizing or nitriding the film 11, the insulating film 14 and the conductive film 11 are insulated by lithography and reactive ion etching. Membrane 12
The gate electrode is formed by processing to reach the upper part.

Next, a silicon oxide film serving as the insulating film 13 is entirely deposited, for example, in a thickness of 2 to 50 nm and then processed by anisotropic etching to leave the side wall insulating film 13 on the steep side wall of the gate electrode 11. The shape shown in FIG. 14 is obtained.

Next, for example, a silicon oxide film or a silicon nitride film serving as the insulating film 17 is formed by, for example, 5 to 100 nm full-surface deposition, and then processed by anisotropic etching, so that the side wall insulating film 13 is raised. The insulating film 17 is left on the side wall. Examples of the combination of the insulating films 13 and 14 and the insulating film 17 include, for example, a silicon oxide film and a silicon nitride film, or a silicon thermal oxide film and a silicon deposited oxide film, a silicon oxide film and BPSG, a combination of BSG and PSG, and the like. ,film
Desirably, the film 17 can be selectively etched leaving the film 13 and the film 14.

Thereafter, B or BF ₂ is accelerated at an acceleration voltage of 1 to 100 eV, 10 ¹³
~ 10 ¹⁶ cm ^-2 ion implantation, for example, at 700-1100 ° C, 0.01 ~
By heating in an Ar or N ₂ atmosphere for 60 min, for example, the p-type region 16 is formed, and the shape shown in FIG. 15 is obtained. p-type region
The depth of 16 is between 0.03 and 0.3 μm, and the thickness of the insulating film 17 is adjusted so that a deep p-type layer does not reach directly below the gate electrode 11. Thereafter, for example, when the insulating film 17 is a silicon oxide film or BPSG, BSG or PSG, a dilute hydrofluoric acid aqueous solution or ammonium fluoride solution, hydrofluoric acid vapor, or when the insulating film 17 is a silicon nitride film, CHF By etching with a mixed gas of ₃ and O ₂ , CH ₂ F ₂ and CH ₃ F, the insulating film 17 is selectively removed while leaving the insulating films 13 and 14 surrounding the gate electrode 11.

When the film 12 is a silicon oxide film, a diluted hydrofluoric acid aqueous solution or ammonium fluoride solution, hydrofluoric acid vapor, and when the film 12 is a silicon nitride film, a mixed gas of CHF ₃ and O ₂ , CH ₂ F ₂ , CH _{2 3} F
Plasma etching is performed, and when the film 12 is a titanium oxide film, a mixed solution of sulfuric acid and hydrogen peroxide solution, and the film 12 is formed of Al ₂ O ₃
In this case, etching is performed with BCl ₃ to expose the semiconductor substrate surfaces on both sides using the film 13 as a mask.

Further, for example, the pre-processing shown in the first embodiment
Method to reduce boron to 10^{Two 0}From 10^{twenty two}cm^-3Between
Amorphous Si added at a concentration of
Form. The thickness of the layer 18 is 2 to 50 nm,
The height of the upper surface of the electrode 11 should be lower than that of FIG.
Get a shape.

At this time, in the region serving as the source / drain of the layer 18, it is formed directly on the semiconductor substrate,
On the element 13 and the element isolation 20, the layer 18 is formed on the silicon oxide film. We have found that the semiconductor layer 18 formed on the silicon oxide film contains at least 10 ¹⁸ cm ^{-3 of} oxygen within a thickness of 20 nm from the interface between the silicon oxide film and the semiconductor layer 18.

In such a high oxygen concentration region, even if heat treatment is performed for a short time, nucleation and recrystallization are inhibited by oxygen, and boron impurities are not activated. On the other hand, the layer 18 formed on the semiconductor layer 15 is epitaxially grown from the single-crystal semiconductor substrate 15 side by a short heat treatment to be single-crystallized to keep the oxygen concentration low. It becomes layer 19.

Thus, following the deposition of layer 18, N ₂ or Ar
Heat treatment between 500 ° C and 750 ° C in an inert gas such as
Perform for t minutes. Here, the annealing temperature is T [K], and the thickness of the layer 18 is
If x [nm], t is t> x / [1.18x10 ¹⁶ * exp (−2.89x1
0 ⁴ / T)], the amorphous semiconductor layer 18 on the (100) plane of the semiconductor layer 15 becomes single-crystallized. This means that, for example, for a 50 nm amorphous silicon
In the case of ° C., t> 12 seconds may be set.

FIG. 19 shows measured values of annealing time and resistance at 600 ° C. of boron-added amorphous Si having a thickness of 50 nm formed on SiO ₂ and single crystal Si on the same substrate. It can be seen that the sheet resistance of the boron-added semiconductor region formed on single-crystal Si is almost constant at 400 W / sheet for 0.5 hours or longer, and that boron is activated to a solid solubility or higher for 0.5 hours or longer.

On the other hand, it was found that the sheet resistance of the boron-added semiconductor region on SiO ₂ was 1 MW / sheet or more in the annealing time of 0.5 hour, and boron was hardly activated. Therefore, for example, the annealing temperature is 600 ° C., and the annealing time t is
If the time is set to 12 seconds or more and within 30 minutes, the boron-added semiconductor region 18 on the sidewall oxide film 13 and the boron-added semiconductor region 18 on the element isolation film 20 are in a state where boron is not activated.

On the other hand, the amorphous semiconductor layer 18 on the surface of the semiconductor layer 15 (100) is monocrystallized to form a single crystal semiconductor region 19. Thus, the shape shown in FIG. 17 is formed.

After that, half of the solid solution was added with boron.
When the conductor layer 18 is used, CF_FourAnd O _TwoMixed gas
Inactive semiconductor by Zuma etching
The body layer 18 was selectively etched to activate boron.
Discovered that the single crystal semiconductor region 19 can be left
Was. Here, the single crystallization occurs from the semiconductor layer 15 side and [11
1] The surface has the slowest selective growth rate. So especially semiconductors
The substrate is the [100] plane, and gate processing is performed in parallel with the <100>
By turning, the gate side as shown in FIG.
A [111] plane is formed on the wall and goes upward from the gate side wall
Can be formed according to
Between the gate and the drain, and between the gate and the drain.
The inter-volume can be kept small.

Further, the boron added to the semiconductor layer 19 is diffused into the n-type semiconductor region 15 by performing a heat treatment at 500 ° C. or more and 750 ° C. or less for 10 minutes to 10 hours in an inert gas such as N ₂ or Ar. Then, a p-type diffusion layer 21 is formed. The depth of the p-type diffusion layer is, for example, between 5 nm and 70 nm, and the diffusion time is
Typically, it is desirable that the p-type region 21 be formed so as to reach below the gate electrode 11 in order to increase the current driving capability.

Further, for example, a silicon oxide film or a silicon nitride film is deposited on the entire surface to a thickness of 10 to 300 nm, and an insulating film 22 is formed on the side wall of the side wall insulating film 13 which is formed by anisotropic etching. Further, using the film 22 as a mask, for example, after removing the insulating film 14 on the gate electrode 11 by etching with an ammonium fluoride solution or dilute hydrofluoric acid, silicide or metal is selectively formed on the source / drain semiconductor regions 19 and 11. To form electrodes 23 and 23 '. For this, for example, Ni, Co or Ti is deposited on the entire surface at 0.01 to 0.3 μm and 600
NiSi, CoSi or TiSi are selectively formed on the source / drain 19 and 11 by passing through a heating step of more than one degree, and the remaining metal is removed by etching with, for example, an aqueous solution of sulfuric acid and hydrogen peroxide. Complete the structure.

This embodiment has the following features. 1) A semiconductor region 19 doped with a p-type impurity more than the solid solubility is formed on the upper surface of the source / drain diffusion layer 21 and the gate electrode
11 Not formed up to the height. Therefore, the capacitance between the semiconductor region 19 and the gate electrode 11 is kept small, and the MISFET can operate at higher speed. Further, the leakage current between the gate electrode and the source / drain electrode can be kept small. Further, since the semiconductor region 19 to which the p-type impurity is added to the solid solution or more is not formed on the element isolation region 20, the leakage current between the transistors sandwiching the element isolation region 20 can be kept small. In addition, the semiconductor region 19
Is formed in a self-aligned manner on the surface of the semiconductor region not covered with the gate sidewall insulating film 13, so that there is no problem of an increase in source / drain resistance due to misalignment or an increase in the source / drain area. 2) The boundary between the semiconductor region 19 doped with p-type impurities above the solid solubility and the semiconductor region 21 doped with p-type impurities below the solid solubility forms a main plane up to the gate end regardless of the shape of the upper surface of the semiconductor region 19. While the gate edge above the semiconductor region 19 can form a forward taper. El by selective epitaxial
In the conventional method of forming a source / drain layer having a desired impurity concentration by ion-implanting boron or indium into the evated layer 19 after the growth of the evated layer 19, the impurity is implanted along the taper. A problem arises that the depth is increased and the short channel effect is deteriorated. However, in the present embodiment, the problem that the short channel effect deteriorates is solved. 3) The manufacturing method does not use selective deposition such as selective epitaxial growth when forming the layer 18. Therefore, the loading effect of changing the film thickness due to the change in pattern density, which is a problem in the selective growth method, can be reduced, and the semiconductor layer 19 having a more uniform thickness can be formed. Further, the problem of abnormal nucleation on the silicon oxide film does not occur, and the gate electrode 11
And the source-drain layer can be reduced. Further, an impurity exceeding the solid solubility can be easily added as the layer 19, and a source / drain electrode with lower resistance can be formed. 4) The method of manufacturing the source / drain regions 21 and 19 includes a pre-deposition treatment of the film 18.
It can be formed at a low temperature of 500-750 ° C. In the conventional selective epitaxial growth method, to remove the silicon surface oxide film
Heating at 850 ° C. or higher, for example, in a hydrogen atmosphere has been required. However, this method is not necessary. For example, diffusion of channel impurity ions can be suppressed. In addition, since the lower limit of the temperature increases the limit value of the elastic deformation stress, dislocations are less likely to occur in the semiconductor layer 15. Further, since there is no need to heat in a hydrogen atmosphere, the problem that the gate insulating film 12 is reduced by hydrogen and the leak characteristic is deteriorated is reduced. Also,
It is known that the layer 19 to which boron is added more than the solid solubility limit is effective for, for example, gettering of the Fe element.
The joining characteristics can be improved.

The present invention is not limited to the above embodiments. Element isolation film and insulating film formation method itself,
Other methods for converting silicon into a silicon oxide film or a silicon nitride film, such as a method of implanting oxygen ions into deposited silicon or a method of oxidizing deposited silicon, may be used. The gate insulating film 12 is made of TiO ₂
Or Al ₂ O ₃ , or a tantalum oxide film, strontium titanate, barium titanate, lead zirconium titanate, or a stacked film thereof may be used. In the embodiment, an n-type Si substrate is assumed as the semiconductor substrates 2 and 15, but instead, a p-type Si substrate or an SOI silicon layer of an SOI substrate, or a single crystal semiconductor containing silicon such as a SiGe mixed crystal or a SiGeC mixed crystal is used. Any substrate may be used. Furthermore, the formation of the p-type semiconductor layer 5 on the n-type semiconductor substrate 2 has been described.
The n-type semiconductor layer on the type semiconductor substrate 2 may be replaced.In this case, the n-type in the above-described embodiment is replaced with p-type, the p-type is replaced with n-type, and the doping impurity species As, P, Sb I
It can be read as either n or B. Further, the second semiconductor layer 5 can use a Si semiconductor, a SiGe mixed crystal, or a SiGeC mixed crystal, and may be a polycrystal instead of a single crystal, or may have a laminated structure of these. In addition, the semiconductor layer 18
Can be made of amorphous Si, amorphous SiGe mixed crystal, or amorphous SiGeC mixed crystal, and may have a laminated structure of these.

In the first embodiment, a mixed gas of disilane and diborane gas is used as a material gas for forming the second semiconductor thin film. For example, silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), _{GeH 4, SiCl 4, SiF 4} , Si 2 H 4 C
l ₂ , SiH ₂ F ₂ , Si ₂ H ₂ Cl ₄ , Si ₂ Cl ₆ , SiH ₄ F ₂ , SiH ₂ F ₄ and
Si ₂ F ₆ or a mixed gas of these may be used.

Further, when forming the p-type impurity-added semiconductor thin film 5, BCl ₃ or BF _{3 is used} instead of the diborane gas.
May be used. When adding an n-type impurity to the semiconductor thin film 5, PH ₃ or AsH ₃ or a halide containing phosphorus or arsenic may be mixed.

In the embodiment, only the method of forming the pn junction has been described.
It is easy to use for the junction between the source and drain electrodes of the MOSFET of -126802 and the substrate. In this case, Japanese Patent Application H8-12680
The pretreatment for depositing boron-added silicon in the second process may be replaced with the pretreatment of this embodiment.

In addition, various modifications can be made without departing from the spirit of the present invention.

[0098]

According to the present invention, a very shallow pn junction having no leak current can be formed.

[Brief description of the drawings]

FIG. 1 shows a conventional pn junction process.

FIG. 2 shows a conventional pn junction process.

FIG. 3 is a diagram showing a conventional pn junction process.

FIG. 4 is a diagram showing a pn junction process of the present invention.

FIG. 5 is a diagram showing a pn junction process of the present invention.

FIG. 6 is a diagram showing a pn junction process of the present invention.

FIG. 7 is a diagram showing a pn junction process of the present invention.

FIG. 8 is a diagram showing the effect of the diluted hydrofluoric acid treatment with a surfactant according to the present invention.

FIG. 9 is a diagram showing a leakage current when the surfactant concentration and the annealing time are changed.

FIG. 10 shows a measurement profile of boron concentration of a pn junction formed by solid-phase diffusion of boron.

FIG. 11 is a profile in which spectrum spread is corrected by measuring a pn junction of solid-phase diffusion of boron.

FIG. 12 is a diagram showing the relationship between the minimum junction depth for preventing junction leakage and the substrate concentration in Example 2.

FIG. 13 is a sectional view of a semiconductor device according to a third embodiment;

FIG. 14 is a sectional view illustrating a manufacturing process of the semiconductor device of the third embodiment;

FIG. 15 is a sectional view showing a manufacturing step of the semiconductor device of the third embodiment.

FIG. 16 is a sectional view illustrating a manufacturing process of the semiconductor device of the third embodiment.

FIG. 17 is a sectional view illustrating a manufacturing process of the semiconductor device of the third embodiment;

FIG. 18 is a sectional view illustrating a manufacturing process of the semiconductor device of the third embodiment;

FIG. 19 is a diagram showing the recrystallization annealing time dependence of the sheet resistance of boron-doped silicon.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Treatment liquid 2 ... Semiconductor substrate 3 ... Element separation film 4 ... Hydrophobic adsorbent 5 ... Semiconductor layer 6 ... Diffusion area 7 ... Dilute hydrofluoric acid + surfactant containing aqueous solution 8 ... Surfactant 11 ... Gate electrode 12 ... Gate Insulating film 13 ... Insulating film 14 ... Insulating film 15 ... Semiconductor region 16 ... Source / drain region 17 ... Insulating film 18 ... Amorphous silicon layer 19 ... Semiconductor layer 20 ... Element isolation film 21 ... P type region 22 ... Insulating film 23 ... Electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F040 DA01 DA11 DA12 DC01 DC10 EC01 EC04 EC07 EC08 EC13 ED03 ED04 EF01 EF02 EF11 EH02 EH07 EK01 EK05 FA03 FA05 FA07 FA16 FA17 FA19 FB03 FB07 FB08 FC00 FC05 FC22

Claims (7)

[Claims] A surface of a first semiconductor of a first conductivity type containing silicon is coated with hydrogen fluoride (0.1% to 10% by weight) and a surfactant (0.01% to 10% by weight). Immersing in an aqueous solution consisting of: removing the oxide film formed on the surface of the first semiconductor; coating the surface of the first semiconductor with the surfactant; and coating the surface with the surfactant. Depositing a second semiconductor of a second conductivity type on the surface of the first semiconductor; and forming a second conductivity type inversion region in the first semiconductor by solid phase diffusion from the second semiconductor. A method of manufacturing a semiconductor device. 2. The method according to claim 1, wherein the surface of the first semiconductor of the first conductivity type containing silicon is coated with hydrogen fluoride (0.1% to 10% by weight) and a surfactant (0.01% to 10% by weight). Immersing in an aqueous solution consisting of: removing the oxide film formed on the surface of the first semiconductor; coating the surface of the first semiconductor with the surfactant; and coating the surface with the surfactant. Depositing an amorphous semiconductor on a surface of a first semiconductor; and forming an inversion region of a second conductivity type in the first semiconductor by crystallizing the amorphous semiconductor. . 3. The method according to claim 1, wherein the surfactant comprises an alcohol containing an alkyl group and has a molecular weight of 50 or more and 90 or less. 4. The method according to claim 3, wherein said surfactant comprises propanol. 5. The step of depositing the amorphous semiconductor comprises:
3. The method according to claim 2, wherein the temperature is 400 [deg.] C. or lower. 6. The method according to claim 5, wherein the step of crystallizing the amorphous semiconductor is performed at 750 ° C. or lower. 7. A semiconductor device according to claim 2, wherein said crystallized semiconductor region is doped with a second conductivity type impurity at a temperature equal to or higher than a solid solubility at a temperature in a step of crystallizing said amorphous semiconductor.
The manufacturing method of the semiconductor device described in the above.