JP2001044627A - Wiring board and manufacture thereof - Google Patents
Wiring board and manufacture thereofInfo
- Publication number
- JP2001044627A JP2001044627A JP21832399A JP21832399A JP2001044627A JP 2001044627 A JP2001044627 A JP 2001044627A JP 21832399 A JP21832399 A JP 21832399A JP 21832399 A JP21832399 A JP 21832399A JP 2001044627 A JP2001044627 A JP 2001044627A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- layer
- lower layer
- insulating layer
- tin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
- H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
- H05K3/384—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0703—Plating
- H05K2203/072—Electroless plating, e.g. finish plating or initial plating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は,導体層の上に絶縁
層を積層してなる配線基板及びその製造方法に関する。
更に詳細には,導体層とその上の絶縁層との確実な密着
を図った配線基板及びその製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board formed by laminating an insulating layer on a conductor layer, and a method of manufacturing the same.
More specifically, the present invention relates to a wiring board which ensures the close contact between a conductor layer and an insulating layer thereover, and a method for manufacturing the same.
【0002】[0002]
【従来の技術】従来より,導体層と絶縁層とを積層する
ことにより配線基板が製造されている。ここにおいて通
常は,導体層の上に絶縁層を積層する前に,導体層の表
面が粗面化される。導体層と絶縁層との密着性を高める
ためである。粗面化は通常何らかの表面処理剤でエッチ
ングすることにより行われる。このための表面処理剤と
して,特開平7−292483号公報に記載されたもの
がある。同号公報では,その表面処理剤により銅などの
導体層の表面に深い凹凸を形成することができるとして
いる。2. Description of the Related Art Conventionally, a wiring board has been manufactured by laminating a conductor layer and an insulating layer. Here, the surface of the conductor layer is usually roughened before the insulating layer is laminated on the conductor layer. This is for improving the adhesion between the conductor layer and the insulating layer. Roughening is usually performed by etching with some surface treatment agent. As a surface treatment agent for this purpose, there is one described in JP-A-7-292483. In the same publication, the surface treating agent can form deep irregularities on the surface of a conductor layer such as copper.
【0003】[0003]
【発明が解決しようとする課題】しかしながら,前述の
表面処理剤で導体層の表面を粗面化しても,密着性はな
お不十分であった。例えば,後の工程で熱が加わったと
きに(部品実装のためのリフロー(230〜250℃)
など),導体層と絶縁層とが剥がれて膨れができてしま
うのである。その原因の一つとして粗面化後に導体層表
面が酸化されて酸化皮膜が形成されてしまうことが考え
られる。However, even if the surface of the conductor layer is roughened with the above-mentioned surface treating agent, the adhesion is still insufficient. For example, when heat is applied in a later process (reflow for component mounting (230 to 250 ° C)
Etc.), and the conductor layer and the insulating layer are peeled off and swelled. As one of the causes, it is considered that the surface of the conductor layer is oxidized after the surface is roughened to form an oxide film.
【0004】本発明は上記問題点を解決するためになさ
れたものである。すなわちその課題とするところは,導
体層表面と絶縁層との密着性を十分なものとする配線基
板の製造方法及び配線基板を提供するところにある。The present invention has been made to solve the above problems. That is, it is an object of the present invention to provide a method of manufacturing a wiring board and a wiring board which have sufficient adhesion between the surface of the conductor layer and the insulating layer.
【0005】[0005]
【課題を解決するための手段】この課題を解決するため
になされた本発明は,導体層の表面の上に絶縁層を積層
することよる配線基板の製造方法において,導体層の表
面を粗面化し,粗面化された導体層の表面にスズ置換め
っきを施し,その後その導体層の上に絶縁層を積層する
ことを要旨とする。SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a method of manufacturing a wiring board by laminating an insulating layer on a surface of a conductive layer. The gist of the present invention is to apply tin displacement plating to the surface of a roughened and roughened conductor layer, and then to laminate an insulating layer on the conductor layer.
【0006】この方法では,まず,導体層の表面の粗面
化を行う。このとき,例えば,前述した表面処理剤を用
いることができる。これにより導体層の表面に深い凹凸
が形成される。しかし,このままの状態では,導体層の
表面に酸化皮膜が形成されてしまう。そこで,粗面化さ
れた上記導体層の表面に,スズ置換めっきを施す。これ
により,導体層の表面はスズに覆われるので,導体層の
表面における酸化皮膜の形成が防止される。その後,そ
の導体層の上に絶縁層を積層する。このため,導体層と
絶縁層とは酸化皮膜を介さずに直に密着する。以上によ
り,導体層と絶縁層との密着性を十分なものとすること
ができる。In this method, first, the surface of the conductor layer is roughened. At this time, for example, the above-described surface treatment agent can be used. Thereby, deep irregularities are formed on the surface of the conductor layer. However, in this state, an oxide film is formed on the surface of the conductor layer. Therefore, the surface of the roughened conductor layer is subjected to tin displacement plating. Thereby, since the surface of the conductor layer is covered with tin, formation of an oxide film on the surface of the conductor layer is prevented. After that, an insulating layer is laminated on the conductor layer. For this reason, the conductor layer and the insulating layer are in direct contact with each other without an oxide film. As described above, the adhesion between the conductor layer and the insulating layer can be made sufficient.
【0007】またこのとき,スズ置換めっきにおけるめ
っき厚を0.10〜0.13μmとすると良い。もし,
めっき厚が0.10μmよりも小さい場合,スズ置換め
っきがまだ不十分な状態である。従って,導体層の表面
と絶縁層との密着性向上の効果が十分に得られない。At this time, the plating thickness in the tin displacement plating is preferably set to 0.10 to 0.13 μm. if,
If the plating thickness is smaller than 0.10 μm, the tin displacement plating is still insufficient. Therefore, the effect of improving the adhesion between the surface of the conductor layer and the insulating layer cannot be sufficiently obtained.
【0008】また,置換めっきによりスズを導体層に付
着させるので,めっき厚が0.13μmよりも大きい場
合,凹凸状の導体層の表面のうちスズに覆われていない
部分の溶解が顕著になってしまう。これにより,凹凸状
の導体層の表面が崩れやすくなる。従って,導体層に絶
縁層を積層したとき,導体層の表面に形成された凹凸に
よるアンカー効果が弱くなるので,導体層の表面と絶縁
層との密着性向上の効果が十分に得られない。Further, since tin is adhered to the conductor layer by displacement plating, when the plating thickness is greater than 0.13 μm, dissolution of a portion of the surface of the uneven conductor layer which is not covered with tin becomes remarkable. Would. As a result, the surface of the uneven conductive layer is likely to collapse. Therefore, when the insulating layer is laminated on the conductor layer, the anchor effect due to the unevenness formed on the surface of the conductor layer is weakened, and the effect of improving the adhesion between the surface of the conductor layer and the insulating layer cannot be sufficiently obtained.
【0009】また,本発明の配線基板は,導体層の上に
絶縁層を積層してなる配線基板において,導体層の表面
が,粗面化されているとともにスズめっきが施されてオ
ーバーハング状をなすものである。Further, according to the wiring board of the present invention, in a wiring board formed by laminating an insulating layer on a conductor layer, the surface of the conductor layer is roughened and tin-plated to form an overhang. It is what makes.
【0010】ここで,オーバーハング状とは,例えば,
めっきされた金属スズが導体層表面の粗面化により形成
された突起の側面に凹凸状に析出して横方向に張り出し
ている状態である。Here, the overhang state is, for example,
This is a state in which plated metal tin is deposited on the side surfaces of the protrusions formed by roughening the surface of the conductor layer in an uneven manner and protrudes laterally.
【0011】本発明の配線基板では,オーバーハング状
のスズめっきの奥の部分に絶縁層の樹脂が入り込んでい
る。このため,後の工程で,導体層から絶縁層を剥がす
力が配線基板に働いても,オーバーハング状に張り出し
た部分とその奥に入り込んだ絶縁層の樹脂とが引っかか
っているため,上記絶縁層は上記導体層から容易に剥が
れない。従って,導体層と絶縁層との密着性は従来の配
線基板と比較してかなり高いものになる。In the wiring board according to the present invention, the resin of the insulating layer enters into the deep portion of the overhanging tin plating. For this reason, even if the force for peeling the insulating layer from the conductive layer acts on the wiring board in a later step, the overhanging portion and the resin of the insulating layer penetrating into the overhang shape are caught, so that the insulation The layer does not easily peel off from the conductor layer. Therefore, the adhesion between the conductor layer and the insulating layer is considerably higher than that of the conventional wiring board.
【0012】[0012]
【発明の実施の形態】以下,本発明を具体化した実施の
形態について,図面を参照しつつ詳細に説明する。ま
ず,原基板上に下層パターンを形成したものを準備す
る。ガラスエポキシ基板,またはBT(ビスマレイミド
トリアジン)樹脂からなる基板1に銅箔(18μm厚程
度)がラミネートされてなる銅貼積層板を出発材料とす
る。この銅貼積層板の銅箔に通常用いられる方法で,パ
ターンエッチングを施し,銅の下層パターン2を形成す
る(図1)。Embodiments of the present invention will be described below in detail with reference to the drawings. First, a substrate in which a lower layer pattern is formed on an original substrate is prepared. The starting material is a glass epoxy substrate or a copper-clad laminate obtained by laminating a copper foil (about 18 μm thick) on a substrate 1 made of BT (bismaleimide triazine) resin. Pattern etching is performed on the copper foil of the copper-clad laminate by a method usually used to form a copper lower layer pattern 2 (FIG. 1).
【0013】次に,下層パターン2の表面の粗面化を行
う。かかる粗面化は,表面処理剤としてCZ−8100
(メック株式会社製)を用いて行う。すると,図2に示
されるように,下層パターン2の表面は粗面化される。Next, the surface of the lower layer pattern 2 is roughened. Such surface roughening is performed by using CZ-8100 as a surface treatment agent.
(Manufactured by MEC Corporation). Then, as shown in FIG. 2, the surface of lower layer pattern 2 is roughened.
【0014】しかしながら,このままの状態では,下層
パターン2は酸化されて酸化皮膜が形成されてしまう。
従って,次に,粗面化された下層パターン2にスズ置換
めっきを行う。かかるスズ置換めっきは,ホウふっ化ス
ズとチオ尿素とを含有するめっき液を使用する。する
と,図3に拡大して示すように,粗面化によって下層パ
ターン2に形成された突起3の表面に,凹凸状に金属ス
ズのめっき層4が形成される。However, in this state, the lower layer pattern 2 is oxidized to form an oxide film.
Therefore, next, tin substitution plating is performed on the roughened lower layer pattern 2. For such tin displacement plating, a plating solution containing tin borofluoride and thiourea is used. Then, as shown in an enlarged manner in FIG. 3, a metal tin plating layer 4 is formed in an uneven shape on the surface of the projection 3 formed on the lower layer pattern 2 by roughening.
【0015】最後に,下層パターン2の上に層間絶縁層
5を形成する。この形成は,エポキシ系樹脂をベースと
したワニス状のものをロールコーティングで80μm塗
布する方法と,ドライフィルム(日立化成製BF−80
00,70μm厚)を真空ラミネータでコーティングす
ることにより行う方法とのいずれを行ってもよい。する
と,図4に示されるように層間絶縁層5が形成される。[0015] Finally, an interlayer insulating layer 5 is formed on the lower layer pattern 2. This formation is performed by a method of applying a varnish-like material based on an epoxy resin by roll coating to a thickness of 80 μm, or a dry film (BF-80 manufactured by Hitachi Chemical).
(Thickness of 00, 70 μm) by coating with a vacuum laminator. Then, an interlayer insulating layer 5 is formed as shown in FIG.
【0016】上記の方法で形成された配線基板は,図4
に示すように,基板1の上に,表面が粗面化された下層
パターン2が形成されている。そして下層パターン2の
表面にはスズ置換めっきが施されて,めっき層4(図6
参照)が形成されている。そして,めっきされた下層パ
ターン4の上には,層間絶縁層5が積層されている。
尚,図4では,めっき層4は下層パターン2や基板1等
よりも極めて薄いため図示されていない。また,下層パ
ターン2の表面部分を拡大した図6に示されるように,
下層パターン2の表面が粗面化されて突起3が形成さ
れ,更に,その突起3の表面に凹凸状にめっき層4が形
成されている。そして,めっき層4は突起3の側面にオ
ーバーハング状に形成されている。更に,層間絶縁層5
の樹脂は凹凸状のめっき層4の間に入り込んでいる。The wiring board formed by the above method is shown in FIG.
As shown in FIG. 1, a lower layer pattern 2 having a roughened surface is formed on a substrate 1. Then, tin displacement plating is applied to the surface of the lower layer pattern 2 to form a plating layer 4 (FIG. 6).
Reference) is formed. An interlayer insulating layer 5 is laminated on the plated lower layer pattern 4.
In FIG. 4, the plating layer 4 is not shown because it is extremely thinner than the lower layer pattern 2, the substrate 1, and the like. Further, as shown in FIG. 6 in which the surface portion of the lower layer pattern 2 is enlarged,
The surface of the lower layer pattern 2 is roughened to form the projections 3, and further, the plating layer 4 is formed on the surface of the projections 3 in an uneven manner. The plating layer 4 is formed on the side surface of the protrusion 3 in an overhang shape. Further, the interlayer insulating layer 5
Resin has entered between the uneven plating layers 4.
【0017】上記構成の配線基板では,下層パターン2
がスズのめっき層4に覆われているので,酸化皮膜が形
成されにくくなっている。従って,下層パターン2と層
間絶縁層5は酸化皮膜を介することなく密着している。
これにより,下層パターン2と層間絶縁層5とがより強
固に密着された配線基板が得られている。In the wiring board having the above structure, the lower layer pattern 2
Is covered with the tin plating layer 4, so that an oxide film is not easily formed. Therefore, the lower layer pattern 2 and the interlayer insulating layer 5 are in close contact with each other without an oxide film.
As a result, a wiring board in which the lower layer pattern 2 and the interlayer insulating layer 5 are more firmly adhered is obtained.
【0018】また,上記構成の配線基板によれば,図6
に示されるように,オーバーハング状に形成されためっ
き層4の奥に層間絶縁層5の樹脂が入り込んでいる。従
って,後の工程で,下層パターン2から層間絶縁層5を
剥がす力が配線基板に働いても,突起3の側面に形成さ
れたオーバーハング状のめっき層4の奥に入り込んだ層
間絶縁層5の樹脂が引っかかっているため層間絶縁層5
は容易に剥がれない。従って,下層パターン2と層間絶
縁層5との密着性は従来の配線基板と比較してかなり高
いものになる。According to the wiring board having the above structure, FIG.
As shown in the figure, the resin of the interlayer insulating layer 5 penetrates into the depth of the overhang-shaped plating layer 4. Therefore, even in a later step, even if a force for peeling the interlayer insulating layer 5 from the lower layer pattern 2 acts on the wiring board, the interlayer insulating layer 5 penetrating into the overhang-shaped plating layer 4 formed on the side surface of the protrusion 3. Of the interlayer insulating layer 5
Does not peel off easily. Therefore, the adhesion between the lower layer pattern 2 and the interlayer insulating layer 5 is considerably higher than that of the conventional wiring board.
【0019】さらに,スズ置換めっきの際における最適
なめっき厚を調べるために,スズ置換めっきによるめっ
き厚と,下層パターン2と層間絶縁層5との密着性との
関係の試験を行った。この試験は,0〜0.3μm厚の
種々のめっき厚範囲内でスズ置換めっきを施した配線基
板にリフローの熱を加え,膨れの発生率を測定をするこ
とにより行った。この試験の試験片として,携帯電話用
の配線基板を使用し,リフローの温度をIRリフローで
最大240℃とした。そして,めっき厚は配線基板にお
ける巨視的な単位面積当たりのスズ量から計算し,単位
面積当たりのスズ量はめっき時間により制御した。図5
は,その結果を示すグラフである。このグラフの縦軸は
リフロー後の配線基板の膨れの発生率(%)であり,横
軸はスズ置換めっきのめっき厚(μm)である。図5に
よれば,めっき厚が0.10〜0.13μmのとき,リ
フローによる膨れの発生率がほぼ0%になっている。従
って,このとき,下層パターン2と層間絶縁層5との密
着性が最も高いことが分かる。その理由として次のこと
が考えられる。Further, in order to examine the optimum plating thickness in the case of tin displacement plating, a test was performed on the relationship between the plating thickness by tin displacement plating and the adhesion between the lower layer pattern 2 and the interlayer insulating layer 5. This test was performed by applying heat of reflow to a wiring board plated with tin within a range of various plating thicknesses of 0 to 0.3 μm and measuring the occurrence of blistering. As a test piece for this test, a wiring board for a mobile phone was used, and the reflow temperature was set to a maximum of 240 ° C. by IR reflow. The plating thickness was calculated from the macroscopic amount of tin per unit area of the wiring board, and the amount of tin per unit area was controlled by the plating time. FIG.
Is a graph showing the results. The vertical axis of this graph is the occurrence rate (%) of swelling of the wiring board after reflow, and the horizontal axis is the plating thickness (μm) of tin displacement plating. According to FIG. 5, when the plating thickness is 0.10 to 0.13 μm, the occurrence rate of blister due to reflow is almost 0%. Therefore, at this time, it can be seen that the adhesion between the lower layer pattern 2 and the interlayer insulating layer 5 is the highest. The following can be considered as the reason.
【0020】すなわち,もし,0.10μmよりも小さ
い場合,スズ置換めっきがまだ不十分な状態である。従
って,下層パターン2と層間絶縁層5との密着性の効果
が不十分なものとなる。That is, if it is smaller than 0.10 μm, the tin displacement plating is still insufficient. Therefore, the effect of the adhesion between the lower layer pattern 2 and the interlayer insulating layer 5 becomes insufficient.
【0021】また,スズ置換めっきを行うと,スズが下
層パターン2に付着し,これに対応して下層パターン2
の銅がめっき液に溶解される。このため,図3におい
て,めっき厚が0.13μmよりも大きい場合,突起3
のうちスズに覆われていない部分の溶解が顕著になる。
これにより,突起3が崩れやすくなるため,この状態で
下層パターン2に層間絶縁層5を形成したとき,下層パ
ターン2に形成された突起3によるアンカー効果が弱
い。従って,下層パターン2と層間絶縁層5との密着性
の効果が不十分なものとなる。Further, when the tin displacement plating is performed, tin adheres to the lower layer pattern 2 and accordingly, the lower layer pattern 2
Of copper is dissolved in the plating solution. Therefore, in FIG. 3, when the plating thickness is larger than 0.13 μm, the protrusion 3
Of the parts not covered with tin, the dissolution becomes remarkable.
As a result, the projections 3 are easily broken, and when the interlayer insulating layer 5 is formed on the lower layer pattern 2 in this state, the anchor effect of the projections 3 formed on the lower layer pattern 2 is weak. Therefore, the effect of the adhesion between the lower layer pattern 2 and the interlayer insulating layer 5 becomes insufficient.
【0022】以上,詳細に説明したように,本実施形態
の配線基板の製造方法によれば,下層パターン2に厚さ
0.10〜0.13μmのスズ置換めっきを施したの
で,下層パターン2と層間絶縁層5とが強固に密着され
た配線基板を得ることができる。また,本実施形態で
は,粗面化された下層パターン2の表面に形成された突
起3の側面に凹凸状にめっき層4が形成されていること
により,層間絶縁層5が剥がれにくくなっているので,
下層パターン2と層間絶縁層5とがより強固に密着され
た配線基板が提供されている。As described in detail above, according to the method of manufacturing a wiring board of the present embodiment, the lower layer pattern 2 is plated with tin substitution with a thickness of 0.10 to 0.13 μm. A wiring board in which the and the interlayer insulating layer 5 are firmly adhered can be obtained. Further, in the present embodiment, since the plating layer 4 is formed on the side surfaces of the projections 3 formed on the surface of the roughened lower layer pattern 2 in an uneven manner, the interlayer insulating layer 5 is hardly peeled off. So
There is provided a wiring board in which the lower layer pattern 2 and the interlayer insulating layer 5 are more firmly adhered.
【0023】尚,本実施形態は単なる例示にすぎず,本
発明を何ら限定するものではない。従って,本発明の要
旨を逸脱しない範囲内での種々の変形,改良が可能であ
る。The present embodiment is merely an example, and does not limit the present invention. Therefore, various modifications and improvements can be made without departing from the scope of the present invention.
【0024】[0024]
【発明の効果】以上の説明からあきらかなように,本発
明によれば,導体層表面と絶縁層との密着性を十分なも
のとする配線基板の製造方法及び配線基板が提供されて
いる。As is apparent from the above description, according to the present invention, there is provided a method of manufacturing a wiring board and a wiring board which provide sufficient adhesion between the surface of the conductive layer and the insulating layer.
【図1】出発基板に下層パターンを形成した状態を示す
図である。FIG. 1 is a view showing a state in which a lower layer pattern is formed on a starting substrate.
【図2】下層パターンを粗面化した状態を示す図であ
る。FIG. 2 is a view showing a state where a lower layer pattern is roughened.
【図3】スズ置換めっきを施した下層パターンを拡大し
た図である。FIG. 3 is an enlarged view of a lower layer pattern subjected to tin displacement plating.
【図4】めっきされた下層パターンの上に層間絶縁層を
積層した状態を示す図である。FIG. 4 is a diagram showing a state in which an interlayer insulating layer is laminated on a plated lower layer pattern.
【図5】スズ置換めっきを施した配線基板にリフローの
熱を加えた場合における膨れの発生率を測定した結果を
示すグラフである。FIG. 5 is a graph showing the results of measuring the occurrence of blistering when a reflow heat is applied to a wiring board subjected to tin displacement plating.
【図6】
層間絶縁層を積層した下層パターンを拡大した図で
ある。FIG. 6
It is the figure which expanded the lower layer pattern which laminated the interlayer insulation layer.
3 突起 4 めっき層 5 層間絶縁層 3 Protrusion 4 Plating layer 5 Interlayer insulating layer
Claims (3)
配線基板の製造方法において,前記導体層の表面を粗面
化し,粗面化された前記導体層の表面にスズ置換めっき
を施し,その後その導体層の上に前記絶縁層を積層する
ことを特徴とする配線基板の製造方法。1. A method for manufacturing a wiring board, comprising laminating an insulating layer on a conductor layer, wherein the surface of the conductor layer is roughened, and the surface of the roughened conductor layer is plated with tin. And a method of manufacturing the wiring board, wherein the insulating layer is laminated on the conductor layer.
において,前記スズ置換めっきの際のめっき厚を0.1
0〜0.13μmとすることを特徴とする配線基板の製
造方法。2. The method for manufacturing a wiring board according to claim 1, wherein the plating thickness in the tin displacement plating is 0.1%.
A method for manufacturing a wiring board, wherein the thickness is 0 to 0.13 μm.
基板において,前記導体層の表面が,粗面化されている
とともにスズめっきが施されてオーバーハング状をなし
ていることを特徴とする配線基板。3. A wiring board comprising an insulating layer laminated on a conductor layer, wherein the surface of the conductor layer is roughened and tin-plated to form an overhang. Characteristic wiring board.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21832399A JP2001044627A (en) | 1999-08-02 | 1999-08-02 | Wiring board and manufacture thereof |
PCT/JP2000/004881 WO2001010178A1 (en) | 1999-08-02 | 2000-07-19 | Production method of wiring board and wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21832399A JP2001044627A (en) | 1999-08-02 | 1999-08-02 | Wiring board and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2001044627A true JP2001044627A (en) | 2001-02-16 |
Family
ID=16718059
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21832399A Pending JP2001044627A (en) | 1999-08-02 | 1999-08-02 | Wiring board and manufacture thereof |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP2001044627A (en) |
WO (1) | WO2001010178A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101184006B1 (en) | 2010-09-28 | 2012-09-19 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
JP2021002539A (en) * | 2019-06-19 | 2021-01-07 | Tdk株式会社 | Substrate with built-in electronic component and method of manufacturing the same |
WO2021200874A1 (en) * | 2020-03-30 | 2021-10-07 | 三菱マテリアル株式会社 | Bonded body and insulating circuit board |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3081026B2 (en) * | 1991-07-18 | 2000-08-28 | 古河サーキットフォイル株式会社 | Electrolytic copper foil for printed wiring boards |
JP3229923B2 (en) * | 1996-03-01 | 2001-11-19 | イビデン株式会社 | Multilayer printed wiring board and method of manufacturing the same |
-
1999
- 1999-08-02 JP JP21832399A patent/JP2001044627A/en active Pending
-
2000
- 2000-07-19 WO PCT/JP2000/004881 patent/WO2001010178A1/en active Application Filing
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101184006B1 (en) | 2010-09-28 | 2012-09-19 | 삼성전기주식회사 | Printed circuit board and manufacturing method thereof |
JP2021002539A (en) * | 2019-06-19 | 2021-01-07 | Tdk株式会社 | Substrate with built-in electronic component and method of manufacturing the same |
JP7342445B2 (en) | 2019-06-19 | 2023-09-12 | Tdk株式会社 | Electronic component built-in board and manufacturing method thereof |
WO2021200874A1 (en) * | 2020-03-30 | 2021-10-07 | 三菱マテリアル株式会社 | Bonded body and insulating circuit board |
JPWO2021200874A1 (en) * | 2020-03-30 | 2021-10-07 | ||
JP7260059B2 (en) | 2020-03-30 | 2023-04-18 | 三菱マテリアル株式会社 | Joined body and insulating circuit board |
Also Published As
Publication number | Publication date |
---|---|
WO2001010178A1 (en) | 2001-02-08 |
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