JP2001044073A - Thin-film capacitor and fabrication thereof - Google Patents
Thin-film capacitor and fabrication thereofInfo
- Publication number
- JP2001044073A JP2001044073A JP11217041A JP21704199A JP2001044073A JP 2001044073 A JP2001044073 A JP 2001044073A JP 11217041 A JP11217041 A JP 11217041A JP 21704199 A JP21704199 A JP 21704199A JP 2001044073 A JP2001044073 A JP 2001044073A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- layer
- electrode layer
- thin film
- lower electrode
- Prior art date
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- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は薄膜コンデンサとそ
の製造方法に係り、とくに基板上に下側電極層、誘電体
層、上側電極層を順次積層して形成するようにした薄膜
コンデンサとその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film capacitor and a method of manufacturing the same, and more particularly to a thin film capacitor formed by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer on a substrate and a method of manufacturing the same. About the method.
【０００２】[0002]
【従来の技術】電子機器の小型軽量化に伴って、このよ
うな電子機器に搭載される電子回路実装基板の小型化が
要求されている。そこで半導体集積回路の高集積化や、
電気配線の微細化、あるいはまた抵抗やコンデンサのよ
うな受動部品の小型チップ化が進められている。さらに
半導体集積回路素子や小型化された受動部品を電子回路
基板の両面に高密度に実装して多層構造としている。2. Description of the Related Art As electronic devices become smaller and lighter, there is a demand for smaller electronic circuit boards mounted on such electronic devices. Therefore, high integration of semiconductor integrated circuits,
Miniaturization of electrical wiring and miniaturization of passive components such as resistors and capacitors have been promoted. Further, semiconductor integrated circuit elements and miniaturized passive components are densely mounted on both sides of the electronic circuit board to form a multilayer structure.
【０００３】[0003]
【発明が解決しようとする課題】電子回路実装基板はよ
り一層の小型化と高密度化とが要求されており、上述の
ような受動部品の小型化や高密度実装化だけでは、その
要求を十分に満足することができなくなっている。そこ
でこのような要求を満足すべく、実装基板に受動素子を
内蔵化することが試みられている。この場合に受動素子
を印刷や蒸着等の方法で、厚膜、薄膜の形で多層基板の
内部に実装するものであって、このような方策によって
回路基板をより小型化することが可能になる。また抵抗
やコンデンサ等の受動部品を多層基板の内部に実装する
ことによって、部品間の電気配線が短くなり、高周波ノ
イズが低減されることになる。There is a demand for further miniaturization and higher density of electronic circuit boards, and the miniaturization and high-density mounting of passive components as described above alone are not sufficient. I am not satisfied enough. In order to satisfy such demands, attempts have been made to incorporate passive elements into a mounting substrate. In this case, the passive element is mounted inside the multilayer substrate in the form of a thick film or a thin film by a method such as printing or vapor deposition, and such a measure makes it possible to further reduce the size of the circuit board. . Also, by mounting passive components such as resistors and capacitors inside the multilayer substrate, electrical wiring between the components is shortened, and high-frequency noise is reduced.
【０００４】多層基板の内部に高容量の薄膜コンデンサ
を内蔵化させる場合には、誘電体としてＢａx Ｓｒ1-x
ＴｉＯ3 （ＢＴＳ）等の高誘電体を薄膜形成する必要が
ある。そしてこのような高誘電体層を形成する場合に
は、一般に５００℃以上の温度で上記の熱処理を行なわ
なければならない。このために受動素子内蔵基板とし
て、例えば特許第２７８４５５５号公報によって示され
るような高耐熱性のセラミック基板を用いるようにして
いる。ところがセラミック基板を用いると電子回路基板
の高コスト化になってしまい、用途が限定される問題が
ある。そこでセラミック基板に代えてマイカ基板を用い
ることが考察される。マイカ基板は低コストであって、
高耐熱性を有し、しかも高周波特性がよい利点がある。When a high-capacity thin-film capacitor is built in a multilayer substrate, Ba x Sr 1 -x is used as a dielectric.
It is necessary to form a thin film of a high dielectric such as TiO 3 (BTS). When such a high dielectric layer is formed, the above heat treatment must be generally performed at a temperature of 500 ° C. or higher. For this purpose, a high heat-resistant ceramic substrate as disclosed in, for example, Japanese Patent No. 28784555 is used as the passive element built-in substrate. However, when a ceramic substrate is used, the cost of the electronic circuit substrate increases, and there is a problem that the use is limited. Therefore, it is considered to use a mica substrate instead of the ceramic substrate. Mica substrates are low cost,
It has the advantage of high heat resistance and good high frequency characteristics.
【０００５】一方で薄膜コンデンサの電極としては一般
に高耐熱性であってしかも耐酸化性のＰｔ電極を用いる
ことが多い。しかしＰｔ電極は高コストであってしかも
エッチングし難いという問題がある。そこでこのような
Ｐｔ電極に代えて、Ｒｕ電極を用いることが例えばＪＡ
ＰＡＮＥＳＥ ＪＯＵＲＮＡＬ ＯＦ ＡＰＰＬＩＥＤ
ＰＨＹＳＩＣＳ ３５巻９Ｂ号４８８０〜４８８５頁
によって提案されている。しかしながらＲｕ系単体の電
極の場合には、基板との密着性が悪くなる問題がある。
一般に基板と電極膜との密着性が悪い場合には、それら
の間にＴｉ層等を導入することによって密着性を向上さ
せることが可能だが、Ｔｉを入れるとコストの増大が避
けられない。On the other hand, generally, a Pt electrode having high heat resistance and oxidation resistance is often used as an electrode of a thin film capacitor. However, there is a problem that the Pt electrode is expensive and difficult to etch. Therefore, a Ru electrode may be used instead of such a Pt electrode, for example, in JA.
PANSE JOURNAL OF APPLIED
PHYSICS, Vol. 35, No. 9B, pp. 4880-4885. However, in the case of a single Ru-based electrode, there is a problem that adhesion to a substrate is deteriorated.
Generally, when the adhesion between the substrate and the electrode film is poor, it is possible to improve the adhesion by introducing a Ti layer or the like between them, but if Ti is added, an increase in cost cannot be avoided.
【０００６】本発明はこのような問題点に鑑みてなされ
たものであって、基板と接触する下側電極層と基板との
密着性を改善するようにした薄膜コンデンサとその製造
方法を提供することを目的とする。The present invention has been made in view of the above problems, and provides a thin film capacitor capable of improving the adhesion between a lower electrode layer in contact with a substrate and the substrate, and a method of manufacturing the same. The purpose is to:
【０００７】[0007]
【課題を解決するための手段】本願の一発明は、基板上
に下側電極層、誘電体層、上側電極層を順次積層して形
成される薄膜コンデンサにおいて、前記基板と前記下側
電極層との間に前記下側電極層を構成する金属の酸化物
から成る密着層が介在されることを特徴とする薄膜コン
デンサに関するものである。According to one aspect of the present invention, there is provided a thin film capacitor formed by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer on a substrate. And a thin film capacitor characterized in that an adhesion layer made of a metal oxide constituting the lower electrode layer is interposed therebetween.
【０００８】ここで前記密着層は基板から下側電極層に
向って酸化の割合が連続的に減少するようにしてよい。
また前記密着層は基板から下側電極層に向って酸化の割
合が段階的に減少するようにしてよい。また下側電極層
がＲｕから構成されるとともに、密着層がＲｕＯ2 から
構成されてよい。あるいは下側電極層がＩｒから構成さ
れるとともに、密着層がＩｒＯ2 から構成されてよい。Here, the adhesion layer may be configured so that the rate of oxidation is continuously reduced from the substrate toward the lower electrode layer.
Further, the adhesion layer may be configured so that the rate of oxidation is reduced stepwise from the substrate toward the lower electrode layer. Further, the lower electrode layer may be made of Ru, and the adhesion layer may be made of RuO 2 . Alternatively, the lower electrode layer may be made of Ir, and the adhesion layer may be made of IrO 2 .
【０００９】またここで基板がマイカ基板であってよ
い。あるいはまた基板がガラスエポキシ基板、ポリイミ
ド基板、アラミド基板等の有機材料基板であってよい。
また誘電体層がＢａx Ｓｒ1-x ＴｉＯ3 のペロブスカイ
ト構造の結晶から成るものであってよい。In this case, the substrate may be a mica substrate. Alternatively, the substrate may be an organic material substrate such as a glass epoxy substrate, a polyimide substrate, and an aramid substrate.
Or may be one dielectric layer is made of crystals of perovskite structure Ba x Sr 1-x TiO 3 .
【００１０】製造方法に関する一発明は、基板上に下側
電極層、誘電体層、上側電極層を順次積層して形成する
ようにした薄膜コンデンサの製造方法において、基板上
に下側電極層を形成する初期段階で下側電極層を酸化さ
せる酸化ガスを導入し、基板と下側電極層との間に酸化
物層から成る密着層を形成することを特徴とする薄膜コ
ンデンサの製造方法に関するものである。One invention related to a manufacturing method relates to a method for manufacturing a thin film capacitor in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated on a substrate, wherein the lower electrode layer is formed on the substrate. A method for manufacturing a thin film capacitor, characterized in that an oxidizing gas for oxidizing a lower electrode layer is introduced at an initial stage of formation, and an adhesion layer composed of an oxide layer is formed between a substrate and the lower electrode layer. It is.
【００１１】ここで密着層がＤＣスパッタ法によって成
膜されるようにしてよい。また密着層を形成する際の雰
囲気ガスがＡｒであって、酸化ガスがＯ2 であり、しか
も酸化ガスがガス全体の２０〜５０％の濃度で流入され
るようにしてよい。また密着層を形成する酸化ガスの濃
度が成膜時に連続的に減少するようにしてよい。あるい
はまた密着層を形成する酸化ガスの濃度が成膜時に段階
的に減少するようにしてよい。Here, the adhesion layer may be formed by a DC sputtering method. The atmosphere gas for forming the adhesion layer may be Ar, the oxidizing gas may be O 2 , and the oxidizing gas may be introduced at a concentration of 20 to 50% of the entire gas. Further, the concentration of the oxidizing gas forming the adhesion layer may be continuously reduced during the film formation. Alternatively, the concentration of the oxidizing gas forming the adhesion layer may be reduced stepwise during film formation.
【００１２】[0012]
【発明の実施の形態】本発明の好ましい実施の形態は、
薄膜コンデンサを形成する基板とコンデンサの下側電極
層との密着性を向上させるために、基板と下側電極層と
の間に下側電極層と同じ材料の酸化物の層を導入するよ
うにしたものである。すなわちマイカ基板上に形成され
る薄膜コンデンサにおいて、下側電極層をＲｕとする場
合にはこの下側電極層と基板との間にＲｕＯ2 の密着層
を形成する。これに対して下側電極層がＩｒである場合
には、密着層としてＩｒＯ2 を基板と下側電極層との間
に形成する。BEST MODE FOR CARRYING OUT THE INVENTION
In order to improve the adhesion between the substrate forming the thin film capacitor and the lower electrode layer of the capacitor, an oxide layer of the same material as the lower electrode layer is introduced between the substrate and the lower electrode layer. It was done. That is, in a thin film capacitor formed on a mica substrate, when the lower electrode layer is made of Ru, an adhesion layer of RuO 2 is formed between the lower electrode layer and the substrate. On the other hand, when the lower electrode layer is Ir, IrO 2 is formed between the substrate and the lower electrode layer as an adhesion layer.
【００１３】このような密着層の形成は、基板上にガス
雰囲気中で下側電極層を成膜する初期段階で、下側電極
層を酸化させる酸化ガスを導入し、これによって密着層
となる酸化物層を形成する。例えば下側電極層をＤＣス
パッタ法によって形成する場合には、密着層をもＤＣス
パッタ法によって成膜するようにしており、密着層を形
成する際の雰囲気ガスとしてＡｒを用い、また酸化ガス
としてＯ2 を用い、Ｏ2 を雰囲気ガスに混入して密着層
を形成する。ここで酸化ガスをガス全体の２０〜５０％
の濃度で流入させるようにしてよい。In the formation of such an adhesion layer, an oxidizing gas for oxidizing the lower electrode layer is introduced at an initial stage of forming the lower electrode layer on the substrate in a gas atmosphere, thereby forming the adhesion layer. An oxide layer is formed. For example, when the lower electrode layer is formed by the DC sputtering method, the adhesion layer is also formed by the DC sputtering method, and Ar is used as an atmosphere gas when the adhesion layer is formed, and as an oxidizing gas. Using O 2 , O 2 is mixed into an atmospheric gas to form an adhesion layer. Here, the oxidizing gas is 20 to 50% of the entire gas.
May be introduced at a concentration of
【００１４】密着層を形成する際の酸化ガスＯ2 の濃度
が成膜時に連続的に減少すると、密着層は基板から下側
電極層に向って酸化の割合が連続的に減少することにな
る。これに対して密着層を形成する際の酸化ガスの濃度
を成膜時に段階的に減少させると、密着層は基板から下
側電極層に向って酸化の割合が段階的に減少することに
なる。[0014] The concentration of the oxidizing gas O 2 for forming the adhesion layer continuously decreases during deposition, the adhesion layer will be the rate of oxidation toward the lower electrode layer from the substrate is reduced continuously . On the other hand, if the concentration of the oxidizing gas in forming the adhesion layer is reduced stepwise during film formation, the rate of oxidation of the adhesion layer gradually decreases from the substrate toward the lower electrode layer. .
【００１５】このようにして基板と、この基板上に順に
積層される下側電極層、誘電体層、上側電極層を有する
薄膜コンデンサにおいて、基板と下側電極層との間に、
下側電極層を構成する金属の酸化物を成分とする密着層
が介在されることになる。なおこの場合における誘電体
層としては、Ｂａx Ｓｒ1-x ＴｉＯ3 のペロブスカイト
構造の結晶が用いられることが好ましい。In the thin film capacitor having the substrate and the lower electrode layer, the dielectric layer, and the upper electrode layer which are sequentially laminated on the substrate in this manner, the thin film capacitor between the substrate and the lower electrode layer
An adhesive layer containing a metal oxide constituting the lower electrode layer is interposed. Note The dielectric layer in this case, crystals of perovskite structure Ba x Sr 1-x TiO 3 is preferably used.
【００１６】上記のような薄膜コンデンサによれば、基
板と下側電極層との間に密着層が形成されることにな
り、これによって基板と下側電極層との密着性が向上さ
れるようになり、熱処理後に剥離を生ずることのない薄
膜コンデンサが提供される。また密着層を工程を大きく
増やすことなく形成できるために、コストの軽減が可能
になる。さらに薄膜コンデンサ膜が形成された基板は、
抵抗膜がついた基板等と積層されて受動素子内蔵型の電
子回路基板を製作することが可能になる。According to the above-described thin film capacitor, an adhesion layer is formed between the substrate and the lower electrode layer, so that the adhesion between the substrate and the lower electrode layer is improved. Thus, a thin film capacitor that does not peel off after heat treatment is provided. Further, since the adhesion layer can be formed without greatly increasing the number of steps, the cost can be reduced. Furthermore, the substrate on which the thin film capacitor film is formed
It is possible to manufacture an electronic circuit board with a built-in passive element by being laminated with a substrate or the like having a resistive film.
【００１７】[0017]
【実施例】以下本発明の一実施例に係る薄膜コンデンサ
をその製造工程の順に図１〜図５によって説明する。図
１は薄膜コンデンサを形成するマイカ基板１０を示して
いる。基板１０としてはマイカ基板、ガラス基板等で酸
化物が主成分の基板や、ガラスエポキシ基板、ポリイミ
ド基板、アラミド基板のような酸素が成分に含まれてお
り、しかも耐熱性に優れた有機材料基板を用いることが
できる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film capacitor according to an embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a mica substrate 10 forming a thin film capacitor. The substrate 10 is a mica substrate, a glass substrate, or the like, which is mainly composed of an oxide, a glass epoxy substrate, a polyimide substrate, or an aramid substrate. Can be used.
【００１８】図２はとくにマイカ基板１０のマイカの結
晶構造を示している。なおマイカの化学組成はＫＡｌ2
（ＡｌＳｉ3 Ｏ10）（ＯＨ）2 である。FIG. 2 shows the mica crystal structure of the mica substrate 10 in particular. The chemical composition of mica is KAl 2
(AlSi 3 O 10 ) (OH) 2 .
【００１９】マイカ基板１０には図１に示すように予め
穴を形成し、ここに導体ペーストを導入し、スルーホー
ル１１を形成する。このようなスルーホール１１が層間
接続手段を構成することになる。なお基板１０の表面に
凹凸があって薄膜形成が困難な場合には、平坦性をあげ
るためにガラスコーティング等の平坦化膜を堆積しても
よい。As shown in FIG. 1, a hole is previously formed in the mica substrate 10, and a conductive paste is introduced into the hole to form a through hole 11. Such a through hole 11 constitutes an interlayer connection means. When it is difficult to form a thin film due to unevenness on the surface of the substrate 10, a flattening film such as a glass coating may be deposited to improve flatness.
【００２０】次に図２に示すように、下側電極層の密着
性を向上させるための密着層１２をＤＣスパッタ蒸着法
により、例えば約１００ｎｍの膜厚で形成する。密着層
１２はその上に形成する下側電極層１３の金属の酸化物
である。下側電極層１３がＲｕの場合には、密着層１２
はＲｕＯ2 になる。また下側電極層１３がＩｒの場合に
は、密着層１２はＩｒＯ2 となる。Next, as shown in FIG. 2, an adhesion layer 12 for improving the adhesion of the lower electrode layer is formed to a thickness of, for example, about 100 nm by DC sputtering deposition. The adhesion layer 12 is a metal oxide of the lower electrode layer 13 formed thereon. When the lower electrode layer 13 is made of Ru, the adhesion layer 12
Becomes RuO 2 . When the lower electrode layer 13 is Ir, the adhesion layer 12 is IrO 2 .
【００２１】また密着層１２と下側電極層１３との界面
に発生する応力を減少させるために、密着層１２の酸化
の割合を基板１０の表面から下側電極層１３との界面へ
連続的に、もしくは段階的に減少させることが好まし
い。そしてこのような密着層１２上に薄膜コンデンサの
下側電極層１３を、例えば２００ｎｍの膜厚でスパッタ
蒸着法により形成する。ここで下側電極層１３として
は、ＲｕやＩｒのような耐熱性に優れた貴金属が望まし
い。In order to reduce the stress generated at the interface between the adhesion layer 12 and the lower electrode layer 13, the rate of oxidation of the adhesion layer 12 is continuously changed from the surface of the substrate 10 to the interface with the lower electrode layer 13. Or stepwise reduction. Then, the lower electrode layer 13 of the thin film capacitor is formed on such an adhesion layer 12 to a thickness of, for example, 200 nm by a sputter deposition method. Here, the lower electrode layer 13 is preferably a noble metal having excellent heat resistance, such as Ru or Ir.
【００２２】密着層１２をマイカ基板１０と下側電極層
１３との間に配置することによって基板１０と下側電極
層１３との間の密着性が向上する。これは基板１０と密
着層１２とがともに酸化物同士であるために、基板１０
上に直接下側電極層１３を構成する金属を堆積させる場
合に比べて密着性が改善される。また下側電極層１３と
密着層１２とは金属とその酸化物の関係であるために密
着性が良好になっている。By arranging the adhesion layer 12 between the mica substrate 10 and the lower electrode layer 13, the adhesion between the substrate 10 and the lower electrode layer 13 is improved. This is because the substrate 10 and the adhesion layer 12 are both oxides.
Adhesion is improved as compared with the case where the metal constituting the lower electrode layer 13 is directly deposited on the upper surface. Further, since the lower electrode layer 13 and the adhesion layer 12 have a relationship between a metal and its oxide, the adhesion is good.
【００２３】とくに下側電極層１３と密着層１２とをス
パッタ蒸着によって形成する場合には、蒸着の金属ター
ゲットを１種類用意するだけでよく、これによって製造
コストの低減につながる。すなわち密着層１２としてＴ
ｉ等の下側電極層１３とは別の金属を用いる場合には、
金属ターゲットが２種類必要になるが、下側電極層１３
の酸化物を密着層１２として用いる場合には、スパッタ
装置のフローガスＡｒに酸素を混ぜて蒸着中に酸化させ
て密着層１２を形成することができ、１種類のスパッタ
ターゲットで密着層１２と下側電極層１３とを形成する
ことができる。この場合に雰囲気ガスを構成するＡｒガ
スに対するＯ2 ガスの流量の比率を０．２〜０．５の割
合にするとよい。密着層１２の酸化の割合を基板１０側
から下側電極層１３側へ連続的に、もしくは段階的に減
少する場合には、Ｏ2 ガスの流量を連続的もしくは段階
的に減少させればよい。In particular, when the lower electrode layer 13 and the adhesion layer 12 are formed by sputtering evaporation, only one kind of metal target for evaporation needs to be prepared, which leads to a reduction in manufacturing cost. That is, T
When a metal different from the lower electrode layer 13 such as i is used,
Although two types of metal targets are required, the lower electrode layer 13
Is used as the adhesion layer 12, the adhesion layer 12 can be formed by mixing the flow gas Ar of a sputtering apparatus with oxygen and oxidizing it during vapor deposition, and the adhesion layer 12 can be formed with one kind of sputter target. The lower electrode layer 13 can be formed. In this case, the ratio of the flow rate of the O 2 gas to the Ar gas constituting the atmosphere gas may be set to 0.2 to 0.5. When the rate of oxidation of the adhesion layer 12 is reduced continuously or stepwise from the substrate 10 side to the lower electrode layer 13 side, the flow rate of the O 2 gas may be reduced continuously or stepwise. .
【００２４】下側電極層１３を形成した後に誘電体層１
４を図４に示すように例えば２００ｎｍ以下の膜厚で形
成する。誘電体層１４はＢａx Ｓｒ1-x ＴｉＯ3 （ＢＳ
Ｔ）、ＰｂＺｒx Ｔｉ1-x Ｏ3 （ＰＺＴ）、Ｐｂx Ｌａ
1-x （ＺｒＴｉ1-y ）1-y/4Ｏ3 （ＰＬＺＴ）、ＰｂＭ
ｇ1/3 Ｎｂ2/3 Ｏ3 （ＰＭＮ）、Ｂｉ4 Ｔｉ3 Ｏ12、Ｓ
ｒＢｉ2 Ｔａ2 Ｏ9 （ＳＢＴ）のような強誘電体特性を
有する材料を用い、スパッタ蒸着法、ゾル−ゲル法、デ
ィップ法、またはミスト法によって形成する。After forming the lower electrode layer 13, the dielectric layer 1
4 is formed with a thickness of, for example, 200 nm or less as shown in FIG. The dielectric layer 14 is Ba x Sr 1-x TiO 3 (BS
T), PbZr x Ti 1-x O 3 (PZT), Pb x La
1-x (ZrTi 1-y ) 1-y / 4 O 3 (PLZT), PbM
g 1/3 Nb 2/3 O 3 (PMN), Bi 4 Ti 3 O 12 , S
A material having ferroelectric properties such as rBi 2 Ta 2 O 9 (SBT) is formed by a sputter deposition method, a sol-gel method, a dip method, or a mist method.
【００２５】誘電体層１４を形成した後に、図５に示す
ようにＰｔの上側電極層１５を例えば２００ｎｍの膜厚
でスパッタ蒸着法により形成する。なおこのような構成
に代えて、Ａｕを抵抗加熱蒸着法で成膜し、これを上側
電極層１５としてもよい。そしてこの後マスクを施して
パターニングすると、図５に示すような薄膜コンデンサ
膜を形成することが可能になる。また図６に示すよう
に、下側電極層１３、誘電体層１４、上側電極層１５の
各層毎にパターニングを行なってもよい。この場合には
スルーホール１１を薄膜コンデンサ形成後にあけること
が可能になり、プロセスの幅が広がる。なおパターニン
グはウエットエッチング法、ドライエッチング法、サン
ドブラスト法等の各種の方法によって行なわれてよい。After the formation of the dielectric layer 14, as shown in FIG. 5, an upper electrode layer 15 of Pt is formed to a thickness of, for example, 200 nm by a sputter deposition method. Instead of such a configuration, Au may be formed by a resistance heating evaporation method, and this may be used as the upper electrode layer 15. Then, when a mask is applied and patterned, a thin film capacitor film as shown in FIG. 5 can be formed. Further, as shown in FIG. 6, patterning may be performed for each of the lower electrode layer 13, the dielectric layer 14, and the upper electrode layer 15. In this case, the through hole 11 can be opened after the formation of the thin film capacitor, and the process width is widened. The patterning may be performed by various methods such as a wet etching method, a dry etching method, and a sand blast method.
【００２６】なお上記実施例においては、密着層１２と
下側電極層１３との成膜法として、電子スパッタ蒸着法
を用いたが、このような方法に限定されることなく、成
膜中に酸化が可能な方法であれば、ＲＦスパッタ蒸着法
やＣＶＤ法、その他の成膜法を用いても同様の効果が得
られる。In the above embodiment, an electron sputtering deposition method was used as a method for forming the adhesion layer 12 and the lower electrode layer 13. However, the present invention is not limited to such a method. A similar effect can be obtained by using an RF sputter deposition method, a CVD method, or another film formation method as long as the method allows oxidation.
【００２７】図８はこのように方法によって形成される
薄膜コンデンサを備えた多層回路基板の一例を示してい
る。ここではマイカ基板から成る第１層２１、第２層２
２、第３層２３、および第４層２４の４層構造をなして
いる。第１層２１の表面には配線パターン２８が形成さ
れるとともに、このような配線パターン２８の一部を電
極として、半田ボール２９によって電気的な接続が行な
われた状態で実装部品３０が実装される。第１層２１と
第２層２２との間はグランド層を構成する導電層３１が
形成される。また第２層２２と第３層２３との間には配
線パターン３２が形成されるとともに、薄膜コンデンサ
３３が形成される。なおこのコンデンサの下側電極層の
下側に上述の密着層が形成されている。また第３層２３
と第４層２４との間には配線パターン３４とともに印刷
抵抗３５が形成されている。第４層２４の下面には配線
パターン３６が形成されることになる。すなわち薄膜コ
ンデンサ３３が形成された基板は、抵抗膜３５が形成さ
れた基板等と積層されて受動素子内蔵型の多層基板を製
作することが可能になる。FIG. 8 shows an example of a multilayer circuit board provided with a thin film capacitor formed by the above method. Here, the first layer 21 and the second layer 2 made of a mica substrate
It has a four-layer structure including a second layer 23, a third layer 23, and a fourth layer 24. A wiring pattern 28 is formed on the surface of the first layer 21, and a mounting component 30 is mounted in a state where a part of such a wiring pattern 28 is used as an electrode and electrically connected by a solder ball 29. You. A conductive layer 31 forming a ground layer is formed between the first layer 21 and the second layer 22. Further, a wiring pattern 32 is formed between the second layer 22 and the third layer 23, and a thin film capacitor 33 is formed. The above-mentioned adhesion layer is formed below the lower electrode layer of the capacitor. The third layer 23
A printed resistor 35 is formed between the first and second layers 24 together with the wiring pattern 34. The wiring pattern 36 is formed on the lower surface of the fourth layer 24. That is, the substrate on which the thin film capacitor 33 is formed is laminated with a substrate or the like on which the resistive film 35 is formed, thereby making it possible to manufacture a multilayer substrate with a built-in passive element.
【００２８】[0028]
【発明の効果】本願の一発明は、基板上に下側電極層、
誘電体層、上側電極層を順次積層して形成される薄膜コ
ンデンサにおいて、基板と下側電極層との間に下側電極
層を構成する金属の酸化物から成る密着層が介在される
ようにしたものである。According to one aspect of the present invention, a lower electrode layer is provided on a substrate.
In a thin film capacitor formed by sequentially laminating a dielectric layer and an upper electrode layer, an adhesion layer made of a metal oxide constituting the lower electrode layer is interposed between the substrate and the lower electrode layer. It was done.
【００２９】従ってこのような構成によれば、基板と下
側電極層との間に介在される密着層によって、基板と下
側電極層との密着性が向上することになり、誘電体層を
形成するために熱処理を行なっても、剥離の発生し難い
薄膜コンデンサが提供されるようになる。Therefore, according to such a configuration, the adhesion between the substrate and the lower electrode layer is improved by the adhesion layer interposed between the substrate and the lower electrode layer, and the dielectric layer is formed. Even if heat treatment is performed to form the thin film capacitor, a thin film capacitor that does not easily peel off can be provided.
【００３０】製造方法に関する一発明は、基板上に下側
電極層、誘電体層、上側電極層を順次積層して形成する
ようにした薄膜コンデンサの製造方法において、基板上
に下側電極層を形成する初期段階で下側電極層を酸化さ
せる酸化ガスを導入し、基板と下側電極層との間に酸化
物層から成る密着層を形成するようにしたものである。One aspect of the present invention relates to a method of manufacturing a thin film capacitor in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially laminated and formed on a substrate, wherein the lower electrode layer is formed on the substrate. An oxidizing gas for oxidizing the lower electrode layer is introduced at an initial stage of formation, so that an adhesion layer made of an oxide layer is formed between the substrate and the lower electrode layer.
【００３１】従ってこのような方法によれば、下側電極
層を形成する初期段階での酸化ガスの導入に伴って、下
側電極層と同一の材料から成る酸化物層によって密着層
が形成されることになり、製造工程を大きく増やすこと
なく効果的に密着層を形成することが可能になり、薄膜
コンデンサの製造コストの低減が可能になる。Therefore, according to such a method, the adhesion layer is formed by the oxide layer made of the same material as the lower electrode layer with the introduction of the oxidizing gas in the initial stage of forming the lower electrode layer. As a result, the adhesion layer can be effectively formed without significantly increasing the number of manufacturing steps, and the manufacturing cost of the thin film capacitor can be reduced.
【図１】マイカ基板の断面図である。FIG. 1 is a sectional view of a mica substrate.
【図２】密着層が形成されたマイカ基板の縦断面図であ
る。FIG. 2 is a longitudinal sectional view of a mica substrate on which an adhesion layer is formed.
【図３】下側電極層が形成されたマイカ基板の縦断面図
である。FIG. 3 is a longitudinal sectional view of a mica substrate on which a lower electrode layer is formed.
【図４】誘電体層が形成されたマイカ基板の縦断面図で
ある。FIG. 4 is a longitudinal sectional view of a mica substrate on which a dielectric layer is formed.
【図５】薄膜コンデンサが形成されたマイカ基板の縦断
面図である。FIG. 5 is a longitudinal sectional view of a mica substrate on which a thin film capacitor is formed.
【図６】薄膜コンデンサが形成されたマイカ基板の縦断
面図である。FIG. 6 is a longitudinal sectional view of a mica substrate on which a thin film capacitor is formed.
【図７】マイカの結晶構造図である。FIG. 7 is a crystal structure diagram of mica.
【図８】薄膜コンデンサを内蔵した多層基板の縦断面図
である。FIG. 8 is a longitudinal sectional view of a multilayer substrate having a built-in thin film capacitor.
１０‥‥マイカ基板、１１‥‥スルーホール、１２‥‥
密着層、１３‥‥下側電極層、１４‥‥誘電体層、１５
‥‥上側電極層、２１‥‥第１層、２２‥‥第２層、２
３‥‥第３層、２４‥‥第４層、２８‥‥配線パター
ン、２９‥‥半田ボール、３０‥‥実装部品、３１‥‥
導電層（グランド層）、３２‥‥配線パターン、３３‥
‥コンデンサ、３４‥‥配線パターン、３５‥‥印刷抵
抗、３６‥‥配線パターン10 ‥‥ mica substrate, 11 ‥‥ through hole, 12 ‥‥
Adhesion layer, 13 ° lower electrode layer, 14 ° dielectric layer, 15
{Upper electrode layer, 21} First layer, 22} Second layer, 2
3 ‥‥ 3rd layer, 24 ‥‥ 4th layer, 28 ‥‥ wiring pattern, 29 ‥‥ solder ball, 30 ‥‥ mounting component, 31 ‥‥
Conductive layer (ground layer), 32 ‥‥ wiring pattern, 33 ‥
{Capacitor, 34} Wiring pattern, 35} Print resistance, 36} Wiring pattern
フロントページの続き (72)発明者 大迫 純一 東京都品川区北品川６丁目７番35号ソニー 株式会社内 Ｆターム(参考） 5E001 AB01 AC01 AC10 AE01 AE02 AE03 AH01 AH03 AJ01 AJ02 AZ01 5E082 AA20 AB01 BC39 EE05 EE23 EE37 FF05 FG03 FG26 FG42 FG46 MM09 PP03 Continued on the front page (72) Inventor Junichi Osako 6-35 Kita-Shinagawa, Shinagawa-ku, Tokyo F-term in Sony Corporation (reference) 5E001 AB01 AC01 AC10 AE01 AE02 AE03 AH01 AH03 AJ01 AJ02 AZ01 5E082 AA20 AB01 BC39 EE05 EE23 EE37 FF05 FG03 FG26 FG42 FG46 MM09 PP03
Claims (13)
層を順次積層して形成される薄膜コンデンサにおいて、 前記基板と前記下側電極層との間に前記下側電極層を構
成する金属の酸化物から成る密着層が介在されることを
特徴とする薄膜コンデンサ。1. A thin film capacitor formed by sequentially laminating a lower electrode layer, a dielectric layer, and an upper electrode layer on a substrate, wherein the lower electrode layer is provided between the substrate and the lower electrode layer. A thin film capacitor comprising an adhesive layer made of a metal oxide constituting the thin film capacitor.
酸化の割合が連続的に減少することを特徴とする請求項
１に記載の薄膜コンデンサ。2. The thin film capacitor according to claim 1, wherein the rate of oxidation of the adhesion layer continuously decreases from the substrate toward the lower electrode layer.
酸化の割合が段階的に減少することを特徴とする請求項
１に記載の薄膜コンデンサ。3. The thin film capacitor according to claim 1, wherein the rate of oxidation of the adhesion layer decreases stepwise from the substrate toward the lower electrode layer.
に、密着層がＲｕＯ2 から構成されることを特徴とする
請求項１に記載の薄膜コンデンサ。4. The thin film capacitor according to claim 1, wherein the lower electrode layer is made of Ru, and the adhesion layer is made of RuO 2 .
に、密着層がＩｒＯ2 から構成されることを特徴とする
請求項１に記載の薄膜コンデンサ。5. The thin film capacitor according to claim 1, wherein the lower electrode layer is made of Ir and the adhesion layer is made of IrO 2 .
請求項１に記載の薄膜コンデンサ。6. The thin film capacitor according to claim 1, wherein the substrate is a mica substrate.
板、アラミド基板等の有機材料基板であることを特徴と
する請求項１に記載の薄膜コンデンサ。7. The thin film capacitor according to claim 1, wherein the substrate is an organic material substrate such as a glass epoxy substrate, a polyimide substrate, and an aramid substrate.
ブスカイト構造の結晶から成ることを特徴とする請求項
１に記載の薄膜コンデンサ。8. The thin film capacitor according to claim 1, wherein the dielectric layer is made of a crystal having a perovskite structure of Ba x Sr 1 -x TiO 3 .
層を順次積層して形成するようにした薄膜コンデンサの
製造方法において、 基板上に下側電極層を形成する初期段階で下側電極層を
酸化させる酸化ガスを導入し、基板と下側電極層との間
に酸化物層から成る密着層を形成することを特徴とする
薄膜コンデンサの製造方法。9. A method of manufacturing a thin film capacitor in which a lower electrode layer, a dielectric layer, and an upper electrode layer are sequentially formed on a substrate, wherein the lower electrode layer is formed on the substrate in an initial stage. A method for manufacturing a thin film capacitor, comprising introducing an oxidizing gas for oxidizing a lower electrode layer and forming an adhesion layer formed of an oxide layer between the substrate and the lower electrode layer.
れることを特徴とする請求項９に記載の薄膜コンデンサ
の製造方法。10. The method according to claim 9, wherein the adhesion layer is formed by a DC sputtering method.
であって、酸化ガスがＯ2 であり、しかも酸化ガスがガ
ス全体の２０〜５０％の濃度で流入されることを特徴と
する請求項１０に記載の薄膜コンデンサの製造方法。11. An atmosphere gas for forming an adhesion layer is Ar.
A is a oxidizing gas O 2, moreover method of manufacturing a thin film capacitor according to claim 10 in which the oxidizing gas is characterized in that it is flowing in 20-50% of the concentration of the total gas.
時に連続的に減少することを特徴とする請求項９に記載
の薄膜コンデンサの製造方法。12. The method for manufacturing a thin film capacitor according to claim 9, wherein the concentration of the oxidizing gas forming the adhesion layer is continuously reduced during film formation.
時に段階的に減少することを特徴とする請求項９に記載
の薄膜コンデンサの製造方法。13. The method for manufacturing a thin film capacitor according to claim 9, wherein the concentration of the oxidizing gas forming the adhesion layer decreases stepwise during the film formation.
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|---|---|---|---|
| JP11217041A JP2001044073A (en) | 1999-07-30 | 1999-07-30 | Thin-film capacitor and fabrication thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11217041A JP2001044073A (en) | 1999-07-30 | 1999-07-30 | Thin-film capacitor and fabrication thereof |
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| Publication Number | Publication Date |
|---|---|
| JP2001044073A true JP2001044073A (en) | 2001-02-16 |
Family
ID=16697922
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|---|---|---|---|
| JP11217041A Pending JP2001044073A (en) | 1999-07-30 | 1999-07-30 | Thin-film capacitor and fabrication thereof |
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| Country | Link |
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| JP (1) | JP2001044073A (en) |
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