JP2001036360A - Gain variable amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To expand gain variable width and to provide low distortion characteristics and low power consumption characteristics. SOLUTION: This amplifier is provided with a transistor Q1, connecting the base to an input terminal IN and grounding an emitter via a resistor RE1, transistors Q2 and Q3 commonly connecting emitters and connecting collectors to a power line directly and via a load resistor RC1, while differentially inputting gain control voltages to bases and a transistor Q4 connecting the base to the collector of the transistor Q3, connecting a collector to the power line and connecting the emitter to an output terminal OUT. Then, the node of the collector of the transistor Q2 with the power line is connected via the series resonance circuit of a capacity C1 and a parasitic inductance L1 of bonding wire and lead frame to a ground terminal GND.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier, and more particularly to a variable gain amplifier suitable for use in a monolithic IC.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a circuit configuration of a conventional variable gain amplifier configured as a monolithic IC. FIG.
In this conventional variable gain amplifier, a differential pair transistor Q2, Q3 having an emitter connected in common and a differential input of a control voltage from a gain control unit 10 at a base;
The collector is connected to the common emitter of the differential pair transistors Q2 and Q3, the base is connected to the input terminal IN, the emitter is the emitter resistor RE1, and the parasitic inductance LGN
Transistor Q connected to ground terminal GND via D
1 constitute the gain variable section 11A, and the collector of the transistor Q2 is directly connected to the power supply line Vcc via the load resistor RC1. The connection point between the collector of the transistor Q3 and the load resistor RC1 is connected to the base of a transistor Q4 having an emitter follower configuration in which the collector is connected to a power supply line, the emitter of the transistor Q4 is connected to the output terminal OUT, and the emitter follower is connected. The emitter follower transistor Q4, which is grounded via the current source 13, constitutes the buffer amplifier 12. In FIG. 4, the inductance LVcc represents, for example, a bonding wire for connecting a bonding pad of a chip to a lead of a package and a parasitic inductance of a lead frame.

In the variable gain amplifier of the circuit shown in FIG. 4, a signal input from an input terminal IN is amplified from a transistor Q1 to a transistor Q3 by a cascode connection from an emitter ground to a base ground, and the gain control unit 10 The gain is variably controlled by the gain control voltage supplied to the differential pair transistors Q2 and Q3 from.

For example, at the time of the maximum gain, the transistor Q2 is turned off, and no current flows through the transistor Q2, and a current flows only through the transistor Q3 to obtain a gain. On the other hand, at the time of the minimum gain, on the other hand, the current is caused to flow through the transistor Q2, and the current is not caused to flow through the transistor Q3, thereby decreasing the gain.

[0005]

In the mobile communication market, there is a demand for a large gain variable width and a low distortion characteristic and a low power consumption characteristic at a frequency of 500 MHz or more.

In the conventional variable gain amplifier having the circuit configuration shown in FIG. 4, only the current I1 flowing through the transistor Q1 is sufficient for the current flowing through the variable gain section 11A.
It is suitable for achieving both low distortion characteristics and low power consumption characteristics.

However, the parasitic inductance LVcc of the bonding wire and the lead frame, which is parasitic on the power supply line, has a high impedance at a high frequency, becomes a load, and the transistor Q2 has a gain. An output signal is generated at a connection node A) between the collector of the transistor Q2 and the power supply line. This output signal is transmitted to the output terminal OUT through the path (load resistance RC1, base of the transistor Q4) indicated as "signal leak" in FIG.

If the leak signal is larger than the output voltage of the transistor Q3, the effective minimum gain is
There is a problem that the output on the signal leak side becomes the minimum gain of the entire system and the gain variable width becomes small.

[0009] As a countermeasure, a variable gain amplifier can be ensured by using a dual differential variable gain amplifier as shown in FIG.

Referring to FIG. 5, a differential pair transistor Q11 having an emitter connected in common and connected to a constant current source 14 and a base connected to complementary input terminals IN and IN #.
Q12 and the emitter are commonly connected to form a transistor Q1.
1 connected to the control voltage of the gain control unit 10, and the collector is connected to the power supply line via the load resistor RC1 and directly to the power supply line.
13, Q14 and the emitter are connected in common and connected to the collector of the transistor Q12, and the base is connected to the gain control unit 1
Transistors Q15, Q16 connected to a control voltage of 0 and a collector via a load resistor RC2 and directly to a power supply line;
The transistor Q17 has an emitter follower configuration in which a connection point with C2 is connected to the base. This is because, in the power supply line, the output of the input terminal IN and the output of the complementary signal input terminal IN # are always out of phase with each other and cancel each other, so that signal leakage does not occur.

However, in the variable gain amplifier of the bi-differential type shown in FIG. 5, the current needs to be doubled in order to secure the same distortion characteristics as the circuit of the single-differential type shown in FIG. It is disadvantageous in terms of low power consumption characteristics.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to provide a variable gain amplifier which realizes low distortion characteristics and low power consumption characteristics while expanding the variable gain range. It is in.

[0013]

According to the present invention, there is provided a differential amplifier comprising a gain control voltage as a differential input and first and second outputs connected to a power supply line directly and via a load resistor. Variable gain amplifier including a pair, a gain variable unit including a base for inputting an input signal and supplying a drive current for the differential pair, and an emitter follower for inputting a second output potential of the differential pair , The first output of the differential pair includes a ground path including a capacitor and a parasitic inductance connected in series with the capacitor.

[0014]

Embodiments of the present invention will be described. The present invention relates to a variable gain amplifier of a differential type composed of a monolithic IC, wherein a bonding wire for connecting a bonding pad of a chip and a lead of a package and a parasitic inductance of a lead frame are embedded in the chip or externally attached to the chip. By connecting a capacitance (capacitor) in series and providing a ground path, signal leakage is prevented.

According to the present invention, there is provided a first transistor (Q1) having a base connected to the input terminal IN and an emitter grounded via a resistor RE1, and a collector connected to the first transistor (Q1) having an emitter connected in common. And a differential input of a gain control voltage to the base, and the collector is connected directly and via a load resistor (RC1) to a power supply line (V
cc) connected to the second and third transistors (Q2,
Q3), the base is connected to a connection point between the collector of the third transistor (Q3) and the load resistor (RC1), the collector is connected to the power supply line, and the emitter is the output terminal (OU).
T), a fourth transistor (Q4) having an emitter follower configuration connected to the power supply line, and the collector of the second transistor (Q2) directly connected to the power supply line is connected to a capacitor (C).
1) and a connection to a ground terminal (GND) via a series resonant circuit of a bonding wire and a parasitic inductance (L1) of a lead frame.

In the present invention, a capacitor (C1) and a parasitic inductance (L) are connected to a connection node between the collector of one transistor Q2 forming a differential pair and the power supply line.
By providing the grounding path of 1), a large gain variable width can be realized even with a single-differential variable gain amplifier. Can be realized.

[0017]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing the configuration of the first exemplary embodiment of the present invention.

Referring to FIG. 1, in the variable gain amplifier of this embodiment, the emitters are connected in common, and the differential pair transistors Q2 and Q3 whose bases receive the output voltage from the gain control section 10 as input, and the collectors are different. Dynamic pair transistor Q2, Q
The transistor Q1 is connected to the common emitter of the third transistor 3, the base is connected to the input terminal IN, and the emitter is connected to the ground terminal GND via the emitter resistor RE1 and the parasitic inductance LGND. The collector of the transistor Q2 is directly connected to the power supply line Vcc (the connection node between the parasitic inductance LVcc of the power supply line and the capacitor C1) via the load resistor RC1. A connection point between the collector of the transistor Q4 and the resistor RC1 is connected to the base of the transistor Q4 having an emitter follower configuration in which the collector is connected to the power supply line, and the transistor Q4
Are connected to the output terminal OUT and to the constant current source 13. The transistor Q4 having the emitter follower configuration forms the buffer amplifier unit 12. A connection point between the power supply line and the collector of the transistor Q2 is grounded via a series resonance frequency determining capacitor C1 and an inductance L1. Note that the inductances LVcc, LGND, and L1 represent parasitic inductances of the bonding wire and the lead frame.

In FIG. 1, a power supply line includes a bonding wire and a parasitic inductance L1 of a lead frame.
And the capacitor C1 are connected in series, and can be grounded.

The ground path has an impedance of 0 at the parasitic resonance L1 of the bonding wire and the lead frame and the series resonance frequency (f = 1 / 2π√ (L1 · C1)) of the capacitor C1 connected in series to the inductance L1. Thus, the signal leak is guided to the ground path, and the signal leak to the output OUT can be prevented.

The series resonance frequency f is the same as the operating frequency. The parasitic inductance L1 between the bonding wire and the lead frame is measured in advance or obtained by calculation or the like. Therefore, in practice, the value of the capacitor C1 connected in series may be determined.

The parasitic inductance L1 between the bonding wire and the lead frame is about 1.5 nH to about 5 nH in the case of a plastic mold package.
In the mobile communication field, a frequency of 800 MHz to 3 GHz can be handled by setting the capacitor C1 to 30 pF or less, so that the value can be realized by a capacitor built in a monolithic IC. When the frequency is lower than this, the capacitor C1 is configured by an external chip component.

FIG. 3A shows an example of the result of a circuit simulation obtained by analyzing the operation of one embodiment of the present invention. In FIG. 3A, the vertical axis represents gain, and the horizontal axis represents frequency.

The simulation result shown in FIG. 3A is based on the element values shown in FIG. In FIG. 3B, the collector voltage of the transistor Q3 connected to the power supply line via the load resistor (RC1) is connected to the collector among the transistors forming the differential pair without the buffer amplifier unit 12 of FIG. Output voltage (O
UT).

The parasitic inductance L1 of the bonding wire and the lead frame is 1.5 nH, the capacitance of the capacitor C1 connected in series is 4 pF, and the operating frequency is 2
The characteristics were analyzed using GHz. Load resistance (RC1)
Is 100 ohms and the emitter resistance (RE1) is 36 ohms.

As can be seen from FIG. 3A, the circuit according to the embodiment of the present invention can expand the variable gain range by 24.4 dB.
As an absolute value, a gain variable width of 42.5 dB can be obtained.

Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG. 2, the collector of the transistor Q2 is provided with an isolation securing resistor RC2, and the collector of the transistor Q2 is connected to a ground terminal via a ground path including a capacitor (C1) and a parasitic inductance (L1). In this embodiment, the isolation securing resistor RC2 prevents signal leakage from flowing into the load resistor RC1 side and the output OUT side of the gain variable section 11 ', thereby increasing the gain variable width and reducing distortion. Characteristics and low power consumption characteristics.

[0028]

As described above, according to the present invention,
By providing a ground path for the capacitor (C1) and the parasitic inductance (L1) on the power supply line side of the differential pair, a large gain variable width can be realized even with a single differential type variable gain amplifier.
As compared with a bi-variable variable gain amplifier, there is an effect that low distortion and low power consumption characteristics can be realized with half the current.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3A is a diagram illustrating a simulation result of the circuit according to the first embodiment of the present invention, and FIG. 3B is a diagram illustrating element values of a circuit to be simulated;

FIG. 4 is a diagram showing a configuration of a conventional single differential type variable gain amplifier.

FIG. 5 is a diagram showing a configuration of a conventional dual differential variable gain amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Gain control part 11, 11 ', 11A Gain variable part 12 Buffer amplifier part 13 Constant current source (emitter follower current source) 14 Constant current source C1 Capacitor (capacitance) Q1-Q4 Transistor L1, LVcc, LGGND Parasitic inductance RC1 Load resistance RC2 Isolation securing resistor

Claims (8)

[Claims] A first and second gain control voltage is set as a differential input.
A differential pair in which the outputs of the differential pair are connected directly to a power supply line via a resistance element, and a transistor that inputs an input signal to a base and supplies a drive current to the differential pair from the output,
A variable gain amplifier that includes a variable gain section having: and an output from a connection point between the second output of the differential pair and the resistance element, wherein a first output of the differential pair and the power supply line are connected to each other. A variable gain amplifier, wherein a connection point is grounded via a capacitor and a parasitic inductance connected in series to the capacitor. 2. The method according to claim 1, wherein the first and second gain control voltages are set as differential inputs.
A differential pair having outputs respectively connected to a power supply line via first and second resistance elements, and a transistor which receives an input signal as a base and supplies a drive current to the differential pair from an output. A variable gain amplifier that includes a variable gain section provided and takes out an output from a connection point between a second output of the differential pair and the second resistive element, wherein a first output of the differential pair has a capacitance; And a variable gain amplifier, which is grounded via a parasitic inductance connected in series to the capacitor. 3. The capacitor according to claim 1, wherein the capacitor is provided on the same chip as the variable gain amplifier, or is externally attached to the chip, and is connected in series with the parasitic inductance to form a ground path. The variable gain amplifier according to claim 1. 4. The variable gain amplifier according to claim 1, wherein a second output of the differential pair is connected to an output terminal via an emitter follower circuit. 5. A first transistor for inputting an input signal to a base and having an emitter grounded via a resistor, an emitter commonly connected to the collector of the first transistor, and a gain control voltage applied to the base. A differential pair consisting of second and third transistors, each having a differential input and a collector connected directly to a power supply line via a load resistor, and a base connected to the collector of the third transistor and the load resistor And a fourth transistor having a collector connected to the power supply line and an emitter connected to the output terminal, the collector of the second transistor and the power supply line. Is connected to a ground terminal via a series resonance circuit comprising a capacitance and a parasitic inductance. Gain amplifier circuit. 6. A first transistor whose input signal is input to a base and whose emitter is grounded via a resistor, whose emitter is connected in common and connected to the collector of said first transistor, and wherein a gain control voltage is applied to its base. A differential pair composed of second and third transistors having differential inputs and a collector connected to a power supply line via an isolation resistor and a load resistor, respectively, and a base connected to a collector of the third transistor. A fourth transistor connected to a connection point with the load resistor, a collector connected to the power supply line, and an emitter connected to the output terminal, wherein the collector of the second transistor is Variable gain amplifier characterized in that it is connected to a ground terminal through a series resonance circuit of capacitance, capacitance and parasitic inductance. 7. The variable gain amplifier according to claim 1, wherein said variable gain amplifier is formed on a semiconductor integrated circuit. 8. The variable gain amplifier according to claim 1, wherein said parasitic inductance comprises a bonding wire for electrically connecting a bonding pad of a chip and a lead, and a parasitic inductance of a lead frame. And a variable gain amplifier.