JP2001035787A - Crystalline semiconductor thin film and manufacture thereof, and semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for forming a single-crystal semiconductor thin film or a substantially single-crystal semiconductor thin film. SOLUTION: A catalyst element for promoting crystallization of an amorphous semiconductor thin film is added to the amorphous semiconductor thin film, and heat treatment is performed on the film so as to obtain a crystalline semiconductor thin film 102. After the crystalline semiconductor thin film 102 is irradiated with ultraviolet light or infrared light, it is subjected to heat treatment at 900-1,200 deg.C in a reducing atmosphere. By this process, the surface of a crystalline semiconductor thin film 104 is markedly planarized, and defects in grain boundaries or crystal grains are eliminated, and thus a single-crystal semiconductor thin film or a substantially single-crystal semiconductor thin film is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology related to a semiconductor device using a semiconductor thin film, and in particular, to a thin film transistor (Thin Film Transistor) using a crystalline silicon film.
(TFT) and a method for manufacturing the same.

[0002] Note that in this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics. Therefore, not only a single semiconductor element such as a TFT, but also an electro-optical device and a semiconductor circuit having a TFT and an electronic device equipped with them are also semiconductor devices.

[0003]

2. Description of the Related Art In recent years, TFTs used for electro-optical devices such as active matrix type liquid crystal display devices have been actively developed.

An active matrix type liquid crystal display device is
This is a monolithic display device provided with a pixel matrix circuit and a driver circuit on the same substrate. In addition, γ
Development of a system-on-panel incorporating a logic circuit such as a correction circuit, a memory circuit, and a clock generation circuit is also in progress.

Since such driver circuits and logic circuits need to operate at high speed, it is inappropriate to use an amorphous silicon film (amorphous silicon film) as an active layer. Therefore, at present, a TFT using a crystalline silicon film (single-crystal silicon film or polysilicon film) as an active layer is being studied.

The present applicant has disclosed a technique described in Japanese Patent Application Laid-Open No. Hei 7-130652 as a technique for obtaining a crystalline silicon film on a glass substrate. The technology described in the publication adds a catalyst element that promotes crystallization to an amorphous silicon film,
A crystalline silicon film is obtained by performing a heat treatment.

According to this technique, the crystallization temperature of the amorphous silicon film can be lowered by 50 to 100 ° C. by the action of a catalytic element, and the time required for crystallization is reduced to 1/5 to 1/10. be able to.

[0008]

SUMMARY OF THE INVENTION However, TFT
When circuit performance comparable to that of conventional LSIs is required for the circuits assembled in the above, the crystalline silicon film formed by the conventional technology requires a TFT having sufficient performance to meet the specifications. It has become difficult to fabricate.

An object of the present invention is to provide a technique for realizing a single crystal semiconductor thin film or a substantially single crystal semiconductor thin film. Note that a substantial single crystal semiconductor thin film refers to a crystalline semiconductor thin film such as a polycrystalline semiconductor thin film in which a portion functioning as a barrier that hinders the movement of carriers such as crystal grain boundaries and defects is eliminated.

Further, a high-performance TFT having the single-crystal semiconductor thin film or substantially single-crystal semiconductor thin film of the present invention as a channel forming region is realized, and a high-performance semiconductor device having a circuit assembled by the TFT is provided. The task is to

In this specification, a single crystal semiconductor thin film,
Semiconductor thin films having crystallinity, such as a polycrystalline semiconductor thin film and a microcrystalline semiconductor thin film, are collectively called a crystalline semiconductor thin film.

[0012]

One of the structures for carrying out the present invention promotes crystallization of the amorphous semiconductor thin film in a part or all of the region on the amorphous semiconductor thin film. A step of adding a catalytic element, a step of performing a first heat treatment to change a part or the entire region of the amorphous semiconductor thin film into a crystalline semiconductor thin film, and a step of reducing the crystalline semiconductor thin film in a reducing atmosphere. Performing a second heat treatment at 900 to 1200 ° C.

In the above structure, the second heat treatment may be performed at a temperature at which a natural oxide film (for example, a silicon oxide film) formed on the surface of the crystalline semiconductor thin film is reduced.
The reaction is performed in a temperature range of 0 to 1200 ° C (preferably 1000 to 1100 ° C). Further, the processing time is preferably at least 3 minutes or more, 3 minutes to 1 hour, typically 10 minutes to 1 hour. This is the time required to exhibit the effect of the second heat treatment.

Note that the second heat treatment may be performed after the crystalline semiconductor thin film is processed into an island shape. The heat treatment is performed by furnace annealing (annealing performed in an electric furnace).

The features of the present invention are as follows.
No. 652, a crystalline semiconductor thin film is formed, and the crystalline semiconductor thin film is formed in a thickness of 900 to 900 nm.
The heat treatment is performed in a reducing atmosphere (typically, a hydrogen atmosphere) at 1200 ° C.

This step has the effect of first planarizing the surface of the crystalline semiconductor thin film. This is the result of enhanced surface diffusion of semiconductor atoms in an attempt to minimize surface energy. At the same time, this step also has an effect of remarkably reducing crystal grain boundaries and defects existing in crystal grains. This is due to the effect of terminating dangling bonds by hydrogen, the effect of removing impurities by hydrogen, and the resulting recombination of semiconductor atoms. Therefore, in order to exhibit these effects efficiently, the processing time as described above is required.

Therefore, the heat treatment step in the reducing atmosphere needs to be performed by furnace annealing. When heat treatment is performed by irradiating ultraviolet light or infrared light, recrystallization proceeds in a non-equilibrium state, and thus the continuity of a crystal lattice at a crystal grain boundary is deteriorated. On the other hand, in the case of furnace annealing, such a problem can be avoided because recrystallization proceeds in an equilibrium state.

In another aspect of the present invention, a step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, A step of performing a heat treatment to change a part or the entire region of the amorphous semiconductor thin film into a crystalline semiconductor thin film, and a step of irradiating the crystalline semiconductor thin film with ultraviolet light or infrared light as a second heat treatment And performing a third heat treatment at 900 to 1200 ° C. in a reducing atmosphere on the crystalline semiconductor thin film.

This structure is characterized in that the crystallinity is improved by irradiating ultraviolet light or infrared light after forming the crystalline semiconductor thin film. Here, the improvement in crystallinity refers to a reduction in defects and levels existing in crystal grains and crystal grain boundaries.

In this case, when ultraviolet light is used, excimer laser light or light emitted from an ultraviolet lamp may be used, and when infrared light is used, light emitted from an infrared lamp may be used.

However, when irradiating ultraviolet light or infrared light, it is necessary to pay attention to the energy of the light. This is because if the crystalline silicon film is heated too much here, the continuity of the crystal lattice at the crystal grain boundaries may be impaired. According to experiments, when the film surface temperature is 600 to 800 ° C., the crystallinity can be improved without impairing the continuity of the crystal lattice. For example, irradiation with excimer laser energy may be performed at 100 to 300 mJ / cm ² .

This flattening effect is very effective when the crystal is irradiated with excimer laser ultraviolet light.

When the semiconductor film is irradiated with an excimer laser, the semiconductor film is instantaneously melted from the surface, and then the semiconductor film is cooled and solidified from the substrate side due to heat conduction to the substrate. During this solidification process, it is recrystallized to form a crystalline semiconductor film having a large grain size. However, once melted, volume expansion occurs, so that irregularities (ridges) occur on the surface of the semiconductor film. In the case of a top-gate type TFT, the device characteristics are greatly affected because the uneven surface is an interface with the gate insulating film.

Hereinafter, the effect of the high-temperature annealing of the present invention will be described with reference to experimental results by the present inventors.

First, the experimental procedure will be described. An amorphous silicon film having a thickness of 50 nm was formed on a quartz substrate. For film formation, reduced pressure CV
Using method D, disilane (Si ₂ H ₆ )
(Flow rate 250sccm), helium (He) (flow rate 300sccm)
cm). Substrate temperature 465 ° C., pressure during film formation is 0.5
torr.

The surface of the amorphous silicon film was etched with buffered hydrofluoric acid to remove a natural oxide film and contaminants. Next, XeCl excimer laser light was irradiated to crystallize the amorphous silicon film. The atmosphere at the time of laser irradiation is air, the substrate temperature is room temperature, the laser energy density is 400 mJ / cm ² , and the pulse width of the laser light is 1
50 nsec.

Then, the crystalline silicon film was subjected to a high-temperature annealing treatment. The conditions for the high-temperature annealing treatment were as follows. The atmosphere was 100% hydrogen, the degree of vacuum was 700 torr, the annealing temperature was 1000 ° C., and the annealing time was 25 minutes.
Before the high-temperature annealing, the crystalline silicon film was wet-etched with hydrofluoric acid to remove a natural oxide film and contaminants on the surface.

In order to confirm the effect of the high-temperature annealing, the surface of the crystalline silicon film before and after the high-temperature annealing was observed by SEM. FIG. 10 shows an observation photograph before the high-temperature annealing, and FIG. 11 shows an observation photograph after the high-temperature annealing. . As is clear from FIGS. 10 and 11, the surface shapes are clearly different before and after high-temperature annealing.

Further, the surface shape of the silicon film was also observed by AFM (atomic force microscope). FIG. 11 shows an AFM observation image of the crystalline silicon film before high-temperature annealing, and FIG. 12 shows an AFM observation image of the crystalline silicon film after high-temperature annealing.
The observation range was 1.5 μm × 1.
This is a rectangular area of 5 μm.

As is clear from FIGS. 11 and 12, the surface shape of the crystalline silicon film before and after the high-temperature annealing is clearly different. Before and after the high-temperature annealing, the surface of the crystalline silicon film has irregularities, but before the high-temperature annealing, the projections are steep and the tops are sharp, and the entire surface has a saw-tooth shape. It is considered that when the surface having such a convex portion becomes the interface between the gate insulating film and the channel formation region, the characteristics of the element are extremely adversely affected. In contrast, the convexities after the high-temperature annealing are smooth and the tops are rounded, so that the interface characteristics of the gate insulating film / channel formation region are improved as compared to before the high-temperature annealing.

From the observation images shown in FIGS. 9 to 13, it can be understood that the surface of the crystallized silicon film is flattened and smoothed by the high-temperature annealing. Hist of the height of the AFM image
The ogram (histogram) distribution was calculated. Furthermore this Histo
The Bearing Ratio curve of the gram distribution was calculated. BearingRati
The o curve is a curve indicating the cumulative frequency of the histogram distribution.

FIGS. 14 and 15 show a histogram of the height of the AFM image and a bearing ratio curve. FIG. 14 shows data before high-temperature annealing, and the pitch of the histogram is about 0.16 nm. FIG. 15 shows data after high-temperature annealing, and the pitch of the histogram is about 0.20 nm.

The measurement area by AFM is 1.5 μm × 1.
5 μm. The bearing ratio curve is a curve representing the cumulative frequency of the data of the histogram. The curves in FIGS. 14 and 15 are accumulated from the maximum value of the height, and show the ratio (%) of the area of an arbitrary height from the maximum value to the total area. In FIGS. 14 and 15, a horizontal line indicated by a dotted line in the graph indicates a half value of the PV value (Peak to Valley, the difference between the maximum value and the minimum value of the height).

Further, in the silicon film before and after the high-temperature annealing, an AFM image was observed in ten regions (a rectangular region of 1.5 μm × 1.5 μm), and 2 ⁻¹ (P
-V value) was calculated. FIG. 16 shows the bearing ratio and the statistical data in each observation region.

Comparing the curves in FIGS. 14 and 15, the height distribution before the high-temperature annealing is biased toward the lower part, but after the high-temperature annealing, the bias shifts to the higher side, and the histogram shows the PV. Are symmetrical with respect to the half of the position. This can be easily understood from the Bearing Ratio curve.

Bearing Ra at a height of 2 ^-1 (PV)
The tio is about 20% in FIG. 14 and about 51% in FIG.
It is. That is, the ratio of the area of the region whose height is in the range of 2 ⁻¹ (PV value) from the maximum value to the total area is about 20% before the high-temperature annealing, and after the high-temperature annealing. It is about 51%. From this difference in the ratio, it can be understood that the sharp top is rounded and the surface of the silicon film is smoothed by the high-temperature annealing.

[0037] Therefore, in the present invention, Rolling Bearings in the crystalline silicon film on the surface shape 2 ^-1 quantified by Rolling Bearings Ratio of (P-V value), 2 ^-1 (P-V value) from the experimental results Ra
The ratio occupied by the region whose height is in the range of 2 ⁻¹ (PV value) from the maximum value to the tio, that is, the predetermined observation region, is in the range of 6 to 28% in the film before the high-temperature annealing. The film after annealing is estimated to be 29-72%.

The range of the bearing ratio is shown in FIG.
2 ^-1 (P-V
Value) is a value calculated from the average ± 3σ of the Bearing Ratio in (Value). The bearing ratio is a value accumulated from the maximum height.

As described above, in the present invention, the crystalline semiconductor film crystallized by ultraviolet light such as excimer laser has its surface melted and crystallized. 1/2 of the difference between the maximum and minimum values from
The area occupied by the area is 6 to 28%,
By treating the crystalline semiconductor film by high-temperature annealing, the proportion of this region changes to 29 to 72%, and the tops of the projections on the film surface can be made gentle.

The experiment described above is an example in which an amorphous silicon film is irradiated with an excimer laser, but it is considered that the same surface shape is obtained when the crystalline silicon film of the present invention is irradiated. In the present invention, the bearing ratio before high-temperature annealing is considered to be larger than the experimental result,
aring Ratio is 29-72%, typically 35-60%
Is expected to be in the range.

In another aspect of the present invention, a step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, Performing a heat treatment to change a part or all of the amorphous semiconductor thin film into a crystalline semiconductor thin film; and performing a second heat treatment on the crystalline semiconductor thin film in a reducing atmosphere containing a halogen element. And having the following.

In this configuration, the second heat treatment is 900 to 1
It is performed at a temperature of 200 ° C. This step aims at the gettering action of the metal element by the halogen element,
It is an object of the present invention to halogenate and remove a catalyst element used for crystallization of an amorphous semiconductor thin film.

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention having the above configuration will be described in detail with reference to the following examples.

[0044]

[Embodiment 1] In this embodiment, a process of manufacturing a TFT on a substrate by implementing the present invention will be described. FIG. 1 is used for the description.

First, a quartz substrate was prepared as the substrate 101. As the substrate 101, a material having high heat resistance must be selected. Instead of a quartz substrate, a highly heat-resistant material such as a silicon substrate, a ceramic substrate, a crystallized glass substrate, or the like can be used.

When a quartz substrate is used, a base film may or may not be provided. However, when another material is used, an insulating film is preferably provided as a base film. As the insulating film, a silicon oxide film (SiOx), a silicon nitride film (Six N
y), a silicon oxynitride film (SiOxNy), an aluminum nitride film (AlxNy), or a laminated film thereof.

It is effective to use a base film in which a heat-resistant metal layer and a silicon oxide film are laminated, since the heat radiation effect is greatly increased. The heat dissipation effect is sufficient even with the above-described laminated structure of the aluminum nitride film and the silicon oxide film.

After the substrate 101 having the insulating surface was thus prepared, a crystalline silicon film 102 having a thickness of 30 nm was formed by utilizing the technique described in Japanese Patent Application Laid-Open No. Hei 7-130652. Since detailed means are described in the publication, only an outline will be described.

First, in this embodiment, disilane (Si ₂ H ₆ ) was used as a film forming gas. 20 to 6 by low pressure thermal CVD
An amorphous silicon film having a thickness of 0 nm was formed. At this time, it is important to thoroughly control the concentration of impurities such as C (carbon), N (nitrogen) and O (oxygen) mixed in the film. This is because the presence of many of these impurities hinders the progress of crystallization.

Applicants have reported that the carbon and nitrogen
Less than × 10 ¹⁸ atoms / cm ³ (preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 2 × 10 ¹⁷ atoms / cm ³ or less) Concentration is 1.5 × 10
^The impurity concentration was controlled so as to be ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less). The metal element was controlled to be 1 × 10 ¹⁷ atoms / cm ³ . If such concentration control is performed at the film formation stage, as long as external contamination is prevented, the impurity concentration will not increase during the TFT manufacturing process. The above concentration is SI
It is the value in the lowest concentration region of MS (mass secondary ion analysis).

After the formation of the amorphous silicon film, a catalytic element for promoting crystallization of the amorphous silicon film was added to the entire surface (all regions) of the amorphous silicon film. Specifically, a 10 ppm nickel acetate solution is applied by spin coating,
Dehydrogenation was performed at 50 ° C. for about 1 hour.

After that, an inert atmosphere and a hydrogen atmosphere
Or 500 to 700 ° C. in an oxygen atmosphere (typically,
Is 550 to 650 ° C) for 4 to 24 hours
Was added to obtain a crystalline silicon film 102. This crystalline silicon film
102 is 1 × 10 nickel ¹⁸~ 1 × 10¹⁹atoms / cm
^ThreeAt a concentration of. (Fig. 1 (A))

Strictly speaking, nickel was not added to the amorphous silicon film at the time of spin coating. However, nickel can be easily diffused into the amorphous silicon film in the subsequent hydrogen pouring step, so that it can be considered as a substantial addition step.

Incidentally, if a film quality equivalent to that of an amorphous silicon film formed by a low pressure thermal CVD method can be obtained, plasma CVD is used.
Method may be used. Also, an amorphous semiconductor thin film such as silicon germanium (expressed as Si _x xGe _1-x (0 <X <1)) containing germanium in the amorphous silicon film instead of the amorphous silicon film May be used. In this case, it is desirable that germanium contained in silicon germanium be 5 atomic% or less.

In addition to nickel, cobalt (C
o), iron (Fe), palladium (Pd), platinum (P
t), a lattice intrusion type catalyst element such as copper (Cu) or gold (Au) or a lattice substitution type (or fusion type) catalyst element such as germanium (Ge), lead (Pb) or tin (Sn). One or more types can be used.

When the state shown in FIG. 1A is obtained,
Next, the crystalline silicon film 102 was irradiated with ultraviolet light or infrared light. In this embodiment, the heat treatment was performed by excimer laser irradiation using XeCl as an excitation gas. The beam shape of the excimer laser may be a linear beam, but is preferably a planar beam in order to improve the uniformity of the processing.
(FIG. 1 (B))

The laser energy at this time is 100 to 2
It is desirable to carry out under the condition of 50 mJ / cm ² . If the energy is too strong, the continuity of the crystal lattice at the crystal grain boundaries may be impaired. Note that the step of irradiating the ultraviolet light or the infrared light may be omitted.

Thus, a crystalline silicon film 103 having improved crystallinity was obtained. Next, 900 to 1200 in a reducing atmosphere.
The heat treatment step was performed in a temperature range of ° C (preferably 1000 to 1150 ° C). In this embodiment, 105
Heat treatment was performed at 0 ° C. for 20 minutes. (Fig. 1 (C))

The reducing atmosphere is preferably a hydrogen atmosphere, an ammonia atmosphere, or an inert atmosphere containing hydrogen or ammonia (such as a mixed atmosphere of hydrogen and nitrogen or a mixture of hydrogen and argon). However, even in the inert atmosphere, the surface of the crystalline silicon film is flat. Is possible. However, it is preferable to reduce the natural oxide film by utilizing the reducing action, since many silicon atoms having high energy are generated, and as a result, the flattening effect is enhanced.

However, it is particularly necessary to keep the concentration of oxygen or oxygen compounds (for example, OH groups) contained in the atmosphere at 10 ppm or less (preferably 1 ppm or less). Otherwise, the reduction reaction by hydrogen will not occur.

Thus, a crystalline silicon film 104 was obtained. The surface of the crystalline silicon film 104 was extremely flattened by a hydrogen heat treatment at a high temperature of 900 to 1200 ° C.
Further, since the heat treatment was performed at a high temperature, there were almost no stacking faults or the like in the crystal grains. This will be described later.

When the crystalline silicon film 104 substantially regarded as a single crystal was obtained, the crystalline silicon film 104 was patterned to form an active layer 105. In this embodiment, the heat treatment is performed in a hydrogen atmosphere before forming the active layer. However, the heat treatment may be performed after forming the active layer. In that case, it is preferable that the patterning reduces the stress generated in the crystalline silicon film.

Then, a silicon oxide film 106 having a thickness of 10 nm was formed on the surface of the active layer 105 by performing a thermal oxidation step. This silicon oxide film 106 functions as a gate insulating film. Also,
The thickness of the active layer was 30 nm because the thickness of the active layer was reduced by 5 nm. It is necessary to determine the film thickness of the amorphous silicon film (starting film) in consideration of film reduction due to thermal oxidation so that an active layer (particularly, a channel forming region) having a thickness of 5 to 40 nm is finally left. It is.

After the gate insulating film 106 was formed, a polycrystalline silicon film having conductivity was formed thereon, and a gate wiring 107 was formed by patterning. (Fig. 1 (D))

In this embodiment, a polycrystalline silicon film having N-type conductivity is used as the gate wiring, but the material is not limited to this. In particular, it is effective to use tantalum, a tantalum alloy, or a stacked film of tantalum and tantalum nitride to reduce the resistance of the gate wiring. If a low-resistance gate wiring is aimed at, it is effective to use copper or a copper alloy.

When the state shown in FIG. 1D was obtained, an impurity imparting N-type conductivity or P-type conductivity was added to form an impurity region 108. At this time, the impurity concentration is
It was determined in consideration of the impurity concentration in the region. In this embodiment, 1 ×
Although arsenic was added at a concentration of 10 ¹⁸ atoms / cm ³ , neither the impurity nor the concentration need be limited to this embodiment.

Next, 5 to 10
A thin silicon oxide film 109 of about nm was formed. This may be formed using a thermal oxidation method or a plasma oxidation method. The purpose of forming the silicon oxide film 109 is to function as an etching stopper in the next sidewall formation step.

Silicon oxide film 1 serving as etching stopper
After the formation of 09, a silicon nitride film was formed and etched back to form a sidewall 110. Thus, the state shown in FIG.

Although the silicon nitride film is used as the side wall in this embodiment, a polycrystalline silicon film or an amorphous silicon film may be used. Needless to say, if the material of the gate wiring changes, the material that can be used as the sidewall changes accordingly.

Next, impurities of the same conductivity type as above were added again. The concentration of the impurity added at this time was higher than that in the previous step. In the present embodiment, arsenic is used as an impurity and the concentration is 1 × 10 ²¹ atoms / cm ³ , but it is not necessary to limit to this. The source region 111, the drain region 112, the LDD region 113, and the channel formation region 114 were defined by the impurity doping process. (FIG. 1 (F))

After the formation of each impurity region, the impurities were activated by heat treatment such as furnace annealing, laser annealing or lamp annealing.

Next, the gate wiring 107 and the source region 11
The silicon oxide films formed on the surfaces of the first and drain regions 112 were removed to expose those surfaces. And 5nm
A heat treatment process was performed after forming a cobalt film (not shown) to a degree. This heat treatment causes a reaction between cobalt and silicon, and the silicide layer (cobalt silicide layer) 11
5 was formed. (Fig. 1 (G))

This technique is a known salicide technique.
Therefore, titanium or tungsten may be used instead of cobalt, and the heat treatment conditions and the like may be referred to a known technique. In this embodiment, the heat treatment step was performed by irradiating infrared light.

After the formation of the silicide layer 115, the cobalt film was removed. Thereafter, an interlayer insulating film 116 having a thickness of 1 μm was formed. As the interlayer insulating film 116, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a resin film (polyimide, acrylic, polyamide, polyimide amide,
Benzocyclobutene (BCB) or the like may be used. Further, these insulating films may be stacked in any combination.

Next, a contact hole was formed in the interlayer insulating film 116 to form a source wiring 117 and a drain wiring 118 made of a material containing aluminum as a main component. Finally, the entire device was subjected to furnace annealing at 300 ° C. for 2 hours in a hydrogen atmosphere to complete hydrogenation.

Thus, a TFT as shown in FIG. 1 (G) was obtained. The structure described in this embodiment is an example, and the TFT structure to which the present invention can be applied is not limited to this. Therefore, the present invention can be applied to any known TFT. Also, the numerical conditions in the steps after the formation of the crystalline silicon film 104 need not be limited to the present embodiment. Furthermore, there is no problem if a known channel doping step (an impurity adding step for controlling a threshold voltage) is introduced somewhere in this embodiment.

In this embodiment, since the concentrations of impurities such as C, N, and O are thoroughly controlled at the stage of forming the amorphous silicon film as the starting film, the active layer of the completed TFT is formed. The concentration of each impurity contained in the
Oxygen concentration of 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less, more preferably 2 × 10 ¹⁷ atoms / cm ³ or less) But 1.5 × 10
^It remained at ¹⁹ atoms / cm ³ or less (preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less). The metal element was 1 × 10 ¹⁷ atoms / cm ³ or less.

It is needless to say that the present invention can be easily applied not only to a top gate structure but also to a bottom gate structure represented by an inverted staggered TFT.

In this embodiment, an N-channel TFT has been described as an example. However, it is easy to manufacture a P-channel TFT by combining with a known technique. Furthermore, if known technologies are combined, an N-channel type TF can be formed on the same substrate.
It is also possible to form a CMOS circuit by forming and combining T and P-channel TFTs complementarily.

Further, in the structure of FIG. 1G, a pixel electrode (not shown) electrically connected to the drain wiring 118
Is formed by known means, it is easy to form a pixel switching element of an active matrix display device.

That is, the present invention can be applied to the manufacture of an active matrix type electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.

[Knowledge on Crystal Structure of Active Layer] The active layer formed in accordance with the above-described manufacturing process has a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) when viewed microscopically.
Are considered to have a crystal structure arranged in a row.
This can be easily confirmed by observation with a TEM (transmission electron microscope). Further, it is also expected that the crystal lattice has a crystal structure in which continuity of the crystal lattice is very high.

The continuity of the crystal grain boundaries can be confirmed by using electron diffraction and X-ray diffraction. Although the surface (portion forming a channel) of the active layer made of crystalline silicon having a high continuity of the crystal lattice includes a slight shift in the crystal axis, the main orientation plane is {110} plane, and {110}. Diffraction spots corresponding to the surface appear clearly, but each spot has a distribution on concentric circles.

FIG. 8 schematically shows this state. FIG.
(A) is a diagram schematically showing a part of an electron beam diffraction pattern. In FIG. 8A, a plurality of bright points 1201 are diffraction spots corresponding to <110> incidence. The plurality of diffraction spots 1201 are distributed concentrically around the center point 1202 of the electron beam irradiation area.

Here, FIG. 8B shows an enlarged area 1203 surrounded by a dotted line. As shown in FIG. 8B, it can be seen that the diffraction spot 1201 has a distribution (fluctuation) with respect to the center point 1202 of the irradiation area.

An angle formed by a tangent 1204 drawn from the center point 1202 of the electron beam irradiation area to the diffraction spot 1201 and a line connecting the center point 1202 of the electron beam irradiation area and the center point 1205 of the diffraction spot is 2 ° or less.
At this time, since two tangent lines can be drawn, the diffraction spot 1201
Spread is within the range of ± 2 ° after all.

This tendency is observed in the entire region of the actual electron diffraction pattern, and is generally within ± 2 ° (typically within ± 1.5 °, preferably within ± 0.5 °). The fact that the diffraction spot has a distribution indicates such a situation.

It is known that such a distribution of diffraction spots appears when individual crystal grains having the same crystal axis are gathered in an arrangement rotated about the crystal axis. That is, the angle formed by a specific axis (called axis A) included in a certain crystal plane and an axis equivalent to axis A (called axis B) included in another adjacent crystal plane is defined as a rotation angle. In other words, the position where the diffraction spot appears is shifted by an amount corresponding to the rotation angle.

Therefore, when a plurality of crystal grains are aggregated in a positional relationship having a certain rotation angle, one electron beam diffraction pattern can be observed as an aggregate of diffraction spots indicated by individual crystal grains. .

When the diffraction spot has a spread within a range of ± 2 ° (typically ± 1.5 °, preferably ± 0.5 °), the rotation angle of an equivalent axis between adjacent crystal grains is set. It means that the absolute value is within 4 ° (typically within 3 °, preferably within 1 °).

When the crystal axis is the <110> axis, the <111> axis can be mentioned as an equivalent axis included in the crystal plane, but in the crystalline semiconductor thin film of the present invention, the <111> axes are 70 There are many crystal grain boundaries in contact with a rotation angle of 0.5 (or 70.4). Also in this case, it is considered that the equivalent axis has a rotation angle of 70.5 ° ± 2 °.

That is, in such a case, the absolute value of the rotation angle between the crystal grains formed by the equivalent axis or the axis having a rotational relationship of 70.5 ° with respect to the equivalent axis is within 4 ° ( (Typically within 3 °, preferably within 1 °).

Further, by observing the crystal grain boundaries by HR-TEM (high-resolution transmission electron microscopy), it is possible to confirm that the crystal lattice has continuity at the crystal grain boundaries. With HR-TEM, it can be easily confirmed whether or not the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafersby MBIC Measurement; Ryuichi Shim
okawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above-mentioned paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, when the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

In the crystalline silicon film obtained by the present applicant by carrying out the method of the present invention, most (90% or more, typically 95% or more) of the crystal grain boundaries are the corresponding grain boundaries of Σ3, that is, ｛. It can be a 211 ° twin grain boundary.

In the grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

The crystalline silicon film according to the present invention has a crystal grain boundary in which each lattice fringe of adjacent crystal grains is continuous at an angle of about 70.5 °, that is, the crystal grain boundary is a {211} twin grain boundary. It came to the conclusion that it was a crystalline silicon film.

When θ = 38.9 °, a corresponding grain boundary of Σ9 was obtained, but such other crystal grain boundaries also existed.

Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, such a corresponding grain boundary is formed over a wide range only when the plane orientation of the crystalline silicon film is approximately {110}.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, it can be considered that the crystalline semiconductor thin film having such a crystal structure has substantially no crystal grain boundary.

Further, defects present in crystal grains can be almost completely eliminated by the heat treatment step in a reducing atmosphere shown in FIG. This can be confirmed from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR). According to the manufacturing process of the first embodiment,
The spin density of the crystalline silicon film is at least 5 × 10 ¹⁷ spins /
cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

Further, since this heat treatment step is performed in a reducing atmosphere, particularly in a hydrogen atmosphere, slight residual defects are terminated by hydrogen and inactivated. Therefore, it is considered that defects in crystal grains may be regarded as substantially absent.

As described above, since the crystalline semiconductor thin film obtained by carrying out the present invention has substantially no inside of the crystal grains and no crystal grain boundary, the single crystal semiconductor thin film or the substantially single crystal semiconductor thin film is obtained. You can think.

[Knowledge Regarding Electrical Characteristics of TFT] The TF formed of the crystalline silicon film having a high continuity of the grain boundaries described above.
T indicates an electrical characteristic comparable to a MOSFET using pure single crystal silicon.

(1) The sub-threshold coefficient which is an index of the switching performance (the agility of switching on / off operation) is 60 to 100 mV / decade (typically 60 to 85 mV) for both the N-channel TFT and the P-channel TFT. / decade)
And small. (2) The field effect mobility (μFE) which is an index of the operation speed of the TFT is 200 to 65 for the N-channel type TFT.
0 cm ² / Vs (typically 300~500cm2 / Vs), 100~300cm in P-channel type TFT ² / Vs (typically 150～200Cm2 /
Vs). (3) The threshold voltage (Vth), which is an index of the driving voltage of the TFT, is -0.5 to 1.5 V for an N-channel TFT, and the threshold voltage (Vth) for a P-channel TFT.
It can be reduced to -1.5 to 0.5 V.

As described above, it has been confirmed that extremely excellent switching characteristics and high-speed operation characteristics can be realized.

[Knowledge on Circuit Characteristics] For example, the frequency characteristics of a ring oscillator can be improved. . The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape.
Used to determine the delay time per stage. The configuration of the ring oscillator is as follows. Number of steps: 9 steps T
FT gate insulating film thickness: 30 nm and 50 nm TFT gate length: 0.6 μm With such a ring oscillator, the oscillation frequency can be set to a maximum value of 1.04 GHz.

A shift register, which is one of the TEGs of the LSI circuit, is manufactured and operated at a frequency of 30 nm for a gate insulating film, a gate length of 0.6 μm, a power supply voltage of 5 V, and a shift register circuit having 50 stages. , 100 MHz output pulse can be generated.

The surprising data of the ring oscillator and the shift register as described above indicate that the TFT using crystalline silicon having a continuous grain boundary is comparable to the IGFET using single crystal silicon, or It shows that it has superior performance.

(Example 2) In Example 1, a catalytic element for promoting crystallization is added to the entire surface (entire region) of the amorphous silicon film. May be added. In that case, Japanese Patent Laid-Open No. 7-1
The means described in Example 2 of Japanese Patent No. 30652 was used.

In general, after an amorphous silicon film is formed, an insulating film is selectively provided, and a catalytic element for promoting crystallization is added using the insulating film as a mask. Specifically, after providing a mask made of a silicon oxide film, a nickel acetate solution is applied by a spin coating method to produce hydrogen (the conditions are the same as those in Example 1).
Same as above).

When a heat treatment step for crystallization was performed in this state, crystallization was started from a portion which was in direct contact with nickel, and crystallization proceeded under the mask.
As a result, a crystal region in which the crystal was grown in a direction substantially parallel to the substrate could be obtained. The present applicant calls a crystal region having such characteristics a lateral growth region. Since nickel is not directly added to the lateral growth region, the concentration of nickel contained after crystallization is about 1 × 10 ^{18 to} 5 × 10 ¹⁸ atoms / cm ^3, which is about an order of magnitude lower than in the case where crystallization is performed by direct contact. .

Therefore, an active layer having a small content of a catalytic element such as nickel could be obtained by leaving only the lateral growth region in an island shape by patterning and using it as an active layer of a TFT.

In the case of this embodiment, first, the crystallization step is performed by the above-described means, and the formed crystalline silicon film (actually, only the nickel-added portion and the lateral growth region are crystallized.
The other portions remain amorphous). This crystal structure is microscopically the same as in Example 1, but differs from Example 1 in that individual rod-shaped crystals are macroscopically arranged with a specific direction.

FIGS. 1B to 1C described in the first embodiment.
Through the steps up to FIG. 1G, a TFT was formed. The TFT thus formed and a circuit formed by such a TFT exhibited excellent electrical characteristics similar to those of the first embodiment.

(Embodiment 3) In this embodiment, before performing the hydrogen annealing step at 900 to 1200 ° C. in Embodiment 1 or 2, a catalytic element (nickel Will be described below.

In the present embodiment, the gettering action of a halogen element is used to remove nickel from the film.
This is a technique that utilizes the fact that a halogen element and nickel combine to form a volatile nickel halide. In this technique, a crystalline silicon film is placed in an atmosphere containing a halogen element, and is heated to 700 to 1150 ° C. (typically, 950 to 1150 ° C.).
(1100 ° C.) for about 0.5 to 8 hours.

In this example, the processing substrate was placed in a gas mixture of oxygen and hydrogen chloride, and the heat treatment was performed at 950 ° C. for 1 hour. By this step, the concentration of nickel remaining in the crystalline silicon film could be reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. ^{Incidentally, 1 × 10 1 7 atoms /} cm 3 near the SI
Since it is the lower limit of measurement of MS (mass secondary ion analysis), it is actually expected that it exists at a concentration of about 1 × 10 ¹⁴ atoms / cm ³ to 1 × 10 ¹⁶ atoms / cm ³ .

Further, the gettering step using the halogen element may be performed before or after the hydrogen annealing step performed at a temperature of 900 to 1200 ° C. Further, the hydrogen annealing step and the gettering step can be combined. In this case, the heat treatment step may be performed at 900 to 1200 ° C. in an atmosphere in which 0.1 to 5 wt% of hydrogen halide (typically, hydrogen chloride) is mixed in a hydrogen atmosphere. When gettering with halogen elements in a reducing atmosphere,
Since the crystalline silicon film is not oxidized, no problem such as abnormal growth of the silicon oxide film occurs.

By adopting this embodiment, the catalytic element can be removed or reduced from the crystalline silicon film. Since the concentration of the catalytic element is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less, it is possible to prevent the TFT characteristics (in particular, the off-current value) from being varied due to the presence of the catalytic element.

(Embodiment 4) In the present embodiment, before performing the hydrogen annealing step at 900 to 1200 ° C. in Embodiment 1 or 2, a catalytic element (nickel The following describes a case in which means different from that of the third embodiment is used when removing the third embodiment.

FIG. 2 is used for the description. First, the amorphous silicon film was crystallized through the steps described in Example 2. Specifically, an amorphous silicon film (not shown) is formed on a quartz substrate 201.
Was formed, and a mask 202 made of a silicon oxide film was formed thereon. Then, in this state, a heat treatment step for crystallization was performed by spin-coating a nickel salt. In this embodiment, the heat treatment was performed at 570 ° C. for 14 hours. The lateral growth region 203 was obtained by this heat treatment step (crystallization step). (Fig. 2 (A))

Next, an element selected from Group 15 (phosphorus in this embodiment) was added using the mask 202 as a mask. Any known method such as an ion implantation method, a plasma doping method, or a gas phase diffusion method may be used. (FIG. 2 (B))

Thus, a region 204 to which phosphorus was added was formed in the crystalline silicon film exposed through the opening of the mask 202. In this embodiment, this region is referred to as a gettering region for convenience. The addition amount was adjusted so that the concentration of phosphorus contained in the gettering region 204 was 1 × 10 ¹⁹ to 1 × 10 ²¹ atoms / cm ³ .

After forming the gettering region 204, 5
The gettering step is performed by performing a heat treatment in a temperature range of 50 to 750 ° C (preferably 600 to 650 ° C) for 2 to 24 hours (preferably 8 to 12 hours). In this embodiment, a heat treatment step at 600 ° C. for 12 hours was performed. (Figure 2
(C))

As a result, nickel contained in the lateral growth region 203 was caught (gettered) in the gettering region 204, and a lateral growth region 205 with a significantly reduced nickel concentration was obtained. The concentration of nickel contained in the lateral growth region 205 was 1 × 10 ¹⁷ atoms / cm ³ or less. However, as described in the third embodiment, 1 × 10 ¹⁷ atom
Since the vicinity of s / cm ³ is the lower limit of measurement by SIMS (Secondary Mass Ion Analysis), it is actually expected to be reduced to about 1 × 10 ¹⁶ atoms / cm ³ or less.

Next, patterning is performed to form a lateral growth region 2.
Active layers 206 and 207 composed of only 05 were formed. Then, a heat treatment step at 1050 ° C. for 1 hour was performed in a hydrogen atmosphere to flatten the active layer surface and improve the crystallinity. Of course, the heat treatment conditions are not limited to this embodiment.

The reason why hydrogen annealing was performed after the active layer was formed was that if heat treatment was performed at 800 ° C. with the gettering region remaining, phosphorus would diffuse back into the lateral growth region. is there. It is preferable to perform hydrogen annealing after completely removing the gettering region as in this embodiment, since phosphorus is not mixed into the channel formation region.

After the state shown in FIG. 2D is obtained, the TFT may be manufactured according to the manufacturing process described in the first embodiment. Of course, even if the TFT is manufactured by other known means, the effect of the present invention is not spoiled.

Before the step (D) of FIG. 2D (hydrogen annealing step), a step of irradiating the crystalline silicon film (or the active layer after patterning) with ultraviolet light or infrared light may be performed. I do not care. In that case, as shown in Example 1,
Care must be taken not to break the continuity of the crystal lattice at the grain boundaries.

Further, before performing the gettering step (FIGS. 2B and 2C), the heat treatment step of FIG. 2D may be performed. In this case, it is necessary to perform hydrogen gettering after removing the mask 202 once, and then perform a gettering step by re-forming the mask.

Embodiment 5 In this embodiment, an example in which a source region and a drain region are used for gettering a catalytic element (nickel in this embodiment) using phosphorus will be described. FIG. 3 is used for the description.

First, an N-channel TFT 301 and a P-channel TFT 302 were formed according to the manufacturing process of the first embodiment. Although an example of a manufacturing process of a P-channel TFT is not described in Embodiment 1, since the structure is the same as that of an N-channel TFT, the conductivity type of the impurity added to the active layer is 1
What is necessary is just to change to the element (typically, boron) selected from Group III.

Thus, the state shown in FIG. 3A was obtained. The source region 303 and the drain region 304 of the N-channel TFT 301 are formed by adding phosphorus at a concentration of 5 × 10 ²⁰ atoms / cm ³ . Also, a P-channel type TFT 302
Source region 305 and drain region 306 are 5 × 10
Phosphorus at a concentration of ²⁰ atoms / cm ³ and boron at a concentration of 1.5 × 10 ²¹ atoms / cm ³ are added.

Next, 500 to 650 in the state of FIG.
A heat treatment step (gettering step) was performed at 1 ° C. for 1 to 12 hours (500 ° C. for 1 hour in this embodiment). At this time, the source regions 303 and 305 and the drain regions 304 and 306
Each functioned as a gettering region. On the P-channel type TFT 305 side, it was possible to getter nickel well despite the fact that the concentration of boron was higher than that of phosphorus.

In this gettering step, nickel is moved and gettered from the channel formation region immediately below the gate wiring to the adjacent source and drain regions. Therefore, the nickel concentration in the channel formation region is 1 × 10 ¹⁷ atoms / cm ³ or less (probably 1 × 10 ¹⁶ ato
ms / cm ³ or less).

The gettering process shown in this embodiment can be combined with any of the first to fourth embodiments.

Embodiment 6 In this embodiment, an example of a reflection type liquid crystal display device manufactured according to the present invention is shown in FIG. A well-known means may be used for a method of manufacturing a pixel TFT (pixel switching element) and a cell assembling step, and a detailed description thereof will be omitted.

In FIG. 4A, reference numeral 11 denotes a substrate having an insulating surface (ceramic substrate provided with a silicon oxide film);
Is a pixel matrix circuit, 13 is a source driver circuit,
14 is a gate driver circuit, 15 is a counter substrate, 16 is an FPC (flexible printed circuit), and 17 is a signal processing circuit. As the signal processing circuit 17, D / A
Conventional ICs such as converters, gamma correction circuits, and signal division circuits
Thus, a circuit for performing the processing similar to the above can be formed. Of course, an IC chip is provided on a glass
It is also possible to perform signal processing on a chip.

Further, in this embodiment, a liquid crystal display device is described as an example. However, if the display device is an active matrix type display device, the present invention is applied to an EL (electroluminescence) display device and an EC (electrochromics) display device. It goes without saying that the invention can be applied.

Here, the driver circuit 13 shown in FIG.
FIG. 4B shows an example of a circuit constituting the circuit 14. In addition,
Since the TFT portion has already been described in the first embodiment, only necessary portions will be described here.

In FIG. 4B, reference numerals 401 and 402 denote N.
A channel TFT 403 is a P-channel TFT, and a TFT 401 and a TFT 403 constitute a CMOS circuit. Reference numeral 404 denotes an insulating layer formed of a laminated film of a silicon nitride film / silicon oxide film / resin film, on which a titanium wiring 405 is provided, and the above-described CMOS circuit and the TFT 402 are electrically connected. The titanium wiring is further covered with an insulating layer 406 made of a resin film. The two insulating layers 404 and 406 also have a function as a planarization film.

Also, the pixel matrix circuit 1 shown in FIG.
FIG. 4C shows a part of the circuit constituting the second circuit. FIG.
In FIG. 4C, reference numeral 407 denotes a pixel TFT formed of an N-channel TFT having a double gate structure, and a drain wiring 408 is formed so as to largely spread in a pixel region. Note that a single gate structure, a triple gate structure, or the like may be employed in addition to the double gate structure.

An insulating layer 404 is provided thereon, and a titanium wiring 405 is provided thereon. At this time, a recess is formed in a part of the insulating layer 404, and only the lowermost silicon nitride and silicon oxide are left.
Thus, an auxiliary capacitance is formed between the drain wiring 408 and the titanium wiring 405.

Further, the titanium wiring 405 provided in the pixel matrix circuit has an electric field shielding effect between the source / drain wiring and the subsequent pixel electrode. Further, in a gap between a plurality of provided pixel electrodes, it also functions as a black mask.

Then, an insulating layer 406 is provided to cover the titanium wiring 405, and a pixel electrode 409 made of a reflective conductive film is formed thereon. Of course, the surface of the pixel electrode 409 may be devised to increase the reflectance.

Although an alignment film and a liquid crystal layer are actually provided on the pixel electrode 409, the description is omitted here.

By using the present invention, a reflection type liquid crystal display device having the above configuration can be manufactured. Of course, a transmission type liquid crystal display device can be easily manufactured by combining with a known technique. Further, an active matrix EL display device can be easily manufactured by combining with a known technique.

Although not distinguished in the drawings, the thickness of the gate insulating film can be made different between the pixel TFT forming the pixel matrix circuit and the CMOS circuit forming the driver circuit and the signal processing circuit.

In the pixel matrix circuit, since the driving voltage applied to the TFT is high, a gate insulating film having a thickness of about 50 to 200 nm is required. On the other hand, in a driver circuit or a signal processing circuit, a driving voltage applied to a TFT is low, and a high-speed operation is required.
It is effective to make it as thin as about nm and smaller than the pixel TFT.

(Embodiment 7) Various liquid crystals other than the TN liquid crystal can be used in the liquid crystal display device manufactured by the above embodiment. For example, 1998, SID, "Charac
teristics and Driving Scheme of Polymer-Stabilized
Monostable FLCD ExhibitingFast Response Time and
High Contrast Ratio with Gray-Scale Capability "by
H. Furue et al., 1997, SID DIGEST, 841, "A Full
-Color ThresholdlessAntiferroelectric LCD Exhibiti
ng Wide Viewing Angle with Fast Response Time "by
T. Yoshida et al., 1996, J. Mater. Chem. 6 (4), 6
71-673, "Thresholdless antiferroelectricity in liq
uid crystals and its application todisplays "by S.
The liquid crystal disclosed in Inui et al. And US Pat. No. 5,594,569 can be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal. As a mixed liquid crystal having an antiferroelectric liquid crystal, there is a so-called thresholdless antiferroelectric mixed liquid crystal exhibiting an electro-optical response characteristic in which transmittance changes continuously with an electric field. This thresholdless antiferroelectric mixed liquid crystal has a V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V (cell thickness is about 1 μm to 2 μm).
m) have also been found.

Here, FIG. 9 shows an example showing characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response. The vertical axis of the graph shown in FIG. 9 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. In addition,
The transmission axis of the polarizing plate on the incident side of the liquid crystal display device is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal, which substantially matches the rubbing direction of the liquid crystal display device. The transmission axis of the exit-side polarizing plate is substantially perpendicular to the transmission axis of the incidence-side polarizing plate (crossed Nicols).
Is set to

As shown in FIG. 9, it is understood that the use of such a thresholdless antiferroelectric mixed liquid crystal enables low-voltage driving and gradation display.

When such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having an analog driver, the power supply voltage of the image signal sampling circuit is, for example, about 5 V to 8 V. It becomes possible to suppress to. Therefore, the operating power supply voltage of the driver can be reduced, and low power consumption and high reliability of the liquid crystal display device can be realized.

Also, when such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device having a digital driver, the output voltage of the D / A conversion circuit can be reduced. , The operating power supply voltage of the D / A conversion circuit, and the operating power supply voltage of the driver can be lowered. Therefore, low power consumption and high reliability of the liquid crystal display device can be realized.

Therefore, the use of such a low-voltage driven thresholdless antiferroelectric mixed liquid crystal can prevent the use of a TFT (for example, a TFT having a relatively small LDD region (low-concentration impurity region)).
(0 nm to 500 nm or 0 nm to 200 nm) is also effective.

In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and a high dielectric constant of the liquid crystal itself. Therefore, when a thresholdless antiferroelectric mixed liquid crystal is used for a liquid crystal display device, a relatively large storage capacitance is required for a pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. Further, by making the driving method of the liquid crystal display device line-sequential driving, the writing period (pixel feed period) of the gray scale voltage to the pixel may be lengthened to compensate for the small storage capacitance. .

Since low-voltage driving is realized by using such a thresholdless antiferroelectric mixed liquid crystal, low power consumption of the liquid crystal display device is realized.

Any liquid crystal having electro-optical characteristics as shown in FIG. 9 can be used as the display medium of the liquid crystal display of the present invention.

(Embodiment 8) The present invention can be applied to all conventional IC technologies. That is, the present invention can be applied to all semiconductor circuits currently on the market. For example, RISC processor, ASI integrated on one chip
The invention may be applied to a microprocessor such as a C processor, or may be applied to a signal processing circuit such as a D / A converter to a high-frequency circuit for a portable device (mobile phone, PHS, mobile computer).

FIG. 5 shows an example of a microprocessor. The microprocessor typically includes a CPU core 21, a RAM 22, a clock controller 23, a cache memory 24, a cache controller 25, a serial interface 26, an I / O port 27, and the like.

Of course, the microprocessor shown in FIG. 5 is a simplified example, and an actual microprocessor is designed for various circuits depending on the application.

However, even if a microprocessor having any function functions as a center, it is an IC (Integer).
grated circuit) 28. The IC 28 is a functional circuit in which an integrated circuit formed on the semiconductor chip 29 is protected by ceramic or the like.

The integrated circuit formed on the semiconductor chip 29 is composed of the N-channel TFT 30 and the P-channel TFT 31 having the structure of the present invention. Note that power consumption can be suppressed by configuring a basic circuit with a CMOS circuit as a minimum unit.

The microprocessor shown in this embodiment is mounted on various electronic devices and functions as a central circuit. Representative electronic devices include personal computers, portable information terminal devices, and all other home appliances. Further, a computer for controlling a vehicle (an automobile, a train, or the like) is also included.

(Embodiment 9) A CMOS circuit and a pixel matrix circuit formed by implementing the present invention are used for various electro-optical devices (active matrix type liquid crystal display, active matrix type EL display, active matrix type EC display). be able to. That is, the invention of the present application can be applied to all electronic devices incorporating such electro-optical devices as display media.

Examples of such electronic devices include a video camera, a digital camera, a projector (rear or front type), a head mounted display (goggle type display), a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone). Or an electronic book). Examples of these are shown in FIGS.

FIG. 6A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display device 20.
03, a keyboard 2004. The present invention can be applied to the image input unit 2002, the display device 2003, and other signal control circuits.

FIG. 6B shows a video camera,
101, display device 2102, audio input unit 2103, operation switch 2104, battery 2105, image receiving unit 210
6. The present invention can be applied to the display device 2102, the audio input unit 2103, and other signal control circuits.

FIG. 6C shows a mobile computer (mobile computer), which includes a main body 2201 and a camera section 2.
202, an image receiving unit 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 and other signal control circuits.

FIG. 6D shows a goggle type display, which includes a main body 2301, a display device 2302, and an arm 230.
3 The present invention can be applied to the display device 2302 and other signal control circuits.

FIG. 6E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display device 2402, and a speaker unit 24.
03, a recording medium 2404, and operation switches 2405. This device uses a DVD (Di) as a recording medium.
A digital versatile disc), a CD, and the like can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display device 2402 and other signal control circuits.

FIG. 6F shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown).
The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 7A shows a front type projector, which comprises a display device 2601 and a screen 2602. The present invention can be applied to a display device and other signal control circuits.

FIG. 7B shows a rear type projector, which includes a main body 2701, a display device 2702, and a mirror 270.
3. It is composed of a screen 2704. The present invention can be applied to a display device and other signal control circuits.

Note that FIG. 7 (C) is similar to FIG. 7 (A) and FIG.
FIG. 3B is a diagram illustrating an example of the structure of the display devices 2601 and 2702 in FIG. Display devices 2601, 2702
Are light source optical system 2801, mirror 2802, 2805
2807, dichroic mirrors 2803, 2804,
It comprises optical lenses 2808, 2809, 2811, a liquid crystal display device 2810, and a projection optical system 2812. The projection optical system 2812 is configured by an optical system having a projection lens. In this embodiment, an example of a three-panel type using three liquid crystal display devices 2810 has been described. However, the present invention is not particularly limited, and may be a single-panel type. In addition, the practitioner may appropriately place an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR light on an optical path indicated by an arrow in FIG.
An optical system such as a film may be provided.

FIG. 7D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 7C.
In this embodiment, the light source optical system 2801 includes a light source 2813,
2814, synthetic prism 2815, collimator lens 2
816, 2820, lens arrays 2817, 2818,
A polarization conversion element 2819 is provided. FIG. 7D
The light source optical system shown in (2) uses two light sources.
Four or more light sources may be used.
One may be used. Further, the practitioner may appropriately provide an optical lens, a film having a polarizing function, a film for adjusting a phase difference, an IR film, or the like to the light source optical system.

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to eighth embodiments.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a thin film transistor.

FIG. 2 illustrates a manufacturing process of a thin film transistor.

FIG. 3 illustrates a manufacturing process of a thin film transistor.

FIG. 4 is a diagram illustrating a configuration of an electro-optical device.

FIG. 5 illustrates a structure of a semiconductor circuit.

FIG. 6 illustrates a structure of an electronic device.

FIG. 7 illustrates a structure of an electronic device.

FIG. 8 is a view schematically showing an electron diffraction pattern.

FIG. 9 is a characteristic diagram of a thresholdless antiferroelectric mixed liquid crystal.

FIG. 10: SE on the surface of a crystalline silicon film before high-temperature annealing
M observation photograph.

FIG. 11 SE on the surface of a crystalline silicon film after high-temperature annealing
M observation photograph.

FIG. 12: AF of crystalline silicon film surface before high-temperature annealing
M image.

FIG. 13: AF on the surface of a crystalline silicon film after high-temperature annealing
M image.

FIG. 14: Histog of AFM image height before high-temperature annealing
ram (histogram) distribution, bearing ratio curve.

FIG. 15: Histog of AFM image height after high temperature annealing
ram (histogram) distribution, bearing ratio curve.

FIG. 16 shows statistical data of a bearing ratio at 1/2 of PV.

Continued on front page F-term (reference) GG47 GG54 HJ01 HJ04 HJ23 HL03 HM15 NN02 PP03 PP06 PP10 PP13 PP23 PP29 PP34 PP35 PP38 QQ11 QQ28

Claims (20)

[Claims] 1. The carbon and nitrogen content is 5 × 10 ¹⁸ atom
s / cm ³ or less and the oxygen content is 1.5 × 10 ¹⁹ atoms / cm ³
The main orientation plane is the {110} plane, and the absolute value of the rotation angle between the adjacent crystal grains and an equivalent axis or an axis having a rotational relationship of 70.5 ° with respect to the equivalent axis Is less than 4 °, has a thickness of 5 to 40 nm, and is a single crystal or substantially a single crystal. 2. The carbon and nitrogen content is 1 × 10 ¹⁸ atom
s / cm ³ or less and the oxygen content is 5 × 10 ¹⁸ atoms / cm ³ or less, the main orientation plane is {110} plane, and an equivalent axis or an equivalent axis between adjacent crystal grains. 7
A crystal characterized by having an absolute value of a rotation angle formed by an axis having a rotation relationship of 0.5 ° within 4 °, a film thickness of 5 to 40 nm, and being a single crystal or substantially a single crystal Semiconductor thin film. 3. The carbon and nitrogen content is 5 × 10 ¹⁸ atoms.
s / cm ³ or less and the oxygen content is 1.5 × 10 ¹⁹ atoms / cm ³
The main orientation plane is the {110} plane, and the absolute value of the rotation angle between the adjacent crystal grains and an equivalent axis or an axis having a rotational relationship of 70.5 ° with respect to the equivalent axis Is within 4 °, has a thickness of 5 to 40 nm, has a semiconductor thin film of single crystal or substantially single crystal, and has a circuit including a thin film transistor including the semiconductor thin film as a channel formation region. A semiconductor device characterized by the above-mentioned. 4. A carbon and nitrogen content of 1 × 10 ¹⁸ atom
s / cm ³ or less and the oxygen content is 5 × 10 ¹⁸ atoms / cm ³ or less, the main orientation plane is {110} plane, and an equivalent axis or an equivalent axis between adjacent crystal grains. The absolute value of the rotation angle formed by the axis having a rotation relationship of 70.5 ° is within 4 °, the individual crystal grains contact each other at a rotation angle, and the absolute value of the rotation angle is within 4 °, A semiconductor device having a thickness of 5 to 40 nm, a semiconductor thin film that is single crystal or substantially single crystal, and a circuit including a thin film transistor including the semiconductor thin film as a channel formation region. 5. A step of adding a catalytic element that promotes crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, and performing a first heat treatment, Changing part or all of the region of the crystalline semiconductor thin film into a crystalline semiconductor thin film;
Performing a second heat treatment at 1200 ° C., and a method for manufacturing a crystalline semiconductor thin film. 6. A step of adding a catalytic element that promotes crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, and performing a first heat treatment, Converting a part or the entire region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; and performing a second heat treatment on the crystalline semiconductor thin film in a reducing atmosphere containing a halogen element. For producing a crystalline semiconductor thin film. 7. The method for manufacturing a crystalline semiconductor thin film according to claim 6, wherein the second heat treatment is performed at 900 to 1200 ° C. 8. The method according to claim 5, wherein in the second heat treatment, the concentration of oxygen or an oxygen compound is 10 ppm.
A method for producing a crystalline semiconductor thin film, which is performed in a reducing atmosphere described below. 9. A step of adding a catalyst element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film; Converting a part or the entire region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; irradiating the crystalline semiconductor thin film with ultraviolet light or infrared light as a second heat treatment; 900 ~ in a reducing atmosphere
Performing a third heat treatment at 1200 ° C., and a method for manufacturing a crystalline semiconductor thin film. 10. A step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film; Converting a part or the entire region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; irradiating the crystalline semiconductor thin film with ultraviolet light or infrared light as a second heat treatment; Performing a third heat treatment in a reducing atmosphere containing a halogen element on the crystalline semiconductor thin film. 11. The method according to claim 10, wherein the third heat treatment is performed at 900 to 1200 ° C. 12. The method for manufacturing a crystalline semiconductor thin film according to claim 9, wherein the third heat treatment is performed in a reducing atmosphere in which the concentration of oxygen or an oxygen compound is 10 ppm or less. 13. A step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film; Changing part or all of the region of the crystalline semiconductor thin film into a crystalline semiconductor thin film;
Performing a second heat treatment at 1200 ° C .; and a thin film transistor formed through the following steps. 14. A step of adding a catalytic element that promotes crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, and performing a first heat treatment, Changing a part or all of the region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; and performing a second heat treatment on the crystalline semiconductor thin film in a reducing atmosphere containing a halogen element. A method for manufacturing a semiconductor device, including a thin film transistor. 15. The method for manufacturing a semiconductor device according to claim 14, wherein the second heat treatment is performed at 900 to 1200 ° C. 16. The method according to claim 13, wherein
In the second heat treatment, the concentration of oxygen or an oxygen compound is 10 ppm.
A method for producing a crystalline semiconductor thin film, which is performed in a reducing atmosphere described below. 17. A step of adding a catalytic element for promoting crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, Converting a part or the entire region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; irradiating the crystalline semiconductor thin film with ultraviolet light or infrared light as a second heat treatment; 900 ~ in a reducing atmosphere
Performing a third heat treatment at 1200 ° C .; and a thin film transistor formed therethrough. 18. A step of adding a catalyst element that promotes crystallization of the amorphous semiconductor thin film to a part or all of the region on the amorphous semiconductor thin film, and performing a first heat treatment, Converting a part or the entire region of the crystalline semiconductor thin film into a crystalline semiconductor thin film; irradiating the crystalline semiconductor thin film with ultraviolet light or infrared light as a second heat treatment; Performing a third heat treatment on the thin film in a reducing atmosphere containing a halogen element; and a thin film transistor formed through the steps of: 19. The method for manufacturing a semiconductor device according to claim 18, wherein the third heat treatment is performed at 900 to 1200 ° C. 20. The method according to claim 17, wherein
In the third heat treatment, the concentration of oxygen or oxygen compound is 10 ppm.
A method for producing a crystalline semiconductor thin film, which is performed in a reducing atmosphere described below.