JP2001028450A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge the area of the p-n junction plane to the area of a polydiode forming region to make it usable for highly integrated semiconductor memory by forming the p-n junction plane with substantially horizontal section of a plug to the top or bottom end face or a substrate surface. SOLUTION: An n-type polycrystalline Si layer is deposited by the CVD method so as to fill up openings 6 and cover a layer insulation film 5, the n-type polycrystalline Si layer on the layer insulation film 5 is removed by the etch back method, with leaving n-type polycrystalline Si plugs 7 in only the openings 6, and then BF2 ions are implanted to form p-type polycrystalline Si plugs 8 on substantially upper halves of the n-type polycrystalline Si plugs 7. As the result the n-type and p-type polycrystalline Si plugs 7, 8 form junctions which are substantially parallel to on a Si substrate 1, thus forming p-n junction planes 9. Since the sectional area of the opening 6 is the p-n junction area, the p-n junction area can be enlarged.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical poly-diode, and more particularly to a vertical poly-diode used in a charge pump type booster circuit of a highly integrated semiconductor memory device.

[0002]

2. Description of the Related Art A semiconductor memory device generally incorporates a charge pump type booster circuit including a diode and a capacitor in order to boost a power supply voltage to a predetermined voltage. 7 and 8 are a cross-sectional view and a plan view of a poly-diode used in the booster circuit. As shown in these drawings, the polydiode has a silicon (Si) substrate 101.
On a silicon substrate 101, a silicon dioxide (SiO ₂ ) layer 102 is formed. The silicon dioxide layer 102 partially supports a thin p-type (p ⁺ ) polycrystalline silicon layer 104 and an n-type (n ⁺ ) polycrystalline silicon layer 103. A PN junction 105 is formed between the silicon layers 103 and 104. The silicon dioxide layer 102 is also covered with an interlayer insulating film 106. The polycrystalline silicon layers 103 and 104 are provided in the interlayer insulating film 106.
Are formed through the interlayer insulating film 106, and these openings are filled with tungsten plugs 107, respectively. The interlayer insulating film 106 also supports the aluminum electrode 108 on the surface thereof and on the tungsten plug 107, so that the polysilicon layers 103 and 104 are electrically connected to the aluminum electrode 108 through the tungsten plug 106. Connected.

[0003]

However, in the polysilicon diode shown in FIGS. 7 and 8, the PN junction 105 is connected to the connection between the p-type polysilicon layer 104 and the n-type polysilicon layer 103 by a silicon substrate. 101, the two polycrystalline silicon layers 103, 1
04 has a small bonding area. In particular, when a poly-diode is incorporated into a highly integrated semiconductor device such as a semiconductor memory device, the thickness of the polycrystalline silicon layer is limited by the element structure, and the thickness of the polycrystalline silicon film is increased to increase the PN junction. It is difficult to increase the area. For this reason, even if a predetermined voltage is applied to the polysilicon diode, both polycrystalline silicon layers 10
The required current was not obtained between 3,104.

It is an object of the present invention to provide a small-sized vertical poly-diode having a large PN junction area, which can be used for a highly integrated semiconductor memory device.

[0005]

Therefore, as a result of diligent research, the present inventors have formed a plug buried in an insulating film between a lower electrode and an upper electrode with polycrystalline silicon, and formed a cross section of the plug with a polycrystalline silicon.
The present inventors have found that the use of the N-junction surface makes it possible to increase the PN junction surface even in a highly integrated semiconductor device, and that the area of the PN junction surface can be arbitrarily set by changing the diameter of the plug.

That is, according to the present invention, a PN junction surface is formed between a first conductivity type polysilicon region and a second conductivity type polysilicon region provided on an insulating film on a substrate. A semiconductor device including a vertical poly-diode, comprising: a lower electrode laminated on an insulating film on the substrate; an insulating layer formed to cover the lower electrode; and an upper layer laminated on the insulating layer. An electrode, a plug buried in an opening provided in the insulating layer, the upper end and the lower end of which include a plug connected to the upper electrode and the lower electrode, respectively, wherein the plug is made of polycrystalline silicon; A semiconductor device including a vertical poly-diode, wherein a cross section of the plug in a direction substantially horizontal to an upper end surface, a lower end surface, or the substrate surface is a PN junction surface. As described above, by providing the PN junction surface in the substrate in a substantially horizontal direction, the area of the PN junction surface with respect to the area of the poly-diode formation region can be increased as compared with the conventional horizontal polysilicon diode. Therefore, even when a polydiode is incorporated in a highly integrated semiconductor device, the PN junction area can be increased, and the current flowing through the polydiode can be increased.

The plug comprises a first conductivity type polycrystalline silicon buried on the substrate side of the opening, and a second conductivity type polycrystalline silicon buried thereon.
The boundary surface between these polycrystalline silicons may be the PN junction surface.

The plug is made of polycrystalline silicon of the first conductivity type, the upper electrode is made of polycrystalline silicon of the second conductivity type, and the boundary between these polycrystalline silicons is the PN junction surface. Is also good.

The plug is made of polycrystalline silicon of the first conductivity type, the lower electrode is made of polycrystalline silicon of the second conductivity type, and the boundary between these polycrystalline silicons is the PN junction surface. Is also good.

A lower end of the plug is embedded in the lower electrode, and a boundary surface between a side wall of the lower end and the lower electrode is
Further, it is preferable to form the PN junction surface. With this structure, the area of the PN junction surface can be further increased.

The present invention also relates to a method of manufacturing a semiconductor device having a vertical type poly-diode having a PN junction surface substantially parallel to a substrate, wherein a lower electrode is formed on an insulating film on the substrate, Forming a film to cover the lower electrode, forming an opening in the insulating film, exposing the lower electrode on a bottom surface of the opening, and forming a first conductive type in a lower portion of the opening. A polycrystalline silicon plug is formed, a polycrystalline silicon plug of the second conductivity type is formed thereon, and a junction surface is formed having a boundary surface between these polycrystalline silicon plugs, which is substantially horizontal to the substrate, as a PN junction surface. Forming an upper electrode connected to the polycrystalline silicon plug of the second conductivity type on the insulating film, wherein the step of forming the bonding surface comprises forming the polycrystalline silicon of the first conductivity type. The opening is filled with a plug, and the second conductive type Implanting the first conductive type polycrystalline silicon plug to convert the upper portion of the first conductive type polycrystalline silicon plug to the second conductive type to form the second conductive type polycrystalline silicon plug. It is also a method for manufacturing a semiconductor device having a poly-type diode. In such a manufacturing method, since a PN junction is formed by changing a part of the first conductivity type polycrystalline silicon plug to the second conductivity type, the manufacturing process can be simplified.

The present invention also relates to a method of manufacturing a semiconductor device having a vertical type poly-diode having a PN junction surface substantially parallel to a substrate, comprising: forming a lower electrode on an insulating film on the substrate; Forming a film to cover the lower electrode, forming an opening in the insulating film, exposing the lower electrode on a bottom surface of the opening, and forming a first conductive type in a lower portion of the opening. A polycrystalline silicon plug is formed, a polycrystalline silicon plug of the second conductivity type is formed thereon, and a junction plane having a PN junction plane between the polycrystalline silicon plugs, which is substantially horizontal to the substrate, is formed. Forming an upper electrode connected to the polycrystalline silicon plug of the second conductivity type on the insulating film, the bonding forming step filling the opening. And depositing a polycrystalline silicon layer of the first conductivity type on the insulating film. Then, ions of the second conductivity type are implanted from the upper portion to change the upper portion of the polycrystalline silicon layer of the first conductivity type to the second conductivity type, and the first conductivity type connected to the lower electrode. Forming a polycrystalline silicon plug of the second conductivity type and a second conductivity type polycrystalline silicon plug provided thereon in the opening, wherein the electrode forming step includes the step of forming ions of the second conductivity type. A method of manufacturing a semiconductor device having a vertical poly-diode, comprising a step of processing the polycrystalline silicon layer on the insulating film, which has been changed to the second conductivity type by implantation, into the upper electrode. By using such a manufacturing method, the second conductivity type polycrystalline silicon plug and the upper electrode can be formed at the same time, and the manufacturing process can be simplified.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a partial cross-sectional view of a semiconductor device showing a manufacturing process of the poly-diode according to the first embodiment. The configuration of the semiconductor device will be described with reference to these drawings together with the manufacturing process. In this manufacturing process, first, as shown in FIG. 1A, a film thickness of about 20 is formed on the silicon substrate 1 by using, for example, a field oxidation method or the like.
SiO _{2 of} about 00-5000Å (angstrom)
An insulating film 2 is formed. Subsequently, an n-type polycrystalline silicon layer having a thickness of about 1000 ° and an impurity concentration of 5 × 10 ²⁰ / cm ³ is combined with a known CVD (chemical vapor deposition) or PVD (physical vapor deposition) method. ) Formed with a film thickness of about 1000 °
Si layers are sequentially stacked on the SiO ₂ insulating film 2. Furthermore,
Using photolithography technology, a lower electrode composed of an n-type polycrystalline silicon lower electrode 3 and a WSi lower electrode 4 is formed at a predetermined position. Subsequently, an interlayer insulating film 5 made of SiO ₂ having a thickness of about 5000 ° is deposited by a CVD method or the like. Further, an opening 6 having a diameter of, for example, about 0.3 μm is formed in the interlayer insulating film 5 by using a photoengraving technique.
The surface of the Si electrode 4 is exposed.

Next, for example, as shown in FIG.
The film thickness is about 8000Å and the impurity concentration is about 5 × 10 ²⁰ / cm
³ of the n-type polycrystalline silicon layer, further deposited by CVD or the like so as to cover the interlayer insulating film 5 above the embedded openings 6, the n-type polycrystalline silicon layer on the interlayer insulating film 5 by etching back method The removal leaves the n-type polycrystalline silicon plug 7 only in the opening 6. Subsequently, for example, the acceleration energy is 20 KeV and the dose is about 5 × 10 ¹⁵ / c so that about the upper half of the polycrystalline silicon plug 7 is inverted to p-type.
BF ₂ is ion-implanted under the condition of m ² , and a p-type polycrystalline silicon plug 8 is formed in substantially the upper half of the n-type polycrystalline silicon plug 7. As a result, the n-type polycrystalline silicon plug 7 and p
The mold polycrystalline silicon plug 8 forms a substantially parallel junction with the silicon substrate 1, which becomes a PN junction surface 9. In this case, since the cross-sectional area of the opening 6 is the area of the PN junction, the cross-sectional area of the opening 6 can be set so as to have a desired PN junction area.

Finally, as shown in FIG. 1C, an aluminum layer is formed to a thickness of, for example, about 3500 ° on the interlayer insulating film 5 so as to be connected to the upper end of the p-type polycrystalline silicon plug 8. The upper electrode 10 is processed using a plate making technique. Through these steps, the vertical type poly diode according to the present embodiment is completed.

As described above, in the vertical type poly-diode of FIG. 1 (c), since a substantially horizontal cross section of the polycrystalline silicon plug in the silicon substrate 1 is a PN junction surface, it is incorporated in a highly integrated semiconductor device. Even in this case, the PN junction area can be made larger than that of the lateral type poly-diode. Also, by changing the diameter of the polycrystalline silicon plug, a desired bonding area can be obtained, and the degree of freedom in designing the bonding area increases.

Embodiment 2 FIG. FIG. 2 is a partial cross-sectional view of the semiconductor device, illustrating a manufacturing process of the polysilicon diode according to the second embodiment. In the present manufacturing process, first, as shown in FIG.
An SiO ₂ insulating film 2 is laminated on a silicon substrate 1,
An n-type polycrystalline silicon lower electrode 3 is formed in a predetermined region on the iO ₂ insulating film 2. Subsequently, an opening 6 is formed in the interlayer insulating film 5 formed on the n-type polycrystalline silicon lower electrode 3 so that the lower electrode 3 is exposed.

Next, as shown in FIG. 2 (b), by the same steps as the first embodiment, the opening 6, n-type polycrystalline silicon impurity concentration of about 5 × 10 ²⁰ / cm ³ The plug 7 is formed.

Next, for example, a film thickness of about 2000 Å, the impurity concentration of p-type polycrystalline silicon layer of about 5 × 10 ²⁰ / cm ^3, so as to be connected to the upper surface of the n-type polycrystalline silicon plug 7 entire 2 (c) using photoengraving technology
Upper electrode 11 made of p-type polycrystalline silicon as shown in FIG.
To form Through these steps, the vertical type poly diode according to the present embodiment is completed.

As described above, in the polydiode of FIG. 2C, the junction surface between the n-type polycrystalline silicon plug 7 and the p-type polycrystalline silicon upper electrode 11 is a PN junction surface.
Even when the semiconductor device is incorporated in a highly integrated semiconductor device, the PN junction area can be made larger than that of the lateral type poly-diode. Also, by changing the diameter of the polycrystalline silicon plug, a desired bonding area can be obtained, and the degree of freedom in designing the bonding area increases. In particular, in the process according to the present embodiment, ion implantation is not used, and the manufacturing process can be simplified as compared with the first embodiment.

Embodiment 3 FIG. 3 is a partial cross-sectional view of the semiconductor device illustrating a manufacturing process of the polysilicon diode according to the third embodiment. In the present manufacturing process, first, as shown in FIG.
An SiO ₂ insulating film 2 is laminated on a silicon substrate 1,
An n-type polycrystalline silicon lower electrode 3 is formed in a predetermined region on the iO ₂ insulating film 2. Subsequently, an opening 6 is formed in the interlayer insulating film 5 formed on the n-type polycrystalline silicon lower electrode 3 so that the lower electrode 3 is exposed. Subsequently, an n concentration of about 5 × 10 ²⁰ / cm ³ is set so as to fill the opening 6.
Type polycrystalline silicon is deposited on interlayer insulating film 5 by a CVD method or the like. Next, the n-type polycrystalline silicon is processed into a shape as shown in FIG. Further, the acceleration energy is 20 KeV and the dose is about 5 × 10 ¹⁵ / c.
BF ₂ is ion-implanted under the condition of m ² .

As a result, as shown in FIG. 3B, the conductivity type of the n-type polycrystalline silicon above the n-type polycrystalline silicon buried in the opening 6 and on the interlayer insulating film 5 is inverted. ,
It becomes the p-type polycrystalline silicon layer 12. The portion of the p-type polycrystalline silicon layer 12 buried in the opening 6 becomes a p-type polycrystalline silicon plug, and forms a PN junction surface at a connection surface with the n-type polycrystalline silicon plug 7. The portion laminated on the interlayer insulating film 5 is patterned to form a p-type polycrystalline silicon upper electrode. Through these steps, the vertical type poly diode according to the present embodiment is completed.

As described above, in the vertical type poly-diode of FIG. 3B, since the junction surface between the n-type polycrystalline silicon plug 7 and the p-type polycrystalline silicon layer 12 is a PN junction surface, high integration is achieved. PN junction area can be increased as compared with a lateral type poly-diode even when incorporated in a semiconductor device that has been manufactured. Also, by changing the diameter of the polycrystalline silicon plug, a desired bonding area can be obtained, and the degree of freedom in designing the bonding area increases. In particular, in the process according to the present embodiment, the p-type polycrystalline silicon plug buried in the opening and the p-type polycrystalline silicon upper electrode formed on the insulating layer are connected to the p-type polycrystalline silicon layer 12. However, since they are integrally formed by one ion implantation, the manufacturing process can be simplified.

Embodiment 4 FIG. 4 is a partial cross-sectional view of the semiconductor device illustrating the steps of manufacturing the polydiode according to the fourth embodiment. In this manufacturing process, first, using the same process as in the second embodiment, SiO 2 is formed on the silicon substrate 1.
_Two insulating films 2 are stacked, and an n-type polycrystalline silicon lower electrode 3 is formed in a predetermined region on the SiO ₂ insulating film 2.

Next, as shown in FIG. 4 (b), SiO ₂
An interlayer insulating film 5 is formed, and an opening 6 is formed by photolithography so that the n-type polycrystalline silicon lower electrode 3 is exposed. The opening 6 has, for example, a diameter of about 0.3 μm.
m, and after etching the interlayer insulating film 5, n
The lower portion of the n-type polycrystalline silicon electrode 3 is etched by 500 ° in the depth direction to form an opening 6 ′ also in the n-type polycrystalline silicon lower electrode 3.

Next, as shown in FIG. 4 (c), a film thickness of about 8000 Å, the impurity concentration of the n-type polycrystalline silicon layer of about 5 × 10 ²⁰ / cm ^3, an interlayer to embed an opening 6 The n-type polycrystalline silicon layer on the interlayer insulating film 5 is removed by, for example, an etch-back method so that the p-type polycrystalline silicon plug 7 is left only in the opening 6 by depositing on the insulating film 5 by a CVD method or the like. . In this case, the p-type polycrystalline silicon plug 7
Is an opening 6 ′ provided in the n-type polycrystalline silicon lower electrode 3.
Embedded in On the other hand, in order to form a lead from n-type polycrystalline silicon lower electrode 3, opening 1 is formed in interlayer insulating film 5 so as to reach n-type polycrystalline silicon lower electrode 3.
3 is formed.

Next, as shown in FIG.
3, tungsten is buried to form a tungsten plug 14, and finally, an aluminum electrode 11 is formed on the p-type polycrystalline silicon plug 7 and the tungsten plug 14, respectively. Through these steps, the vertical type poly diode according to the present embodiment is completed.

As described above, in the vertical type poly-diode of FIG. 4D, the p-type polycrystalline silicon plug 7 and the n-type polycrystalline silicon lower electrode 12 are connected to the lower surface of the end of the p-type polycrystalline silicon plug 7. In addition, since the bonding surface is formed on the side surface of the end, the PN bonding surface can be made wider. For this reason, even when incorporated in a highly integrated semiconductor device, the area of the PN junction surface can be increased as compared with the lateral type poly-diode. In addition, Japanese Patent Application Laid-Open No. 1-19679
No. 5 also discloses a vertical poly diode,
The vertical type poly-diode according to the present invention is different from the poly-diode described in the above publication in that it is used for a highly integrated semiconductor device in which the diameter of a plug is 0.3 μm, for example. That is, since the present invention relates to a highly integrated and small-sized poly-diode, not only the lower surface of the end of the polycrystalline silicon plug but also the side surface of the end of the polycrystalline silicon plug have a PN.
Forming the junction surface can greatly contribute to the current characteristics of the diode.

By changing the diameter of the polycrystalline silicon plug, a desired bonding area can be obtained, and the degree of freedom in designing the bonding area increases.

Further, in the conventional lateral polysilicon diode, n-type ions and p-type ions are respectively implanted into predetermined polysilicon regions using a photolithography technique, so that the n-type polysilicon region 103 and the p-type A crystalline silicon region 104 is formed. For this reason, considering the shift of the position of the PN junction due to the shift of the photolithography, the n-type polysilicon region 10
The distance between the contact 109 and the contact 109 formed on the p-type polycrystalline silicon region 104 needs to be at least about 1 μm, for example, in a 0.35 μm rule process. Further, the contact 109 is formed from the end of the n-type polycrystalline silicon region 103 and the end of the p-type polycrystalline silicon region 104.
It must be formed with a margin of at least about 0.3 μm. Therefore, the diameter of the contact 109 is set to 0.3 μm.
In the case of m, as shown in FIG. 5, the lateral length of the polysilicon formation region needs to be at least 2.2 μm.

On the other hand, the polysilicon regions 103 and 104
When the film thickness is 1000 °, for example, the area is 1 μm
^In order to form ^two PN junctions, the length of the polysilicon formation region in the vertical direction must be 10 μm.

Accordingly, the area of the lateral type polysilicon diode forming region is 2.2 μm × 10 μm, that is, 22 μm ² .

On the other hand, in the vertical polysilicon diode according to the present embodiment, the cross-sectional area of the contact 109 is PN.
Since the contact area is equal to the contact area (here, the area of the PN junction surface formed on the plug side wall is not considered), when the contact diameter is 0.3 μm, the PN junction area per contact is (0.3 / 2 μm) ² × 3.14, approx.
07 μm ² . Therefore, to obtain a PN junction area of 1 μm ² , 15 contacts 109 are required.

This is set to 0.
When formed according to the 35 μm rule, the interval between the contacts 109 must be at least 0.8 μm in order to prevent interference between the adjacent contacts 109 during photolithography. Therefore, as shown in FIG. 6, the margin from the end of the polysilicon region is set to 0.3 μm and the contact 109
Is 5 × 3, the horizontal length is 4.1 μ
m, a polysilicon region having a vertical length of 2.5 μm is required.

Therefore, the area of the vertical polysilicon diode forming region is 4.1 μm × 2.5 μm, which is 10.25 μm ² . That is, the area of the poly-diode formation region can be reduced to about 47% as compared with the horizontal type poly-diode. This is particularly advantageous when a charge pump type booster circuit is formed in a highly integrated semiconductor memory device.
Although the cross section of the contact 109 is shown as a square in the drawing, the actual shape is a circle. By forming a PN junction surface also on the plug side wall portion, the area of the vertical polysilicon diode formation region can be further reduced.

In the first to fourth embodiments, the case where three polycrystalline silicon plugs are formed has been described.
The number of polycrystalline silicon plugs may be one or more. Further, the conductivity types of the n-type conductor and the p-type conductor can be reversed.

[0037]

As is clear from the above description, in the vertical type poly-diode according to the present invention, since the horizontal plane of the polycrystalline silicon plug is the PN junction, the area of the PN junction is smaller than that of the horizontal type poly-diode. It is possible to increase the amount of current flowing through the diode. This is particularly effective when incorporated into a highly integrated semiconductor device.

By changing the diameter of the polycrystalline silicon plug, a desired bonding area can be easily obtained.
The required amount of current can be obtained.

Further, in the vertical polydiode according to the present invention, a part of the side surface of the polycrystalline silicon plug also becomes a PN junction surface, so that the PN junction area can be further increased and the amount of current flowing through the diode can be increased.

[Brief description of the drawings]

FIG. 1 is a partial cross-sectional view illustrating a manufacturing process of a vertical polysilicon diode according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing a step of manufacturing the vertical type poly-diode according to the second embodiment of the present invention.

FIG. 3 is a partial cross-sectional view showing a step of manufacturing the vertical type polysilicon diode according to the third embodiment of the present invention.

FIG. 4 is a partial cross-sectional view showing a manufacturing step of a vertical poly-diode according to a fourth embodiment of the present invention.

FIG. 5 is a plan view of a horizontal type poly diode.

FIG. 6 is a plan view of a vertical type poly diode.

FIG. 7 is a cross-sectional view of a conventional horizontal poly diode.

FIG. 8 is a plan view of a conventional horizontal poly diode.

[Explanation of symbols]

Reference Signs List 1 silicon substrate, 2 SiO ₂ insulating film, 3 n-type polycrystalline silicon lower electrode, 4 WSi lower electrode, 5 interlayer insulating film, 6, 6 ′ opening, 7 n-type polycrystalline silicon plug, 8 p-type polycrystalline silicon Plug, 9 PN junction surface,
10 aluminum upper electrode, 11 p-type polycrystalline silicon upper electrode, 12 p-type polycrystalline silicon layer, 13 opening, 14 tungsten plug.

Claims (7)

[Claims] 1. A semiconductor device including a vertical poly-diode having a PN junction surface formed between a first conductivity type polysilicon region and a second conductivity type polysilicon region provided on a substrate. A lower electrode stacked on the substrate, an insulating layer formed to cover the lower electrode, an upper electrode stacked on the insulating layer, and an opening provided in the insulating layer Embedded therein, the upper and lower ends of which include a plug connected to the upper electrode and the lower electrode, respectively, wherein the plug is made of polycrystalline silicon, and the upper end surface, the lower end surface of the plug, or the substrate surface. A semiconductor device including a vertical poly-diode, wherein a cross section of the plug in a substantially horizontal direction is a PN junction surface. A second conductive type polycrystalline silicon buried on the substrate side of the opening, and a second conductive type polycrystalline silicon buried thereon; 2. The semiconductor device according to claim 1, wherein a boundary surface between these polycrystalline silicons is the PN junction surface. 3. The plug according to claim 1, wherein the plug is made of polycrystalline silicon of a first conductivity type, the upper electrode is made of polycrystalline silicon of a second conductivity type, and a boundary surface between these polycrystalline silicon is a PN junction surface. The semiconductor device according to claim 1, wherein: 4. The plug is made of polycrystalline silicon of a first conductivity type, the lower electrode is made of polycrystalline silicon of a second conductivity type, and the boundary surface between these polycrystal silicon is the PN junction surface. The semiconductor device according to claim 1, wherein: 5. The plug according to claim 4, wherein a lower end of the plug is embedded in the lower electrode, and a boundary surface between a side wall of the lower end and the lower electrode further serves as the PN junction surface. 13. The semiconductor device according to claim 1. 6. A method for manufacturing a semiconductor device having a vertical poly-diode having a PN junction surface substantially parallel to a substrate, comprising: forming a lower electrode on the substrate; forming an insulating film on the lower electrode; Forming an opening in the insulating film, exposing the lower electrode on the bottom surface of the opening; forming a first conductivity type polycrystalline silicon plug below the opening; Forming a second conductivity type polycrystalline silicon plug thereon, and forming a PN junction surface between the polycrystalline silicon plugs, which is substantially horizontal to the substrate, and forming a PN junction surface on the insulating film. Forming an upper electrode connected to the second conductivity type polycrystalline silicon plug, wherein the bonding surface forming step fills the opening with the first conductivity type polycrystalline silicon plug; Implanting ions of the second conductivity type from above, A method of manufacturing a semiconductor device having a vertical polysilicon diode, comprising a step of converting an upper portion of a conductive type polycrystalline silicon plug to a second conductive type to form the second conductive type polycrystalline silicon plug. . 7. A method for manufacturing a semiconductor device having a vertical poly-diode having a PN junction surface substantially parallel to a substrate, comprising: forming a lower electrode on the substrate; forming an insulating film on the lower electrode; Forming an opening in the insulating film, exposing the lower electrode on the bottom surface of the opening; forming a first conductivity type polycrystalline silicon plug below the opening; Forming a second conductivity type polycrystalline silicon plug thereon, and forming a PN junction surface at a boundary between these polycrystalline silicon plugs which is substantially horizontal to the substrate; Forming an upper electrode connected to the polycrystalline silicon plug of the second conductivity type, wherein the step of forming the junction forms a plurality of polycrystal silicon plugs of the first conductivity type so as to fill the opening. A crystalline silicon layer is deposited on the insulating film, and a Conductivity type by implanting ions alter the top of the first conductivity type polycrystalline silicon layer on the second conductivity type,
Forming a first conductivity type polycrystalline silicon plug connected to the lower electrode and a second conductivity type polycrystalline silicon plug provided thereon in the opening; A step of processing the polycrystalline silicon layer on the insulating film, which has been changed to the second conductivity type by the implantation of the ions of the second conductivity type, into the upper electrode. A method for manufacturing a semiconductor device having a polydiode.