JP2001028312A - Manufacture of laminated electronic component - Google Patents

Manufacture of laminated electronic component

Info

Publication number
JP2001028312A
JP2001028312A JP2000200694A JP2000200694A JP2001028312A JP 2001028312 A JP2001028312 A JP 2001028312A JP 2000200694 A JP2000200694 A JP 2000200694A JP 2000200694 A JP2000200694 A JP 2000200694A JP 2001028312 A JP2001028312 A JP 2001028312A
Authority
JP
Japan
Prior art keywords
hole
electrode
internal electrode
forming
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000200694A
Other languages
Japanese (ja)
Inventor
Yoichi Yamamoto
洋一 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP2000200694A priority Critical patent/JP2001028312A/en
Publication of JP2001028312A publication Critical patent/JP2001028312A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated electronic component which can connect internal and external electrodes simply and reliably with high connection reliability. SOLUTION: In this laminated electronic component, a lead-out electrode 2a of an internal electrode 2 and a through-hole 7 connected to an internal electrode 2 are connected to an external electrode 4, so that the connection area can be made larger than that of the prior art by an amount corresponding to the connection area of the through-hole 7. Furthermore, since it is sufficient that it only forms the through-hole 7, the connection area between the internal and external electrodes 2 and 4 can be made large easily.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、積層チップインダ
クタ、積層コンデンサ等の積層型電子部品の製造方法に
関し、その内部電極と外部電極との接続構造を改良した
ものに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer electronic component such as a multilayer chip inductor and a multilayer capacitor, and more particularly to an improved method for connecting internal electrodes to external electrodes.

【0002】[0002]

【従来の技術】従来、この種の積層チップインダクタ、
例えばチップビーズとして図11乃至図14に示すもの
が知られている。
2. Description of the Related Art Conventionally, this kind of multilayer chip inductor,
For example, chip beads shown in FIGS. 11 to 14 are known.

【0003】このチップビーズを製造するときは、ま
ず、図11に示すように、磁性体グリーンシート1a,
1b,1cを用意し、そのうちの一枚の磁性体グリーン
シート1bに導電ペーストを塗布し内部電極2のパター
ンを多数印刷する。次いで、この印刷された磁性体グリ
ーンシート1b及びこれを挟む保護用の各磁性体グリー
ンシート1a,1cを実線矢印に示すように積層固着す
る。その後、磁性体グリーンシート1bが図11の一点
鎖線に沿って分離されるよう、この積層体を切断する。
これにより、図12及び図13に示すようなチップビー
ズ素体3が形成される。
When manufacturing the chip beads, first, as shown in FIG. 11, a magnetic green sheet 1a,
1b and 1c are prepared, a conductive paste is applied to one of the magnetic green sheets 1b, and a large number of patterns of the internal electrodes 2 are printed. Next, the printed magnetic green sheets 1b and the protective magnetic green sheets 1a and 1c sandwiching the printed magnetic green sheets 1b are laminated and fixed as indicated by solid arrows. Thereafter, the laminate is cut so that the magnetic green sheet 1b is separated along the dashed line in FIG.
Thus, the chip bead element body 3 as shown in FIGS. 12 and 13 is formed.

【0004】このように形成されたチップビーズ素体3
を乾燥、焼成し、その後、このチップビーズ素体3の外
側に内部電極2の端部(引き出し電極部2a)に接続す
る外部電極4を図14に示すように塗布形成する。最後
に、この外部電極4の外側にはんだメッキを行いチップ
ビーズが製造される。
[0004] The chip bead element body 3 thus formed
Then, an external electrode 4 connected to the end of the internal electrode 2 (lead electrode portion 2a) is formed on the outside of the chip bead body 3 as shown in FIG. Finally, solder plating is performed on the outside of the external electrodes 4 to produce chip beads.

【0005】[0005]

【発明が解決しようとする課題】このようにチップビー
ズを製造するときは、外部電極4を塗布する前にペース
ト状の内部電極2が乾燥、焼成されるため、この焼成等
により内部電極2が収縮し、引き出し電極部2aの電極
面積が減少したり、或いは、図13に示すように引き出
し電極部2aがチップビーズ素体3の内側に引き込まれ
てしまう。
When the chip beads are manufactured as described above, the paste-like internal electrode 2 is dried and fired before the external electrode 4 is applied. As a result, the electrode area of the extraction electrode portion 2a is reduced, or the extraction electrode portion 2a is pulled into the chip bead body 3 as shown in FIG.

【0006】このような状態で外部電極4を塗布して
も、図14に示すように引き出し電極部2aと外部電極
4との間に隙間5ができ、接続不良を起こすおそれがあ
った。また、この内部電極2と外部電極4との接続信頼
性は、大きな電流を使用するとき特に高いものを要求さ
れるが、従来のチップビーズではその要求を満足させる
ことができず、チップビーズの高電流仕様の製造には不
向きなものとなっていた。
[0006] Even when the external electrode 4 is applied in such a state, a gap 5 is formed between the extraction electrode portion 2a and the external electrode 4 as shown in FIG. In addition, the connection reliability between the internal electrode 2 and the external electrode 4 is required to be particularly high when a large current is used. However, the conventional chip beads cannot satisfy the demand, and the chip beads cannot be used. It was unsuitable for manufacturing high-current specifications.

【0007】このようなことから、従来は、この引き出
し電極部2aの接続面積をその厚さ方向にかせぐため、
引き出し電極部2aを通常よりも厚膜に形成したり、或
いは、引き出し電極部2aに導電ペーストを複数回に亘
って塗布したり、更には、引き出し電極部2aを複数の
導電部材で積層する構造が採用されていた。
For this reason, conventionally, in order to increase the connection area of the extraction electrode portion 2a in the thickness direction,
A structure in which the extraction electrode portion 2a is formed thicker than usual, or a conductive paste is applied to the extraction electrode portion 2a a plurality of times, and further, the extraction electrode portion 2a is laminated with a plurality of conductive members. Was adopted.

【0008】しかしながら、引き出し電極部2aを通常
よりも厚膜に形成するときは、引き出し電極部2aを含
む内部電極2全体を一回のスクリーン印刷等で形成でき
ないし、また、導電ペーストを複数回に亘り塗布する構
造では、内部電極2全体を印刷するマスクスクリーン
と、これとは別個に引き出し電極部2aのみを印刷する
マスクスクリーンを用意しなければならず、製造コスト
が割高になるという問題点を有していた。更に、引き出
し電極部2aに導電部材を積層する構造では、この引き
出し電極部2aに対応する導電部材を予め用意し、これ
を積層しなければならず、その製造工程が複雑になると
いう問題点を有していた。本発明の目的は前記従来の課
題に鑑み、内部電極と外部電極とを簡単かつ確実に接続
でき、接続信頼性の高い積層型電子部品の製造方法を提
供することにある。
However, when the extraction electrode portion 2a is formed to be thicker than usual, the entire internal electrode 2 including the extraction electrode portion 2a cannot be formed by one screen printing or the like, and the conductive paste is applied a plurality of times. In such a structure, a mask screen for printing the entire internal electrode 2 and a mask screen for printing only the lead-out electrode portion 2a must be prepared separately, which increases the manufacturing cost. Had. Further, in the structure in which a conductive member is laminated on the extraction electrode portion 2a, a conductive member corresponding to the extraction electrode portion 2a must be prepared in advance and laminated, and the manufacturing process becomes complicated. Had. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a laminated electronic component that can easily and surely connect an internal electrode and an external electrode and has high connection reliability in view of the above-mentioned conventional problems.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に、請求項1では、絶縁シートに内部電極用の導体を形
成する工程と、導体が形成された絶縁シートを少なくと
も1枚以上含む複数の絶縁シートを積層してシート積層
体を形成する工程と、シート積層体を単位部品ごとに裁
断して積層体を作成する工程と、積層体の外面に内部電
極と接続するように外部電極を形成する工程とを備えた
積層型電子部品の製造方法において、前記絶縁シートへ
の導体形成工程に先立ち、該絶縁シートの前記裁断工程
における切断線上で且つ内部電極の端部に対応する位置
にスルーホールを形成する工程を備え、前記絶縁シート
への導体形成工程では内部電極用の導体を前記スルーホ
ールに充填するとともに、前記外部電極の形成工程では
積層体の表面に露出する内部電極及びスルーホールに接
続するように外部電極を形成することを特徴とするもの
を提案する。
In order to achieve the above object, according to the present invention, a step of forming a conductor for an internal electrode on an insulating sheet and a step of forming at least one insulating sheet on which the conductor is formed are provided. A step of forming a sheet laminate by laminating the insulating sheets, a step of cutting the sheet laminate into unit parts to form a laminate, and an external electrode connected to an internal electrode on an outer surface of the laminate. Forming a conductor on the insulating sheet prior to the step of forming a conductor on the insulating sheet, the through-hole is formed at a position corresponding to an end of the internal electrode on a cutting line in the cutting step of the insulating sheet. A step of forming a hole; in the step of forming a conductor in the insulating sheet, a conductor for an internal electrode is filled in the through-hole; Suggest that, and forming external electrodes so as to be connected to the internal electrodes and the through-hole is.

【0010】本発明によれば、積層体の外面には内部電
極と共に該内部電極と同一材料が充填されたスルーホー
ルの断面が一体となって露出する。つまり、内部電極と
外部電極との接続面積がスルーホールの断面積分だけ増
大することになる。これにより、外部電極と内部電極と
の接続信頼性を向上させることができる。また、この接
続面積の拡大に際し、スルーホールを形成するだけで良
いため、簡単に接続面積を拡大できる。
According to the present invention, the cross section of the through-hole filled with the same material as the internal electrode is exposed integrally with the internal electrode on the outer surface of the laminate. That is, the connection area between the internal electrode and the external electrode increases by the sectional integral of the through hole. Thereby, the connection reliability between the external electrode and the internal electrode can be improved. In addition, when the connection area is increased, it is only necessary to form a through-hole, so that the connection area can be easily increased.

【0011】本発明の好適な態様の一例として、請求項
2では、請求項1記載の積層型電子部品の製造方法にお
いて、前記積層工程では最上層又は最下層にはスルーホ
ールを形成していない絶縁シートを積層することを特徴
とするものを提案する。
According to a second aspect of the present invention, in the method of manufacturing a multilayer electronic component according to the first aspect, no through hole is formed in the uppermost layer or the lowermost layer in the laminating step. The present invention proposes one characterized by laminating insulating sheets.

【0012】また、請求項3では、請求項1又は2何れ
か1項記載の積層型電子部品の製造方法において、前記
絶縁シートは磁性体グリーンシートからなることを特徴
とするものを提案する。
According to a third aspect of the present invention, there is provided a method of manufacturing a multilayer electronic component according to the first aspect, wherein the insulating sheet is made of a magnetic green sheet.

【0013】[0013]

【発明の実施の形態】図1乃至図9の(a)(b)は本発明に
係る積層型電子部品の製造方法の一実施例を示すもの
で、図1は磁性体グリーンシートの積層工程を示す斜視
図、図2はチップビーズ素体の斜視図、図3は図2のA
−A線矢視方向の断面図、図4はチップビーズの断面
図、図5は内部電極及びスルーホールの平面図、図6の
(a)(b)は内部電極及びスルーホールの接続部分を従来例
と比較した断面図、図7の(a)(b)はチップビーズのたわ
み試験及び試験結果を示す図、図8はたわみ試験による
外部電極の剥離状態を示す従来の断面図、図9はたわみ
試験による外部電極の剥離状態を示す本実施例の断面図
である。なお、従来例と同一構成部分は同一符号をもっ
て表す。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 9 (a) and 9 (b) show an embodiment of a method of manufacturing a laminated electronic component according to the present invention. FIG. 1 shows a process of laminating a magnetic green sheet. 2 is a perspective view of the chip bead body, and FIG. 3 is a perspective view of FIG.
FIG. 4 is a sectional view of a chip bead, FIG. 5 is a plan view of an internal electrode and a through hole, and FIG.
7 (a) and 7 (b) are cross-sectional views comparing a connection portion of an internal electrode and a through hole with a conventional example, FIGS. 7 (a) and 7 (b) show a deflection test and test results of chip beads, and FIG. FIG. 9 is a cross-sectional view of a conventional example showing a peeling state of an external electrode by a test, and FIG. The same components as those of the conventional example are denoted by the same reference numerals.

【0014】本実施例に係るチップビーズ素体も従来例
と同様に製造されるもので、図1に示すように、3枚の
磁性体グリーンシート1a,1b,1cを実線矢印に示
すように積層固着し、次いで、内部電極2が印刷された
磁性体グリーンシート1bを図1の一点鎖線に沿って分
離するようこの積層体を切断し、図2に示すようなチッ
プビーズ素体6を形成する。
The chip bead body according to the present embodiment is also manufactured in the same manner as the conventional example. As shown in FIG. 1, three magnetic green sheets 1a, 1b and 1c are arranged as shown by solid arrows. The laminated body is cut and fixed so that the magnetic green sheet 1b on which the internal electrodes 2 are printed is separated along the dashed line in FIG. 1 to form a chip bead body 6 as shown in FIG. I do.

【0015】ここで、本実施例の特徴とするところは、
内部電極2を印刷した磁性体グリーンシート1bにおい
て、その内部電極2の端部である引き出し電極部2aに
スルーホール7を形成した点にある。
The features of this embodiment are as follows.
In the magnetic green sheet 1b on which the internal electrode 2 is printed, a through hole 7 is formed in a lead electrode portion 2a which is an end of the internal electrode 2.

【0016】即ち、このスルーホール7は磁性体グリー
ンシート1bの厚さ方向に円筒状に形成されたもので、
図5に示すように、積層体の切断線がスルーホール7の
中央を通るよう配置されている。これにより、図2及び
図3に示すように、チップビーズ素体6の側面に外部電
極4への接続部分が露出する。この接続部分は引き出し
電極部2aとスルーホール7とからなるため、その接続
面積が、図4に示すように、スルーホール7の分、従来
より広くなる。
That is, the through hole 7 is formed in a cylindrical shape in the thickness direction of the magnetic green sheet 1b.
As shown in FIG. 5, the cut line of the stacked body is arranged to pass through the center of the through hole 7. As a result, as shown in FIGS. 2 and 3, a connection portion to the external electrode 4 is exposed on the side surface of the chip bead element body 6. Since this connection portion is composed of the extraction electrode portion 2a and the through hole 7, the connection area thereof is wider than that of the related art as shown in FIG.

【0017】この接続面積の拡大割合を図5及び図6の
(a)(b)に基づいて説明する。ここで、本実施例(図6の
(a))及び従来例(図6の(b))の両者とも、その引き出
し電極部2aの幅寸法が0.92mm、厚さ寸法が0.02mmとな
っており、その接続面積は0.0184mm2(0.92mm×0.02m
m)となる。一方、本実施例のスルーホール7の直径が
0.25mm、厚さ寸法が0.06mmであり、このスルーホール7
の接続面積が0.015mm2(0.25mm×0.06mm)となる。従っ
て、従来の接続面積に対する本実施例の接続面積の拡大
割合は約1.82[(0.0184mm2+0.015mm2)/0.0184mm2
倍となる。なお、一点鎖線は切断線を示している。
The rate of increase of the connection area is shown in FIGS.
A description will be given based on (a) and (b). Here, in the present embodiment (FIG. 6)
In both (a)) and the conventional example ((b) of FIG. 6), the width of the lead electrode portion 2a is 0.92 mm, the thickness is 0.02 mm, and the connection area is 0.0184 mm 2 ( 0.92mm × 0.02m
m). On the other hand, the diameter of the through hole 7 of this embodiment is
0.25mm, thickness is 0.06mm.
Has a connection area of 0.015 mm 2 (0.25 mm × 0.06 mm). Therefore, expansion ratio of the connection area of the present embodiment for conventional connection area about 1.82 [(0.0184mm 2 + 0.015mm 2 ) /0.0184mm 2]
Double. The dashed line indicates the cutting line.

【0018】このように、本実施例に係るチップビーズ
は外部電極4との接続面積がスルーホール7の分広くな
るため、チップビーズの製造工程で内部電極2が収縮し
チップビーズ素体6側に引き込まれても、その分このス
ルーホール7の接続面積でカバーでき、内部電極2と外
部電極4の接続信頼性が向上する。
As described above, since the chip bead according to the present embodiment has a larger connection area with the external electrode 4 due to the through hole 7, the internal electrode 2 shrinks in the chip bead manufacturing process and the chip bead body 6 side , The connection area of the through hole 7 can cover the connection area, and the connection reliability between the internal electrode 2 and the external electrode 4 is improved.

【0019】このような接続信頼性を確認するため、図
7の(a)に示すたわみ試験を行った。試料として本実施
例のチップビーズと従来のチップビーズをそれぞれ10
個宛用意し、これを基板にはんだ付けし、この基板のた
わみによる各チップビーズの機械的破壊及び電気的破壊
を計数した。この結果、図7の(b)に示すように、本実
施例のチップビーズはたわみ量が12mm以上となった
ときのみ機械的破壊及び電気的破壊が起こるのに対し
て、従来のチップビーズはたわみ量が12mm未満で、
機械的破壊及び電気的破壊が5個程度起きている。よっ
て、このたわみ試験からも本実施例に係るチップビーズ
が接続信頼性に優れていることが理解できる。
In order to confirm such connection reliability, a bending test shown in FIG. 7A was performed. The chip beads of the present example and the conventional chip beads were
Each chip bead was soldered to a substrate, and the mechanical and electrical destruction of each chip bead due to the deflection of the substrate was counted. As a result, as shown in FIG. 7B, the chip beads of the present example cause mechanical and electrical destruction only when the deflection amount is 12 mm or more, whereas the conventional chip beads have The amount of deflection is less than 12 mm,
About five mechanical and electrical destructions have occurred. Therefore, it can be understood from the deflection test that the chip beads according to the present example have excellent connection reliability.

【0020】また、このたわみ試験による機械的破壊及
び電気的破壊を図8の(a)(b)及び図9の(a)(b)を参照し
て説明する。図8の(a)に示すように、従来のチップビ
ーズを基板8にはんだ9で固着した後、図8の(b)に示
すように、白抜き矢印方向に圧力を加えたとき、はんだ
9及び外部電極4に実線矢印の方向に力が加わる。これ
により、チップビーズ素体6から外部電極4が剥離し、
外部電極4と引き出し電極部2aが離隔する。この剥離
により機械的破壊及び電気的破壊が起こる。
The mechanical and electrical destruction by the bending test will be described with reference to FIGS. 8 (a) and (b) and FIGS. 9 (a) and 9 (b). As shown in FIG. 8 (a), after the conventional chip beads are fixed to the substrate 8 with solder 9, as shown in FIG. Further, a force is applied to the external electrode 4 in the direction of the solid arrow. As a result, the external electrode 4 is peeled off from the chip bead element 6,
The external electrode 4 is separated from the extraction electrode portion 2a. This delamination causes mechanical and electrical destruction.

【0021】他方、図9の(a)に示すように、本実施例
のチップビーズを基板8にはんだ9で固着した後、同じ
く図9の(b)に示すように白抜き矢印方向に圧力を加え
たときは、これまた実線矢印方向に力が加わりチップビ
ーズ素体6から外部電極4が剥離することがある。しか
しながら、内部電極2、スルーホール7及び外部電極4
がともにAg等を主成分とする共通の材質からなるた
め、その接続強度が高く、従って本実施例の如く引き出
し電極部2aをスルーホール7にて接触面積が広くとる
ときは、その機械的強度が向上し、その破壊が起こりに
くいことが理解できる。
On the other hand, as shown in FIG. 9 (a), after the chip beads of this embodiment are fixed to the substrate 8 with solder 9, pressure is also applied in the direction of a white arrow as shown in FIG. 9 (b). Is applied, a force is also applied in the direction of the solid arrow, and the external electrode 4 may peel off from the chip bead body 6. However, the inner electrode 2, the through hole 7, and the outer electrode 4
Are made of a common material mainly composed of Ag or the like, so that the connection strength thereof is high. Therefore, when the contact area of the lead-out electrode portion 2a with the through hole 7 is large as in the present embodiment, the mechanical strength is high. Can be understood, and the destruction is unlikely to occur.

【0022】また、その電気的破壊の点を検討するに、
図9の(b)に示すように機械的破壊が起こったときで
も、その接続面積が広い分、内部電極2と外部電極4と
が電気的に接続しており、電気的破壊が起こりにくいこ
とが理解できる。
Further, to examine the point of the electrical breakdown,
Even when mechanical destruction occurs as shown in FIG. 9B, the internal electrode 2 and the external electrode 4 are electrically connected to each other due to the large connection area, so that electrical destruction is unlikely to occur. Can understand.

【0023】更に、内部電極2及びスルーホール7を形
成するときは、磁性体グリーンシート1bにスルーホー
ル用の穴を穿設し、引き出し電極部2aがこの穴に対応
するよう導電ペーストを塗布すれば良く、これにより、
内部電極2及びスルーホール7が一括して形成され、外
部電極4への接続面積を簡単に拡大できる。
Further, when forming the internal electrode 2 and the through hole 7, a hole for a through hole is formed in the magnetic green sheet 1b, and a conductive paste is applied so that the extraction electrode portion 2a corresponds to the hole. All you need is this
The internal electrode 2 and the through hole 7 are formed at a time, and the connection area to the external electrode 4 can be easily enlarged.

【0024】図10の(a)(b)(c)(d)は本実施例に係るチ
ップビーズ素体の他の例を示すものである。図10の
(a)にはチップビーズ素体6aの引き出し電極部2aの
両端にスルーホール7aを形成したものが示されてい
る。このように2箇所にスルーホール7aを形成するこ
とにより、外部電極4への接続面積を更に拡大してい
る。
FIGS. 10 (a), (b), (c) and (d) show another example of the chip bead body according to the present embodiment. Of FIG.
(a) shows a chip bead body 6a in which through-holes 7a are formed at both ends of a lead electrode portion 2a. By forming the through-holes 7a at two locations in this manner, the connection area to the external electrode 4 is further increased.

【0025】図10の(b)には内部電極2の電気特性を
向上させるため引き出し電極部2aの幅を狭くしたチッ
プビーズ素体6bが示されている。このような場合は引
き出し電極部2aの接続面積が非常に狭くなるため、こ
のスルーホール7bは外部電極4との接続のために必要
不可欠なものとなる。
FIG. 10B shows a chip bead body 6b in which the width of the extraction electrode portion 2a is reduced in order to improve the electrical characteristics of the internal electrode 2. In such a case, since the connection area of the extraction electrode portion 2a becomes very small, the through hole 7b is indispensable for connection with the external electrode 4.

【0026】図10の(c)(d)には内部電極を上下2層に
亘って形成したチップビーズ素体6c,6dが示されて
おり、そのうち図10の(c)には上下の引き出し電極部
2aを一体に接続するスルーホール7cが示され、図1
0の(d)には上下の引き出し電極部2aをそれぞれ別個
に接続するスルーホール7dが示されている。このよう
に、内部電極が多層に亘って形成されている場合にあっ
ても、各スルーホール7c,7dで任意に接続面積を拡
大できる。
FIGS. 10 (c) and 10 (d) show chip bead bodies 6c and 6d in which internal electrodes are formed in two upper and lower layers, of which FIG. A through hole 7c for integrally connecting the electrode portion 2a is shown in FIG.
0 (d) shows a through hole 7d for separately connecting the upper and lower extraction electrode portions 2a. As described above, even when the internal electrodes are formed in multiple layers, the connection area can be arbitrarily increased by the through holes 7c and 7d.

【0027】なお、前記実施例では積層型電子部品中、
積層チップインダクタであるチップビーズについて説明
したが、内部電極とこれに接続する外部電極を有するも
のであれば積層コンデンサ等全ての積層型電子部品に適
用できることは言うまでもない。
In the above embodiment, in the multilayer electronic component,
Although the chip beads, which are multilayer chip inductors, have been described, it goes without saying that the present invention can be applied to all multilayer electronic components such as multilayer capacitors as long as they have internal electrodes and external electrodes connected to them.

【0028】[0028]

【発明の効果】以上詳述したように、本発明によれば、
積層体の外面には内部電極と共に該内部電極と同一材料
が充填されたスルーホールの断面が一体となって露出す
る。つまり、内部電極と外部電極との接続面積がスルー
ホールの断面積分だけ増大することになる。これによ
り、外部電極と内部電極との接続信頼性を向上させるこ
とができる。また、この接続面積の拡大に際し、スルー
ホールを形成するだけで良いため、簡単に接続面積を拡
大できる。
As described in detail above, according to the present invention,
On the outer surface of the laminate, a cross section of a through hole filled with the same material as the internal electrode is integrally exposed together with the internal electrode. That is, the connection area between the internal electrode and the external electrode increases by the sectional integral of the through hole. Thereby, the connection reliability between the external electrode and the internal electrode can be improved. In addition, when the connection area is increased, it is only necessary to form a through-hole, so that the connection area can be easily increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る磁性体グリーンシートの積層工程
を示す斜視図
FIG. 1 is a perspective view showing a step of laminating a magnetic green sheet according to the present invention.

【図2】本発明に係るチップビーズ素体の斜視図FIG. 2 is a perspective view of a chip bead body according to the present invention.

【図3】図2のA−A線矢視方向の断面図FIG. 3 is a sectional view taken along the line AA of FIG. 2;

【図4】本発明に係る外部電極が形成されたチップビー
ズ素体の断面図
FIG. 4 is a cross-sectional view of a chip bead body on which external electrodes according to the present invention are formed.

【図5】本発明に係る内部電極及びスルーホールの平面
FIG. 5 is a plan view of an internal electrode and a through hole according to the present invention.

【図6】本発明に係る内部電極及びスルーホールの接続
部分を従来例と比較した断面図
FIG. 6 is a cross-sectional view comparing a connection portion of an internal electrode and a through hole according to the present invention with a conventional example.

【図7】チップビーズのたわみ試験及び試験結果を示す
FIG. 7 is a diagram showing a bending test and test results of chip beads.

【図8】たわみ試験による外部電極の剥離状態を示す従
来の断面図
FIG. 8 is a conventional cross-sectional view showing a peeled state of an external electrode by a bending test.

【図9】たわみ試験による外部電極の剥離状態を示す本
実施例の断面図
FIG. 9 is a cross-sectional view of the present example showing a state of peeling of the external electrode by a deflection test.

【図10】本発明に係るチップビーズ素体の他の例を示
す斜視図
FIG. 10 is a perspective view showing another example of the chip bead body according to the present invention.

【図11】従来の磁性体グリーンシートの積層工程を示
す斜視図
FIG. 11 is a perspective view showing a conventional magnetic green sheet laminating process.

【図12】従来のチップビーズ素体の斜視図FIG. 12 is a perspective view of a conventional chip bead element body.

【図13】図12のA−A線矢視方向の断面図FIG. 13 is a sectional view taken along the line AA of FIG. 12;

【図14】従来の外部電極が形成されたチップビーズ素
体の断面図
FIG. 14 is a cross-sectional view of a conventional chip bead body on which external electrodes are formed.

【符号の説明】[Explanation of symbols]

2…内部電極、2a…引き出し電極部、4…外部電極、
6,6a,6b,6c,6d…チップビーズ素体、7,
7a,7b,7c,7d…スルーホール。
2 ... internal electrode, 2 a ... lead electrode part, 4 ... external electrode,
6, 6a, 6b, 6c, 6d: chip bead body, 7,
7a, 7b, 7c, 7d ... through holes.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 絶縁シートに内部電極用の導体を形成す
る工程と、導体が形成された絶縁シートを少なくとも1
枚以上含む複数の絶縁シートを積層してシート積層体を
形成する工程と、シート積層体を単位部品ごとに裁断し
て積層体を作成する工程と、積層体の外面に内部電極と
接続するように外部電極を形成する工程とを備えた積層
型電子部品の製造方法において、 前記絶縁シートへの導体形成工程に先立ち、該絶縁シー
トの前記裁断工程における切断線上で且つ内部電極の端
部に対応する位置にスルーホールを形成する工程を備
え、 前記絶縁シートへの導体形成工程では内部電極用の導体
を前記スルーホールに充填するとともに、 前記外部電極の形成工程では積層体の表面に露出する内
部電極及びスルーホールに接続するように外部電極を形
成することを特徴とする積層型電子部品の製造方法。
A step of forming a conductor for an internal electrode on an insulating sheet;
A step of forming a sheet laminate by laminating a plurality of insulating sheets including at least one sheet, a step of cutting the sheet laminate into unit parts to form a laminate, and connecting an internal electrode to an outer surface of the laminate. Forming an external electrode on the insulating sheet, prior to the step of forming a conductor on the insulating sheet, corresponding to an end of the internal electrode on a cutting line in the cutting step of the insulating sheet. Forming a through hole at a position where the conductor is to be formed on the insulating sheet. In the step of forming a conductor on the insulating sheet, the conductor for an internal electrode is filled in the through hole, and in the step of forming the external electrode, the inside exposed on the surface of the laminate A method for manufacturing a multilayer electronic component, comprising forming an external electrode so as to be connected to an electrode and a through hole.
【請求項2】 前記積層工程では最上層又は最下層には
スルーホールを形成していない絶縁シートを積層するこ
とを特徴とする請求項1記載の積層型電子部品の製造方
法。
2. The method for manufacturing a multilayer electronic component according to claim 1, wherein in the laminating step, an insulating sheet having no through hole is laminated on the uppermost layer or the lowermost layer.
【請求項3】 前記絶縁シートは磁性体グリーンシート
からなることを特徴とする請求項1又は2何れか1項記
載の積層型電子部品の製造方法。
3. The method according to claim 1, wherein the insulating sheet is made of a magnetic green sheet.
JP2000200694A 2000-01-01 2000-07-03 Manufacture of laminated electronic component Pending JP2001028312A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000200694A JP2001028312A (en) 2000-01-01 2000-07-03 Manufacture of laminated electronic component

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000200694A JP2001028312A (en) 2000-01-01 2000-07-03 Manufacture of laminated electronic component

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP19075794A Division JP3230932B2 (en) 1994-08-12 1994-08-12 Multilayer electronic components

Publications (1)

Publication Number Publication Date
JP2001028312A true JP2001028312A (en) 2001-01-30

Family

ID=18698524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000200694A Pending JP2001028312A (en) 2000-01-01 2000-07-03 Manufacture of laminated electronic component

Country Status (1)

Country Link
JP (1) JP2001028312A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5896710A (en) * 1981-12-04 1983-06-08 Tdk Corp Laminated inductor
JPH06176965A (en) * 1992-12-09 1994-06-24 Tdk Corp Method of fabricating chip electronic parts

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5896710A (en) * 1981-12-04 1983-06-08 Tdk Corp Laminated inductor
JPH06176965A (en) * 1992-12-09 1994-06-24 Tdk Corp Method of fabricating chip electronic parts

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